forked from luck/tmp_suning_uos_patched
iio:adc:ad7949: Add AD7949 ADC driver family
Compatible with AD7682 and AD7689 chips. It is a Analog Devices ADC driver 14/16 bits 4/8 channels with SPI protocol Datasheet of the device: http://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf Signed-off-by: Charles-Antoine Couret <charles-antoine.couret@essensium.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Charles-Antoine Couret
Jonathan Cameron
parent
3138bbc129
commit
7f40e06143
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@ -116,6 +116,16 @@ config AD7923
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To compile this driver as a module, choose M here: the
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module will be called ad7923.
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config AD7949
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tristate "Analog Devices AD7949 and similar ADCs driver"
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depends on SPI
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help
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Say yes here to build support for Analog Devices
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AD7949, AD7682, AD7689 8 Channel ADCs.
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To compile this driver as a module, choose M here: the
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module will be called ad7949.
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config AD799X
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tristate "Analog Devices AD799x ADC driver"
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depends on I2C
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@ -14,6 +14,7 @@ obj-$(CONFIG_AD7766) += ad7766.o
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obj-$(CONFIG_AD7791) += ad7791.o
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obj-$(CONFIG_AD7793) += ad7793.o
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obj-$(CONFIG_AD7887) += ad7887.o
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obj-$(CONFIG_AD7949) += ad7949.o
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obj-$(CONFIG_AD799X) += ad799x.o
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obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
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obj-$(CONFIG_AT91_ADC) += at91_adc.o
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347
drivers/iio/adc/ad7949.c
Normal file
347
drivers/iio/adc/ad7949.c
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@ -0,0 +1,347 @@
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// SPDX-License-Identifier: GPL-2.0
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/* ad7949.c - Analog Devices ADC driver 14/16 bits 4/8 channels
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*
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* Copyright (C) 2018 CMC NV
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*
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* http://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
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*/
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/module.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spi/spi.h>
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#define AD7949_MASK_CHANNEL_SEL GENMASK(9, 7)
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#define AD7949_MASK_TOTAL GENMASK(13, 0)
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#define AD7949_OFFSET_CHANNEL_SEL 7
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#define AD7949_CFG_READ_BACK 0x1
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#define AD7949_CFG_REG_SIZE_BITS 14
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enum {
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ID_AD7949 = 0,
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ID_AD7682,
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ID_AD7689,
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};
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struct ad7949_adc_spec {
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u8 num_channels;
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u8 resolution;
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};
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static const struct ad7949_adc_spec ad7949_adc_spec[] = {
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[ID_AD7949] = { .num_channels = 8, .resolution = 14 },
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[ID_AD7682] = { .num_channels = 4, .resolution = 16 },
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[ID_AD7689] = { .num_channels = 8, .resolution = 16 },
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};
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/**
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* struct ad7949_adc_chip - AD ADC chip
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* @lock: protects write sequences
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* @vref: regulator generating Vref
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* @iio_dev: reference to iio structure
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* @spi: reference to spi structure
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* @resolution: resolution of the chip
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* @cfg: copy of the configuration register
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* @current_channel: current channel in use
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* @buffer: buffer to send / receive data to / from device
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*/
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struct ad7949_adc_chip {
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struct mutex lock;
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struct regulator *vref;
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struct iio_dev *indio_dev;
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struct spi_device *spi;
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u8 resolution;
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u16 cfg;
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unsigned int current_channel;
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u32 buffer ____cacheline_aligned;
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};
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static bool ad7949_spi_cfg_is_read_back(struct ad7949_adc_chip *ad7949_adc)
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{
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if (!(ad7949_adc->cfg & AD7949_CFG_READ_BACK))
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return true;
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return false;
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}
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static int ad7949_spi_bits_per_word(struct ad7949_adc_chip *ad7949_adc)
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{
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int ret = ad7949_adc->resolution;
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if (ad7949_spi_cfg_is_read_back(ad7949_adc))
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ret += AD7949_CFG_REG_SIZE_BITS;
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return ret;
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}
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static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
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u16 mask)
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{
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int ret;
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int bits_per_word = ad7949_spi_bits_per_word(ad7949_adc);
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int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS;
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struct spi_message msg;
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struct spi_transfer tx[] = {
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{
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.tx_buf = &ad7949_adc->buffer,
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.len = 4,
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.bits_per_word = bits_per_word,
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},
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};
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ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask);
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ad7949_adc->buffer = ad7949_adc->cfg << shift;
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spi_message_init_with_transfers(&msg, tx, 1);
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ret = spi_sync(ad7949_adc->spi, &msg);
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/*
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* This delay is to avoid a new request before the required time to
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* send a new command to the device
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*/
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udelay(2);
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return ret;
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}
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static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
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unsigned int channel)
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{
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int ret;
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int bits_per_word = ad7949_spi_bits_per_word(ad7949_adc);
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int mask = GENMASK(ad7949_adc->resolution, 0);
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struct spi_message msg;
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struct spi_transfer tx[] = {
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{
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.rx_buf = &ad7949_adc->buffer,
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.len = 4,
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.bits_per_word = bits_per_word,
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},
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};
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ret = ad7949_spi_write_cfg(ad7949_adc,
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channel << AD7949_OFFSET_CHANNEL_SEL,
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AD7949_MASK_CHANNEL_SEL);
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if (ret)
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return ret;
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ad7949_adc->buffer = 0;
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spi_message_init_with_transfers(&msg, tx, 1);
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ret = spi_sync(ad7949_adc->spi, &msg);
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if (ret)
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return ret;
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/*
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* This delay is to avoid a new request before the required time to
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* send a new command to the device
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*/
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udelay(2);
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ad7949_adc->current_channel = channel;
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if (ad7949_spi_cfg_is_read_back(ad7949_adc))
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*val = (ad7949_adc->buffer >> AD7949_CFG_REG_SIZE_BITS) & mask;
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else
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*val = ad7949_adc->buffer & mask;
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return 0;
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}
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#define AD7949_ADC_CHANNEL(chan) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (chan), \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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}
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static const struct iio_chan_spec ad7949_adc_channels[] = {
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AD7949_ADC_CHANNEL(0),
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AD7949_ADC_CHANNEL(1),
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AD7949_ADC_CHANNEL(2),
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AD7949_ADC_CHANNEL(3),
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AD7949_ADC_CHANNEL(4),
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AD7949_ADC_CHANNEL(5),
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AD7949_ADC_CHANNEL(6),
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AD7949_ADC_CHANNEL(7),
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};
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static int ad7949_spi_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
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int ret;
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if (!val)
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return -EINVAL;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&ad7949_adc->lock);
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ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel);
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mutex_unlock(&ad7949_adc->lock);
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if (ret < 0)
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return ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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ret = regulator_get_voltage(ad7949_adc->vref);
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if (ret < 0)
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return ret;
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*val = ret / 5000;
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return IIO_VAL_INT;
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}
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return -EINVAL;
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}
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static int ad7949_spi_reg_access(struct iio_dev *indio_dev,
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unsigned int reg, unsigned int writeval,
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unsigned int *readval)
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{
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struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
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int ret = 0;
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if (readval)
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*readval = ad7949_adc->cfg;
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else
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ret = ad7949_spi_write_cfg(ad7949_adc,
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writeval & AD7949_MASK_TOTAL, AD7949_MASK_TOTAL);
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return ret;
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}
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static const struct iio_info ad7949_spi_info = {
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.read_raw = ad7949_spi_read_raw,
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.debugfs_reg_access = ad7949_spi_reg_access,
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};
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static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc)
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{
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int ret;
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int val;
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/* Sequencer disabled, CFG readback disabled, IN0 as default channel */
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ad7949_adc->current_channel = 0;
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ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL);
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/*
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* Do two dummy conversions to apply the first configuration setting.
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* Required only after the start up of the device.
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*/
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ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
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ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
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return ret;
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}
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static int ad7949_spi_probe(struct spi_device *spi)
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{
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struct device *dev = &spi->dev;
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const struct ad7949_adc_spec *spec;
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struct ad7949_adc_chip *ad7949_adc;
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struct iio_dev *indio_dev;
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int ret;
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indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc));
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if (!indio_dev) {
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dev_err(dev, "can not allocate iio device\n");
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return -ENOMEM;
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}
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indio_dev->dev.parent = dev;
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indio_dev->dev.of_node = dev->of_node;
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indio_dev->info = &ad7949_spi_info;
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indio_dev->name = spi_get_device_id(spi)->name;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = ad7949_adc_channels;
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spi_set_drvdata(spi, indio_dev);
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ad7949_adc = iio_priv(indio_dev);
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ad7949_adc->indio_dev = indio_dev;
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ad7949_adc->spi = spi;
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spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data];
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indio_dev->num_channels = spec->num_channels;
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ad7949_adc->resolution = spec->resolution;
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ad7949_adc->vref = devm_regulator_get(dev, "vref");
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if (IS_ERR(ad7949_adc->vref)) {
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dev_err(dev, "fail to request regulator\n");
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return PTR_ERR(ad7949_adc->vref);
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}
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ret = regulator_enable(ad7949_adc->vref);
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if (ret < 0) {
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dev_err(dev, "fail to enable regulator\n");
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return ret;
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}
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mutex_init(&ad7949_adc->lock);
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ret = ad7949_spi_init(ad7949_adc);
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if (ret) {
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dev_err(dev, "enable to init this device: %d\n", ret);
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goto err;
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}
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ret = iio_device_register(indio_dev);
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if (ret) {
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dev_err(dev, "fail to register iio device: %d\n", ret);
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goto err;
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}
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return 0;
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err:
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mutex_destroy(&ad7949_adc->lock);
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regulator_disable(ad7949_adc->vref);
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return ret;
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}
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static int ad7949_spi_remove(struct spi_device *spi)
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{
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struct iio_dev *indio_dev = spi_get_drvdata(spi);
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struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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mutex_destroy(&ad7949_adc->lock);
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regulator_disable(ad7949_adc->vref);
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return 0;
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}
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static const struct of_device_id ad7949_spi_of_id[] = {
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{ .compatible = "adi,ad7949" },
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{ .compatible = "adi,ad7682" },
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{ .compatible = "adi,ad7689" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ad7949_spi_of_id);
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static const struct spi_device_id ad7949_spi_id[] = {
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{ "ad7949", ID_AD7949 },
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{ "ad7682", ID_AD7682 },
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{ "ad7689", ID_AD7689 },
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{ }
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};
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MODULE_DEVICE_TABLE(spi, ad7949_spi_id);
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static struct spi_driver ad7949_spi_driver = {
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.driver = {
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.name = "ad7949",
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.of_match_table = ad7949_spi_of_id,
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},
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.probe = ad7949_spi_probe,
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.remove = ad7949_spi_remove,
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.id_table = ad7949_spi_id,
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};
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module_spi_driver(ad7949_spi_driver);
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MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@essensium.com>");
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MODULE_DESCRIPTION("Analog Devices 14/16-bit 8-channel ADC driver");
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MODULE_LICENSE("GPL v2");
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