forked from luck/tmp_suning_uos_patched
Misc fixes, an expansion of perf syscall access to CAP_PERFMON privileged tools,
plus a RAPL HW-enablement for Intel SPR platforms. Signed-off-by: Ingo Molnar <mingo@kernel.org> -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEEBpT5eoXrXCwVQwEKEnMQ0APhK1gFAl83xBQRHG1pbmdvQGtl cm5lbC5vcmcACgkQEnMQ0APhK1gb9RAArM0jJemRPHv1a/xLhrRo/cKURrOWpNl0 OQtgppEv9axkavYL34eyoax4LTDCFXxE+NDClSC16abFEVPNriGODNE+CMbFgMbW AyDfP+AsDdNExwl+JWR+J37KIpEIzWLqtjzEjVxZqsuov3C+EaLU4gv947UFohxM QE93d8q3znBSdMjeC/aZyL8iX4aCB0oMjrP7BMXo9a61/oseKLnvE8Zu/ESFDe1S TYZ+VlCxyaZOUBkEyd8+h/CBL8kOvQ2ObBEBxmyQQdGuRZ20BcJRodk3g+mOdnHJ zeohRcXvIHskHTEVeQv+Eh4EitFT3bEFrbk0LwMhKubIhFTKIB42sAzyeC6iUGc/ O5+Qe+bn3kYMynMHNo1yfh0s0S3cU3cfBnC1I2A/NyAn49H0UPr+rjynuKHtCA1+ S36Q9BydZegU/jyhbbDs+h/cdOiKY2F3MPEAZg3u/7EM+NIrmvuQoA7+C33fmLA+ tZzpeDpqNKz65JgYDQ2sZdghyVp41KTogeTm6Xu5O3sLhCnATiyqL2z2LCoWj+yZ KuZ+zHtV8ajRwt1bhq7qFUIyQLsHHUlz5z7TiUC7qqB48LpxO7LiTZ7CxUDY432N Xz8QPD/D71HAWmbkAXUih+JXG0nQSdlF6Xpwquczqc/8odJ46xdQ+i5wIgBOcudP A+kEXRqz5rA= =NsxB -----END PGP SIGNATURE----- Merge tag 'perf-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Misc fixes, an expansion of perf syscall access to CAP_PERFMON privileged tools, plus a RAPL HW-enablement for Intel SPR platforms" * tag 'perf-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/rapl: Add support for Intel SPR platform perf/x86/rapl: Support multiple RAPL unit quirks perf/x86/rapl: Fix missing psys sysfs attributes hw_breakpoint: Remove unused __register_perf_hw_breakpoint() declaration kprobes: Remove show_registers() function prototype perf/core: Take over CAP_SYS_PTRACE creds to CAP_PERFMON capability
This commit is contained in:
Linus Torvalds
commit
7f5faaaa59
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@ -130,11 +130,17 @@ struct rapl_pmus {
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struct rapl_pmu *pmus[];
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};
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enum rapl_unit_quirk {
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RAPL_UNIT_QUIRK_NONE,
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RAPL_UNIT_QUIRK_INTEL_HSW,
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RAPL_UNIT_QUIRK_INTEL_SPR,
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};
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struct rapl_model {
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struct perf_msr *rapl_msrs;
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unsigned long events;
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unsigned int msr_power_unit;
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bool apply_quirk;
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enum rapl_unit_quirk unit_quirk;
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};
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/* 1/2^hw_unit Joule */
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@ -612,14 +618,28 @@ static int rapl_check_hw_unit(struct rapl_model *rm)
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for (i = 0; i < NR_RAPL_DOMAINS; i++)
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rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
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switch (rm->unit_quirk) {
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/*
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* DRAM domain on HSW server and KNL has fixed energy unit which can be
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* different than the unit from power unit MSR. See
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* "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
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* of 2. Datasheet, September 2014, Reference Number: 330784-001 "
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*/
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if (rm->apply_quirk)
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case RAPL_UNIT_QUIRK_INTEL_HSW:
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rapl_hw_unit[PERF_RAPL_RAM] = 16;
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break;
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/*
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* SPR shares the same DRAM domain energy unit as HSW, plus it
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* also has a fixed energy unit for Psys domain.
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*/
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case RAPL_UNIT_QUIRK_INTEL_SPR:
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rapl_hw_unit[PERF_RAPL_RAM] = 16;
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rapl_hw_unit[PERF_RAPL_PSYS] = 0;
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break;
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default:
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break;
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}
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/*
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* Calculate the timer rate:
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@ -665,7 +685,7 @@ static const struct attribute_group *rapl_attr_update[] = {
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&rapl_events_pkg_group,
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&rapl_events_ram_group,
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&rapl_events_gpu_group,
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&rapl_events_gpu_group,
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&rapl_events_psys_group,
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NULL,
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};
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@ -698,7 +718,6 @@ static struct rapl_model model_snb = {
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.events = BIT(PERF_RAPL_PP0) |
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BIT(PERF_RAPL_PKG) |
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BIT(PERF_RAPL_PP1),
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.apply_quirk = false,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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@ -707,7 +726,6 @@ static struct rapl_model model_snbep = {
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.events = BIT(PERF_RAPL_PP0) |
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BIT(PERF_RAPL_PKG) |
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BIT(PERF_RAPL_RAM),
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.apply_quirk = false,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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@ -717,7 +735,6 @@ static struct rapl_model model_hsw = {
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BIT(PERF_RAPL_PKG) |
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BIT(PERF_RAPL_RAM) |
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BIT(PERF_RAPL_PP1),
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.apply_quirk = false,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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@ -726,7 +743,7 @@ static struct rapl_model model_hsx = {
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.events = BIT(PERF_RAPL_PP0) |
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BIT(PERF_RAPL_PKG) |
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BIT(PERF_RAPL_RAM),
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.apply_quirk = true,
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.unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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@ -734,7 +751,7 @@ static struct rapl_model model_hsx = {
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static struct rapl_model model_knl = {
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.events = BIT(PERF_RAPL_PKG) |
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BIT(PERF_RAPL_RAM),
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.apply_quirk = true,
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.unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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@ -745,14 +762,22 @@ static struct rapl_model model_skl = {
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BIT(PERF_RAPL_RAM) |
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BIT(PERF_RAPL_PP1) |
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BIT(PERF_RAPL_PSYS),
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.apply_quirk = false,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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static struct rapl_model model_spr = {
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.events = BIT(PERF_RAPL_PP0) |
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BIT(PERF_RAPL_PKG) |
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BIT(PERF_RAPL_RAM) |
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BIT(PERF_RAPL_PSYS),
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.unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR,
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.msr_power_unit = MSR_RAPL_POWER_UNIT,
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.rapl_msrs = intel_rapl_msrs,
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};
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static struct rapl_model model_amd_fam17h = {
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.events = BIT(PERF_RAPL_PKG),
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.apply_quirk = false,
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.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
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.rapl_msrs = amd_rapl_msrs,
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};
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@ -787,6 +812,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx),
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X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl),
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X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl),
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr),
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X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h),
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X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h),
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{},
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@ -72,7 +72,6 @@ register_wide_hw_breakpoint(struct perf_event_attr *attr,
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void *context);
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extern int register_perf_hw_breakpoint(struct perf_event *bp);
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extern int __register_perf_hw_breakpoint(struct perf_event *bp);
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extern void unregister_hw_breakpoint(struct perf_event *bp);
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extern void unregister_wide_hw_breakpoint(struct perf_event * __percpu *cpu_events);
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@ -119,8 +118,6 @@ register_wide_hw_breakpoint(struct perf_event_attr *attr,
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void *context) { return NULL; }
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static inline int
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register_perf_hw_breakpoint(struct perf_event *bp) { return -ENOSYS; }
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static inline int
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__register_perf_hw_breakpoint(struct perf_event *bp) { return -ENOSYS; }
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static inline void unregister_hw_breakpoint(struct perf_event *bp) { }
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static inline void
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unregister_wide_hw_breakpoint(struct perf_event * __percpu *cpu_events) { }
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@ -11706,7 +11706,7 @@ SYSCALL_DEFINE5(perf_event_open,
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goto err_task;
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/*
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* Reuse ptrace permission checks for now.
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* Preserve ptrace permission check for backwards compatibility.
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*
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* We must hold exec_update_mutex across this and any potential
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* perf_install_in_context() call for this new event to
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@ -11714,7 +11714,7 @@ SYSCALL_DEFINE5(perf_event_open,
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* perf_event_exit_task() that could imply).
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*/
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err = -EACCES;
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if (!ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
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if (!perfmon_capable() && !ptrace_may_access(task, PTRACE_MODE_READ_REALCREDS))
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goto err_cred;
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}
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