forked from luck/tmp_suning_uos_patched
drm/i915: introduce intel_ring_buffer structure (V2)
Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com> [anholt: Fixed up whitespace fail and rebased against prep patches] Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
parent
d3301d86b4
commit
8187a2b70e
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@ -317,14 +317,14 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data)
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u8 *virt;
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u8 *virt;
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uint32_t *ptr, off;
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uint32_t *ptr, off;
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if (!dev_priv->render_ring.ring_obj) {
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if (!dev_priv->render_ring.gem_object) {
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seq_printf(m, "No ringbuffer setup\n");
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seq_printf(m, "No ringbuffer setup\n");
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return 0;
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return 0;
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}
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}
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virt = dev_priv->render_ring.virtual_start;
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virt = dev_priv->render_ring.virtual_start;
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for (off = 0; off < dev_priv->render_ring.Size; off += 4) {
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for (off = 0; off < dev_priv->render_ring.size; off += 4) {
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ptr = (uint32_t *)(virt + off);
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ptr = (uint32_t *)(virt + off);
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seq_printf(m, "%08x : %08x\n", off, *ptr);
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seq_printf(m, "%08x : %08x\n", off, *ptr);
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}
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}
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@ -344,7 +344,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
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seq_printf(m, "RingHead : %08x\n", head);
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seq_printf(m, "RingHead : %08x\n", head);
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seq_printf(m, "RingTail : %08x\n", tail);
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seq_printf(m, "RingTail : %08x\n", tail);
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seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.Size);
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seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size);
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seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
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seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD));
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return 0;
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return 0;
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@ -40,7 +40,6 @@
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#include <linux/vga_switcheroo.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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/**
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/**
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* Sets up the hardware status page for devices that need a physical address
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* Sets up the hardware status page for devices that need a physical address
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* in the register.
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* in the register.
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@ -56,10 +55,11 @@ static int i915_init_phys_hws(struct drm_device *dev)
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DRM_ERROR("Can not allocate hardware status page\n");
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DRM_ERROR("Can not allocate hardware status page\n");
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
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dev_priv->render_ring.status_page.page_addr
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= dev_priv->status_page_dmah->vaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
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if (IS_I965G(dev))
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if (IS_I965G(dev))
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dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
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dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
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@ -95,7 +95,7 @@ void i915_kernel_lost_context(struct drm_device * dev)
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{
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv;
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struct drm_i915_master_private *master_priv;
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drm_i915_ring_buffer_t *ring = &(dev_priv->render_ring);
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struct intel_ring_buffer *ring = &dev_priv->render_ring;
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/*
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/*
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* We should never lose context on the ring with modesetting
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* We should never lose context on the ring with modesetting
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@ -108,7 +108,7 @@ void i915_kernel_lost_context(struct drm_device * dev)
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ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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if (ring->space < 0)
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ring->space += ring->Size;
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ring->space += ring->size;
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if (!dev->primary->master)
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if (!dev->primary->master)
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return;
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return;
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@ -128,12 +128,7 @@ static int i915_dma_cleanup(struct drm_device * dev)
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if (dev->irq_enabled)
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if (dev->irq_enabled)
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drm_irq_uninstall(dev);
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drm_irq_uninstall(dev);
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if (dev_priv->render_ring.virtual_start) {
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intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
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drm_core_ioremapfree(&dev_priv->render_ring.map, dev);
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dev_priv->render_ring.virtual_start = NULL;
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dev_priv->render_ring.map.handle = NULL;
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dev_priv->render_ring.map.size = 0;
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}
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/* Clear the HWS virtual address at teardown */
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/* Clear the HWS virtual address at teardown */
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if (I915_NEED_GFX_HWS(dev))
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if (I915_NEED_GFX_HWS(dev))
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@ -156,14 +151,14 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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}
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}
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if (init->ring_size != 0) {
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if (init->ring_size != 0) {
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if (dev_priv->render_ring.ring_obj != NULL) {
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if (dev_priv->render_ring.gem_object != NULL) {
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i915_dma_cleanup(dev);
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i915_dma_cleanup(dev);
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DRM_ERROR("Client tried to initialize ringbuffer in "
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DRM_ERROR("Client tried to initialize ringbuffer in "
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"GEM mode\n");
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"GEM mode\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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dev_priv->render_ring.Size = init->ring_size;
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dev_priv->render_ring.size = init->ring_size;
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dev_priv->render_ring.map.offset = init->ring_start;
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dev_priv->render_ring.map.offset = init->ring_start;
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dev_priv->render_ring.map.size = init->ring_size;
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dev_priv->render_ring.map.size = init->ring_size;
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@ -201,26 +196,29 @@ static int i915_dma_resume(struct drm_device * dev)
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{
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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struct intel_ring_buffer *ring;
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DRM_DEBUG_DRIVER("%s\n", __func__);
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DRM_DEBUG_DRIVER("%s\n", __func__);
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if (dev_priv->render_ring.map.handle == NULL) {
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ring = &dev_priv->render_ring;
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if (ring->map.handle == NULL) {
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DRM_ERROR("can not ioremap virtual address for"
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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" ring buffer\n");
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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/* Program Hardware Status Page */
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/* Program Hardware Status Page */
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if (!dev_priv->hw_status_page) {
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if (!ring->status_page.page_addr) {
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DRM_ERROR("Can not find hardware status page\n");
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DRM_ERROR("Can not find hardware status page\n");
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return -EINVAL;
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return -EINVAL;
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}
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}
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DRM_DEBUG_DRIVER("hw status page @ %p\n",
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DRM_DEBUG_DRIVER("hw status page @ %p\n",
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dev_priv->hw_status_page);
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ring->status_page.page_addr);
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if (ring->status_page.gfx_addr != 0)
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if (dev_priv->status_gfx_addr != 0)
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ring->setup_status_page(dev, ring);
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I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
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else
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else
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I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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DRM_DEBUG_DRIVER("Enabled hardware status page\n");
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DRM_DEBUG_DRIVER("Enabled hardware status page\n");
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return 0;
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return 0;
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@ -330,9 +328,8 @@ static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
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{
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i;
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int i;
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RING_LOCALS;
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if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.Size - 8)
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if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
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return -EINVAL;
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return -EINVAL;
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BEGIN_LP_RING((dwords+1)&~1);
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BEGIN_LP_RING((dwords+1)&~1);
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@ -365,9 +362,7 @@ i915_emit_box(struct drm_device *dev,
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struct drm_clip_rect *boxes,
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struct drm_clip_rect *boxes,
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int i, int DR1, int DR4)
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int i, int DR1, int DR4)
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{
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_clip_rect box = boxes[i];
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struct drm_clip_rect box = boxes[i];
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RING_LOCALS;
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if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
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if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
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DRM_ERROR("Bad box %d,%d..%d,%d\n",
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DRM_ERROR("Bad box %d,%d..%d,%d\n",
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@ -404,7 +399,6 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
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{
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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RING_LOCALS;
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dev_priv->counter++;
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dev_priv->counter++;
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if (dev_priv->counter > 0x7FFFFFFFUL)
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if (dev_priv->counter > 0x7FFFFFFFUL)
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@ -458,10 +452,8 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
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drm_i915_batchbuffer_t * batch,
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drm_i915_batchbuffer_t * batch,
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struct drm_clip_rect *cliprects)
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struct drm_clip_rect *cliprects)
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{
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int nbox = batch->num_cliprects;
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int nbox = batch->num_cliprects;
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int i = 0, count;
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int i = 0, count;
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RING_LOCALS;
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if ((batch->start | batch->used) & 0x7) {
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if ((batch->start | batch->used) & 0x7) {
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DRM_ERROR("alignment");
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DRM_ERROR("alignment");
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@ -510,7 +502,6 @@ static int i915_dispatch_flip(struct drm_device * dev)
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv =
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struct drm_i915_master_private *master_priv =
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dev->primary->master->driver_priv;
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dev->primary->master->driver_priv;
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RING_LOCALS;
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if (!master_priv->sarea_priv)
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if (!master_priv->sarea_priv)
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return -EINVAL;
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return -EINVAL;
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@ -563,7 +554,8 @@ static int i915_quiescent(struct drm_device * dev)
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = dev->dev_private;
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i915_kernel_lost_context(dev);
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i915_kernel_lost_context(dev);
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return i915_wait_ring(dev, dev_priv->render_ring.Size - 8, __func__);
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return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
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dev_priv->render_ring.size - 8);
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}
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}
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static int i915_flush_ioctl(struct drm_device *dev, void *data,
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static int i915_flush_ioctl(struct drm_device *dev, void *data,
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@ -805,6 +797,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
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{
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_private_t *dev_priv = dev->dev_private;
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drm_i915_hws_addr_t *hws = data;
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drm_i915_hws_addr_t *hws = data;
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struct intel_ring_buffer *ring = &dev_priv->render_ring;
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if (!I915_NEED_GFX_HWS(dev))
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if (!I915_NEED_GFX_HWS(dev))
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return -EINVAL;
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return -EINVAL;
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@ -821,7 +814,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
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DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
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DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
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dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
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ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
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dev_priv->hws_map.offset = dev->agp->base + hws->addr;
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dev_priv->hws_map.offset = dev->agp->base + hws->addr;
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dev_priv->hws_map.size = 4*1024;
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dev_priv->hws_map.size = 4*1024;
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@ -837,10 +830,10 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
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" G33 hw status page\n");
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" G33 hw status page\n");
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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dev_priv->hw_status_page = dev_priv->hws_map.handle;
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ring->status_page.page_addr = dev_priv->hws_map.handle;
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memset(ring->status_page.page_addr, 0, PAGE_SIZE);
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I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
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DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
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DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
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dev_priv->status_gfx_addr);
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dev_priv->status_gfx_addr);
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DRM_DEBUG_DRIVER("load hws at %p\n",
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DRM_DEBUG_DRIVER("load hws at %p\n",
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@ -1639,7 +1632,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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spin_lock_init(&dev_priv->user_irq_lock);
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spin_lock_init(&dev_priv->user_irq_lock);
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spin_lock_init(&dev_priv->error_lock);
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spin_lock_init(&dev_priv->error_lock);
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dev_priv->user_irq_refcount = 0;
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dev_priv->trace_irq_seqno = 0;
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dev_priv->trace_irq_seqno = 0;
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ret = drm_vblank_init(dev, I915_NUM_PIPE);
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ret = drm_vblank_init(dev, I915_NUM_PIPE);
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@ -388,33 +388,10 @@ int i965_reset(struct drm_device *dev, u8 flags)
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* switched away).
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* switched away).
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*/
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*/
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if (drm_core_check_feature(dev, DRIVER_MODESET) ||
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if (drm_core_check_feature(dev, DRIVER_MODESET) ||
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!dev_priv->mm.suspended) {
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!dev_priv->mm.suspended) {
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drm_i915_ring_buffer_t *ring = &dev_priv->render_ring;
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struct intel_ring_buffer *ring = &dev_priv->render_ring;
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struct drm_gem_object *obj = ring->ring_obj;
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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dev_priv->mm.suspended = 0;
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dev_priv->mm.suspended = 0;
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ring->init(dev, ring);
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/* Stop the ring if it's running. */
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I915_WRITE(PRB0_CTL, 0);
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I915_WRITE(PRB0_TAIL, 0);
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I915_WRITE(PRB0_HEAD, 0);
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/* Initialize the ring. */
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I915_WRITE(PRB0_START, obj_priv->gtt_offset);
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I915_WRITE(PRB0_CTL,
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((obj->size - 4096) & RING_NR_PAGES) |
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RING_NO_REPORT |
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RING_VALID);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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i915_kernel_lost_context(dev);
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else {
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ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->Size;
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}
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mutex_unlock(&dev->struct_mutex);
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mutex_unlock(&dev->struct_mutex);
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drm_irq_uninstall(dev);
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drm_irq_uninstall(dev);
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drm_irq_install(dev);
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drm_irq_install(dev);
|
||||||
|
|
|
@ -31,8 +31,8 @@
|
||||||
#define _I915_DRV_H_
|
#define _I915_DRV_H_
|
||||||
|
|
||||||
#include "i915_reg.h"
|
#include "i915_reg.h"
|
||||||
#include "i915_drm.h"
|
|
||||||
#include "intel_bios.h"
|
#include "intel_bios.h"
|
||||||
|
#include "intel_ringbuffer.h"
|
||||||
#include <linux/io-mapping.h>
|
#include <linux/io-mapping.h>
|
||||||
|
|
||||||
/* General customization:
|
/* General customization:
|
||||||
|
@ -92,16 +92,6 @@ struct drm_i915_gem_phys_object {
|
||||||
struct drm_gem_object *cur_obj;
|
struct drm_gem_object *cur_obj;
|
||||||
};
|
};
|
||||||
|
|
||||||
typedef struct _drm_i915_ring_buffer {
|
|
||||||
unsigned long Size;
|
|
||||||
u8 *virtual_start;
|
|
||||||
int head;
|
|
||||||
int tail;
|
|
||||||
int space;
|
|
||||||
drm_local_map_t map;
|
|
||||||
struct drm_gem_object *ring_obj;
|
|
||||||
} drm_i915_ring_buffer_t;
|
|
||||||
|
|
||||||
struct mem_block {
|
struct mem_block {
|
||||||
struct mem_block *next;
|
struct mem_block *next;
|
||||||
struct mem_block *prev;
|
struct mem_block *prev;
|
||||||
|
@ -244,7 +234,7 @@ typedef struct drm_i915_private {
|
||||||
void __iomem *regs;
|
void __iomem *regs;
|
||||||
|
|
||||||
struct pci_dev *bridge_dev;
|
struct pci_dev *bridge_dev;
|
||||||
drm_i915_ring_buffer_t render_ring;
|
struct intel_ring_buffer render_ring;
|
||||||
|
|
||||||
drm_dma_handle_t *status_page_dmah;
|
drm_dma_handle_t *status_page_dmah;
|
||||||
void *hw_status_page;
|
void *hw_status_page;
|
||||||
|
@ -270,8 +260,6 @@ typedef struct drm_i915_private {
|
||||||
atomic_t irq_received;
|
atomic_t irq_received;
|
||||||
/** Protects user_irq_refcount and irq_mask_reg */
|
/** Protects user_irq_refcount and irq_mask_reg */
|
||||||
spinlock_t user_irq_lock;
|
spinlock_t user_irq_lock;
|
||||||
/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
|
|
||||||
int user_irq_refcount;
|
|
||||||
u32 trace_irq_seqno;
|
u32 trace_irq_seqno;
|
||||||
/** Cached value of IMR to avoid reads in updating the bitfield */
|
/** Cached value of IMR to avoid reads in updating the bitfield */
|
||||||
u32 irq_mask_reg;
|
u32 irq_mask_reg;
|
||||||
|
@ -832,9 +820,7 @@ extern int i915_irq_emit(struct drm_device *dev, void *data,
|
||||||
struct drm_file *file_priv);
|
struct drm_file *file_priv);
|
||||||
extern int i915_irq_wait(struct drm_device *dev, void *data,
|
extern int i915_irq_wait(struct drm_device *dev, void *data,
|
||||||
struct drm_file *file_priv);
|
struct drm_file *file_priv);
|
||||||
void i915_user_irq_get(struct drm_device *dev);
|
|
||||||
void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
|
void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
|
||||||
void i915_user_irq_put(struct drm_device *dev);
|
|
||||||
extern void i915_enable_interrupt (struct drm_device *dev);
|
extern void i915_enable_interrupt (struct drm_device *dev);
|
||||||
|
|
||||||
extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
|
extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
|
||||||
|
@ -853,8 +839,10 @@ extern int i915_vblank_swap(struct drm_device *dev, void *data,
|
||||||
struct drm_file *file_priv);
|
struct drm_file *file_priv);
|
||||||
extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
|
extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
|
||||||
extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
|
extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
|
||||||
void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask);
|
extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
|
||||||
void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask);
|
u32 mask);
|
||||||
|
extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
|
||||||
|
u32 mask);
|
||||||
|
|
||||||
void
|
void
|
||||||
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
|
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
|
||||||
|
@ -962,8 +950,6 @@ void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
|
||||||
|
|
||||||
void i915_gem_shrinker_init(void);
|
void i915_gem_shrinker_init(void);
|
||||||
void i915_gem_shrinker_exit(void);
|
void i915_gem_shrinker_exit(void);
|
||||||
int i915_gem_init_pipe_control(struct drm_device *dev);
|
|
||||||
void i915_gem_cleanup_pipe_control(struct drm_device *dev);
|
|
||||||
|
|
||||||
/* i915_gem_tiling.c */
|
/* i915_gem_tiling.c */
|
||||||
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
|
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
|
||||||
|
@ -1014,16 +1000,6 @@ static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return;
|
||||||
static inline void opregion_enable_asle(struct drm_device *dev) { return; }
|
static inline void opregion_enable_asle(struct drm_device *dev) { return; }
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* intel_ringbuffer.c */
|
|
||||||
extern void i915_gem_flush(struct drm_device *dev,
|
|
||||||
uint32_t invalidate_domains,
|
|
||||||
uint32_t flush_domains);
|
|
||||||
extern int i915_dispatch_gem_execbuffer(struct drm_device *dev,
|
|
||||||
struct drm_i915_gem_execbuffer2 *exec,
|
|
||||||
struct drm_clip_rect *cliprects,
|
|
||||||
uint64_t exec_offset);
|
|
||||||
extern uint32_t i915_ring_add_request(struct drm_device *dev);
|
|
||||||
|
|
||||||
/* modesetting */
|
/* modesetting */
|
||||||
extern void intel_modeset_init(struct drm_device *dev);
|
extern void intel_modeset_init(struct drm_device *dev);
|
||||||
extern void intel_modeset_cleanup(struct drm_device *dev);
|
extern void intel_modeset_cleanup(struct drm_device *dev);
|
||||||
|
@ -1044,7 +1020,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
|
||||||
* has access to the ring.
|
* has access to the ring.
|
||||||
*/
|
*/
|
||||||
#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
|
#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
|
||||||
if (((drm_i915_private_t *)dev->dev_private)->render_ring.ring_obj == NULL) \
|
if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
|
||||||
|
== NULL) \
|
||||||
LOCK_TEST_WITH_RETURN(dev, file_priv); \
|
LOCK_TEST_WITH_RETURN(dev, file_priv); \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
|
@ -1060,32 +1037,27 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
|
||||||
|
|
||||||
#define I915_VERBOSE 0
|
#define I915_VERBOSE 0
|
||||||
|
|
||||||
#define RING_LOCALS volatile unsigned int *ring_virt__;
|
#define BEGIN_LP_RING(n) do { \
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private; \
|
||||||
#define BEGIN_LP_RING(n) do { \
|
if (I915_VERBOSE) \
|
||||||
int bytes__ = 4*(n); \
|
DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
|
||||||
if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
|
intel_ring_begin(dev, &dev_priv->render_ring, 4*(n)); \
|
||||||
/* a wrap must occur between instructions so pad beforehand */ \
|
|
||||||
if (unlikely (dev_priv->render_ring.tail + bytes__ > dev_priv->render_ring.Size)) \
|
|
||||||
i915_wrap_ring(dev); \
|
|
||||||
if (unlikely (dev_priv->render_ring.space < bytes__)) \
|
|
||||||
i915_wait_ring(dev, bytes__, __func__); \
|
|
||||||
ring_virt__ = (unsigned int *) \
|
|
||||||
(dev_priv->render_ring.virtual_start + dev_priv->render_ring.tail); \
|
|
||||||
dev_priv->render_ring.tail += bytes__; \
|
|
||||||
dev_priv->render_ring.tail &= dev_priv->render_ring.Size - 1; \
|
|
||||||
dev_priv->render_ring.space -= bytes__; \
|
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
#define OUT_RING(n) do { \
|
|
||||||
if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
|
#define OUT_RING(x) do { \
|
||||||
*ring_virt__++ = (n); \
|
drm_i915_private_t *dev_priv = dev->dev_private; \
|
||||||
|
if (I915_VERBOSE) \
|
||||||
|
DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
|
||||||
|
intel_ring_emit(dev, &dev_priv->render_ring, x); \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
||||||
#define ADVANCE_LP_RING() do { \
|
#define ADVANCE_LP_RING() do { \
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private; \
|
||||||
if (I915_VERBOSE) \
|
if (I915_VERBOSE) \
|
||||||
DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->render_ring.tail); \
|
DRM_DEBUG("ADVANCE_LP_RING %x\n", \
|
||||||
I915_WRITE(PRB0_TAIL, dev_priv->render_ring.tail); \
|
dev_priv->render_ring.tail); \
|
||||||
|
intel_ring_advance(dev, &dev_priv->render_ring); \
|
||||||
} while(0)
|
} while(0)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1103,14 +1075,12 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
|
||||||
*
|
*
|
||||||
* The area from dword 0x20 to 0x3ff is available for driver usage.
|
* The area from dword 0x20 to 0x3ff is available for driver usage.
|
||||||
*/
|
*/
|
||||||
#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
|
#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
|
||||||
|
(dev_priv->render_ring.status_page.page_addr))[reg])
|
||||||
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
|
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
|
||||||
#define I915_GEM_HWS_INDEX 0x20
|
#define I915_GEM_HWS_INDEX 0x20
|
||||||
#define I915_BREADCRUMB_INDEX 0x21
|
#define I915_BREADCRUMB_INDEX 0x21
|
||||||
|
|
||||||
extern int i915_wrap_ring(struct drm_device * dev);
|
|
||||||
extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
|
|
||||||
|
|
||||||
#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
|
#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
|
||||||
|
|
||||||
#define IS_I830(dev) ((dev)->pci_device == 0x3577)
|
#define IS_I830(dev) ((dev)->pci_device == 0x3577)
|
||||||
|
|
|
@ -1590,6 +1590,7 @@ i915_gem_process_flushing_list(struct drm_device *dev,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32_t
|
uint32_t
|
||||||
i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
|
i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
|
||||||
uint32_t flush_domains)
|
uint32_t flush_domains)
|
||||||
|
@ -1607,7 +1608,8 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
|
||||||
if (request == NULL)
|
if (request == NULL)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
seqno = i915_ring_add_request(dev);
|
seqno = dev_priv->render_ring.add_request(dev, &dev_priv->render_ring,
|
||||||
|
file_priv, flush_domains);
|
||||||
|
|
||||||
DRM_DEBUG_DRIVER("%d\n", seqno);
|
DRM_DEBUG_DRIVER("%d\n", seqno);
|
||||||
|
|
||||||
|
@ -1645,10 +1647,8 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
|
||||||
static uint32_t
|
static uint32_t
|
||||||
i915_retire_commands(struct drm_device *dev)
|
i915_retire_commands(struct drm_device *dev)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
||||||
uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
|
uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
|
||||||
uint32_t flush_domains = 0;
|
uint32_t flush_domains = 0;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
/* The sampler always gets flushed on i965 (sigh) */
|
/* The sampler always gets flushed on i965 (sigh) */
|
||||||
if (IS_I965G(dev))
|
if (IS_I965G(dev))
|
||||||
|
@ -1746,7 +1746,9 @@ i915_gem_retire_requests(struct drm_device *dev)
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
uint32_t seqno;
|
uint32_t seqno;
|
||||||
|
|
||||||
if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
|
struct intel_ring_buffer *ring = &(dev_priv->render_ring);
|
||||||
|
if (!ring->status_page.page_addr
|
||||||
|
|| list_empty(&dev_priv->mm.request_list))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
seqno = i915_get_gem_seqno(dev);
|
seqno = i915_get_gem_seqno(dev);
|
||||||
|
@ -1773,7 +1775,8 @@ i915_gem_retire_requests(struct drm_device *dev)
|
||||||
|
|
||||||
if (unlikely (dev_priv->trace_irq_seqno &&
|
if (unlikely (dev_priv->trace_irq_seqno &&
|
||||||
i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
|
i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
|
||||||
i915_user_irq_put(dev);
|
|
||||||
|
ring->user_irq_put(dev, ring);
|
||||||
dev_priv->trace_irq_seqno = 0;
|
dev_priv->trace_irq_seqno = 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1803,6 +1806,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
|
||||||
u32 ier;
|
u32 ier;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
|
struct intel_ring_buffer *ring = &dev_priv->render_ring;
|
||||||
BUG_ON(seqno == 0);
|
BUG_ON(seqno == 0);
|
||||||
|
|
||||||
if (atomic_read(&dev_priv->mm.wedged))
|
if (atomic_read(&dev_priv->mm.wedged))
|
||||||
|
@ -1823,7 +1827,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
|
||||||
trace_i915_gem_request_wait_begin(dev, seqno);
|
trace_i915_gem_request_wait_begin(dev, seqno);
|
||||||
|
|
||||||
dev_priv->mm.waiting_gem_seqno = seqno;
|
dev_priv->mm.waiting_gem_seqno = seqno;
|
||||||
i915_user_irq_get(dev);
|
ring->user_irq_get(dev, ring);
|
||||||
if (interruptible)
|
if (interruptible)
|
||||||
ret = wait_event_interruptible(dev_priv->irq_queue,
|
ret = wait_event_interruptible(dev_priv->irq_queue,
|
||||||
i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
|
i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
|
||||||
|
@ -1833,7 +1837,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
|
||||||
i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
|
i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
|
||||||
atomic_read(&dev_priv->mm.wedged));
|
atomic_read(&dev_priv->mm.wedged));
|
||||||
|
|
||||||
i915_user_irq_put(dev);
|
ring->user_irq_put(dev, ring);
|
||||||
dev_priv->mm.waiting_gem_seqno = 0;
|
dev_priv->mm.waiting_gem_seqno = 0;
|
||||||
|
|
||||||
trace_i915_gem_request_wait_end(dev, seqno);
|
trace_i915_gem_request_wait_end(dev, seqno);
|
||||||
|
@ -1867,6 +1871,19 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static void
|
||||||
|
i915_gem_flush(struct drm_device *dev,
|
||||||
|
uint32_t invalidate_domains,
|
||||||
|
uint32_t flush_domains)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
if (flush_domains & I915_GEM_DOMAIN_CPU)
|
||||||
|
drm_agp_chipset_flush(dev);
|
||||||
|
dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
|
||||||
|
invalidate_domains,
|
||||||
|
flush_domains);
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Ensures that all rendering to the object has completed and the object is
|
* Ensures that all rendering to the object has completed and the object is
|
||||||
* safe to unbind from the GTT or access from the CPU.
|
* safe to unbind from the GTT or access from the CPU.
|
||||||
|
@ -3820,7 +3837,11 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Exec the batchbuffer */
|
/* Exec the batchbuffer */
|
||||||
ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
|
ret = dev_priv->render_ring.dispatch_gem_execbuffer(dev,
|
||||||
|
&dev_priv->render_ring,
|
||||||
|
args,
|
||||||
|
cliprects,
|
||||||
|
exec_offset);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
DRM_ERROR("dispatch failed %d\n", ret);
|
DRM_ERROR("dispatch failed %d\n", ret);
|
||||||
goto err;
|
goto err;
|
||||||
|
@ -4378,7 +4399,8 @@ i915_gem_idle(struct drm_device *dev)
|
||||||
|
|
||||||
mutex_lock(&dev->struct_mutex);
|
mutex_lock(&dev->struct_mutex);
|
||||||
|
|
||||||
if (dev_priv->mm.suspended || dev_priv->render_ring.ring_obj == NULL) {
|
if (dev_priv->mm.suspended ||
|
||||||
|
dev_priv->render_ring.gem_object == NULL) {
|
||||||
mutex_unlock(&dev->struct_mutex);
|
mutex_unlock(&dev->struct_mutex);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -4420,7 +4442,7 @@ i915_gem_idle(struct drm_device *dev)
|
||||||
* 965+ support PIPE_CONTROL commands, which provide finer grained control
|
* 965+ support PIPE_CONTROL commands, which provide finer grained control
|
||||||
* over cache flushing.
|
* over cache flushing.
|
||||||
*/
|
*/
|
||||||
int
|
static int
|
||||||
i915_gem_init_pipe_control(struct drm_device *dev)
|
i915_gem_init_pipe_control(struct drm_device *dev)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
@ -4459,7 +4481,8 @@ i915_gem_init_pipe_control(struct drm_device *dev)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
|
||||||
|
static void
|
||||||
i915_gem_cleanup_pipe_control(struct drm_device *dev)
|
i915_gem_cleanup_pipe_control(struct drm_device *dev)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
@ -4476,6 +4499,37 @@ i915_gem_cleanup_pipe_control(struct drm_device *dev)
|
||||||
dev_priv->seqno_page = NULL;
|
dev_priv->seqno_page = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int
|
||||||
|
i915_gem_init_ringbuffer(struct drm_device *dev)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
int ret;
|
||||||
|
dev_priv->render_ring = render_ring;
|
||||||
|
if (!I915_NEED_GFX_HWS(dev)) {
|
||||||
|
dev_priv->render_ring.status_page.page_addr
|
||||||
|
= dev_priv->status_page_dmah->vaddr;
|
||||||
|
memset(dev_priv->render_ring.status_page.page_addr,
|
||||||
|
0, PAGE_SIZE);
|
||||||
|
}
|
||||||
|
if (HAS_PIPE_CONTROL(dev)) {
|
||||||
|
ret = i915_gem_init_pipe_control(dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
|
||||||
|
intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
|
||||||
|
if (HAS_PIPE_CONTROL(dev))
|
||||||
|
i915_gem_cleanup_pipe_control(dev);
|
||||||
|
}
|
||||||
|
|
||||||
int
|
int
|
||||||
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
||||||
struct drm_file *file_priv)
|
struct drm_file *file_priv)
|
||||||
|
|
|
@ -545,7 +545,8 @@ i915_ringbuffer_last_batch(struct drm_device *dev)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (bbaddr == 0) {
|
if (bbaddr == 0) {
|
||||||
ring = (u32 *)(dev_priv->render_ring.virtual_start + dev_priv->render_ring.Size);
|
ring = (u32 *)(dev_priv->render_ring.virtual_start
|
||||||
|
+ dev_priv->render_ring.size);
|
||||||
while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
|
while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
|
||||||
bbaddr = i915_get_bbaddr(dev, ring);
|
bbaddr = i915_get_bbaddr(dev, ring);
|
||||||
if (bbaddr)
|
if (bbaddr)
|
||||||
|
@ -639,7 +640,8 @@ static void i915_capture_error_state(struct drm_device *dev)
|
||||||
error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
|
error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
|
||||||
|
|
||||||
/* Record the ringbuffer */
|
/* Record the ringbuffer */
|
||||||
error->ringbuffer = i915_error_object_create(dev, dev_priv->render_ring.ring_obj);
|
error->ringbuffer = i915_error_object_create(dev,
|
||||||
|
dev_priv->render_ring.gem_object);
|
||||||
|
|
||||||
/* Record buffers on the active list. */
|
/* Record buffers on the active list. */
|
||||||
error->active_bo = NULL;
|
error->active_bo = NULL;
|
||||||
|
@ -984,7 +986,6 @@ static int i915_emit_irq(struct drm_device * dev)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
i915_kernel_lost_context(dev);
|
i915_kernel_lost_context(dev);
|
||||||
|
|
||||||
|
@ -1009,9 +1010,10 @@ static int i915_emit_irq(struct drm_device * dev)
|
||||||
void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
|
void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||||
|
struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
|
||||||
|
|
||||||
if (dev_priv->trace_irq_seqno == 0)
|
if (dev_priv->trace_irq_seqno == 0)
|
||||||
i915_user_irq_get(dev);
|
render_ring->user_irq_get(dev, render_ring);
|
||||||
|
|
||||||
dev_priv->trace_irq_seqno = seqno;
|
dev_priv->trace_irq_seqno = seqno;
|
||||||
}
|
}
|
||||||
|
@ -1021,6 +1023,7 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
|
||||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||||
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
|
||||||
|
|
||||||
DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
|
DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
|
||||||
READ_BREADCRUMB(dev_priv));
|
READ_BREADCRUMB(dev_priv));
|
||||||
|
@ -1034,10 +1037,10 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
|
||||||
if (master_priv->sarea_priv)
|
if (master_priv->sarea_priv)
|
||||||
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
||||||
|
|
||||||
i915_user_irq_get(dev);
|
render_ring->user_irq_get(dev, render_ring);
|
||||||
DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
|
DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
|
||||||
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
||||||
i915_user_irq_put(dev);
|
render_ring->user_irq_put(dev, render_ring);
|
||||||
|
|
||||||
if (ret == -EBUSY) {
|
if (ret == -EBUSY) {
|
||||||
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
|
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
|
||||||
|
|
|
@ -4629,7 +4629,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
|
int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
|
||||||
int ret, pipesrc;
|
int ret, pipesrc;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
work = kzalloc(sizeof *work, GFP_KERNEL);
|
work = kzalloc(sizeof *work, GFP_KERNEL);
|
||||||
if (work == NULL)
|
if (work == NULL)
|
||||||
|
|
|
@ -211,9 +211,7 @@ static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
|
||||||
static int intel_overlay_on(struct intel_overlay *overlay)
|
static int intel_overlay_on(struct intel_overlay *overlay)
|
||||||
{
|
{
|
||||||
struct drm_device *dev = overlay->dev;
|
struct drm_device *dev = overlay->dev;
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
||||||
int ret;
|
int ret;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
BUG_ON(overlay->active);
|
BUG_ON(overlay->active);
|
||||||
|
|
||||||
|
@ -248,7 +246,6 @@ static void intel_overlay_continue(struct intel_overlay *overlay,
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
u32 flip_addr = overlay->flip_addr;
|
u32 flip_addr = overlay->flip_addr;
|
||||||
u32 tmp;
|
u32 tmp;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
BUG_ON(!overlay->active);
|
BUG_ON(!overlay->active);
|
||||||
|
|
||||||
|
@ -274,7 +271,6 @@ static int intel_overlay_wait_flip(struct intel_overlay *overlay)
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
int ret;
|
int ret;
|
||||||
u32 tmp;
|
u32 tmp;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
if (overlay->last_flip_req != 0) {
|
if (overlay->last_flip_req != 0) {
|
||||||
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
|
ret = i915_do_wait_request(dev, overlay->last_flip_req, 1);
|
||||||
|
@ -314,9 +310,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
|
||||||
{
|
{
|
||||||
u32 flip_addr = overlay->flip_addr;
|
u32 flip_addr = overlay->flip_addr;
|
||||||
struct drm_device *dev = overlay->dev;
|
struct drm_device *dev = overlay->dev;
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
||||||
int ret;
|
int ret;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
BUG_ON(!overlay->active);
|
BUG_ON(!overlay->active);
|
||||||
|
|
||||||
|
@ -390,11 +384,9 @@ int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
|
||||||
int interruptible)
|
int interruptible)
|
||||||
{
|
{
|
||||||
struct drm_device *dev = overlay->dev;
|
struct drm_device *dev = overlay->dev;
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
||||||
struct drm_gem_object *obj;
|
struct drm_gem_object *obj;
|
||||||
u32 flip_addr;
|
u32 flip_addr;
|
||||||
int ret;
|
int ret;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
if (overlay->hw_wedged == HW_WEDGED)
|
if (overlay->hw_wedged == HW_WEDGED)
|
||||||
return -EIO;
|
return -EIO;
|
||||||
|
|
|
@ -29,30 +29,24 @@
|
||||||
|
|
||||||
#include "drmP.h"
|
#include "drmP.h"
|
||||||
#include "drm.h"
|
#include "drm.h"
|
||||||
#include "i915_drm.h"
|
|
||||||
#include "i915_drv.h"
|
#include "i915_drv.h"
|
||||||
|
#include "i915_drm.h"
|
||||||
#include "i915_trace.h"
|
#include "i915_trace.h"
|
||||||
#include "intel_drv.h"
|
|
||||||
|
|
||||||
void
|
static void
|
||||||
i915_gem_flush(struct drm_device *dev,
|
render_ring_flush(struct drm_device *dev,
|
||||||
uint32_t invalidate_domains,
|
struct intel_ring_buffer *ring,
|
||||||
uint32_t flush_domains)
|
u32 invalidate_domains,
|
||||||
|
u32 flush_domains)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
||||||
uint32_t cmd;
|
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
#if WATCH_EXEC
|
#if WATCH_EXEC
|
||||||
DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
|
DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
|
||||||
invalidate_domains, flush_domains);
|
invalidate_domains, flush_domains);
|
||||||
#endif
|
#endif
|
||||||
trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
|
u32 cmd;
|
||||||
|
trace_i915_gem_request_flush(dev, ring->next_seqno,
|
||||||
invalidate_domains, flush_domains);
|
invalidate_domains, flush_domains);
|
||||||
|
|
||||||
if (flush_domains & I915_GEM_DOMAIN_CPU)
|
|
||||||
drm_agp_chipset_flush(dev);
|
|
||||||
|
|
||||||
if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
|
if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
|
||||||
/*
|
/*
|
||||||
* read/write caches:
|
* read/write caches:
|
||||||
|
@ -100,19 +94,130 @@ i915_gem_flush(struct drm_device *dev,
|
||||||
#if WATCH_EXEC
|
#if WATCH_EXEC
|
||||||
DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
|
DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
|
||||||
#endif
|
#endif
|
||||||
BEGIN_LP_RING(2);
|
intel_ring_begin(dev, ring, 8);
|
||||||
OUT_RING(cmd);
|
intel_ring_emit(dev, ring, cmd);
|
||||||
OUT_RING(MI_NOOP);
|
intel_ring_emit(dev, ring, MI_NOOP);
|
||||||
ADVANCE_LP_RING();
|
intel_ring_advance(dev, ring);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int render_ring_get_head(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
return I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int render_ring_get_tail(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
return I915_READ(PRB0_TAIL) & TAIL_ADDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int render_ring_get_active_head(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
|
||||||
|
|
||||||
|
return I915_READ(acthd_reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void render_ring_advance_ring(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
I915_WRITE(PRB0_TAIL, ring->tail);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int init_ring_common(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
u32 head;
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
struct drm_i915_gem_object *obj_priv;
|
||||||
|
obj_priv = to_intel_bo(ring->gem_object);
|
||||||
|
|
||||||
|
/* Stop the ring if it's running. */
|
||||||
|
I915_WRITE(ring->regs.ctl, 0);
|
||||||
|
I915_WRITE(ring->regs.head, 0);
|
||||||
|
I915_WRITE(ring->regs.tail, 0);
|
||||||
|
|
||||||
|
/* Initialize the ring. */
|
||||||
|
I915_WRITE(ring->regs.start, obj_priv->gtt_offset);
|
||||||
|
head = ring->get_head(dev, ring);
|
||||||
|
|
||||||
|
/* G45 ring initialization fails to reset head to zero */
|
||||||
|
if (head != 0) {
|
||||||
|
DRM_ERROR("%s head not reset to zero "
|
||||||
|
"ctl %08x head %08x tail %08x start %08x\n",
|
||||||
|
ring->name,
|
||||||
|
I915_READ(ring->regs.ctl),
|
||||||
|
I915_READ(ring->regs.head),
|
||||||
|
I915_READ(ring->regs.tail),
|
||||||
|
I915_READ(ring->regs.start));
|
||||||
|
|
||||||
|
I915_WRITE(ring->regs.head, 0);
|
||||||
|
|
||||||
|
DRM_ERROR("%s head forced to zero "
|
||||||
|
"ctl %08x head %08x tail %08x start %08x\n",
|
||||||
|
ring->name,
|
||||||
|
I915_READ(ring->regs.ctl),
|
||||||
|
I915_READ(ring->regs.head),
|
||||||
|
I915_READ(ring->regs.tail),
|
||||||
|
I915_READ(ring->regs.start));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
I915_WRITE(ring->regs.ctl,
|
||||||
|
((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
|
||||||
|
| RING_NO_REPORT | RING_VALID);
|
||||||
|
|
||||||
|
head = I915_READ(ring->regs.head) & HEAD_ADDR;
|
||||||
|
/* If the head is still not zero, the ring is dead */
|
||||||
|
if (head != 0) {
|
||||||
|
DRM_ERROR("%s initialization failed "
|
||||||
|
"ctl %08x head %08x tail %08x start %08x\n",
|
||||||
|
ring->name,
|
||||||
|
I915_READ(ring->regs.ctl),
|
||||||
|
I915_READ(ring->regs.head),
|
||||||
|
I915_READ(ring->regs.tail),
|
||||||
|
I915_READ(ring->regs.start));
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||||
|
i915_kernel_lost_context(dev);
|
||||||
|
else {
|
||||||
|
ring->head = ring->get_head(dev, ring);
|
||||||
|
ring->tail = ring->get_tail(dev, ring);
|
||||||
|
ring->space = ring->head - (ring->tail + 8);
|
||||||
|
if (ring->space < 0)
|
||||||
|
ring->space += ring->size;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int init_render_ring(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
|
int ret = init_ring_common(dev, ring);
|
||||||
|
if (IS_I9XX(dev) && !IS_GEN3(dev)) {
|
||||||
|
I915_WRITE(MI_MODE,
|
||||||
|
(VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
#define PIPE_CONTROL_FLUSH(addr) \
|
#define PIPE_CONTROL_FLUSH(addr) \
|
||||||
|
do { \
|
||||||
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
|
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
|
||||||
PIPE_CONTROL_DEPTH_STALL); \
|
PIPE_CONTROL_DEPTH_STALL); \
|
||||||
OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
|
OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
|
||||||
OUT_RING(0); \
|
OUT_RING(0); \
|
||||||
OUT_RING(0); \
|
OUT_RING(0); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Creates a new sequence number, emitting a write of it to the status page
|
* Creates a new sequence number, emitting a write of it to the status page
|
||||||
|
@ -122,21 +227,15 @@ i915_gem_flush(struct drm_device *dev,
|
||||||
*
|
*
|
||||||
* Returned sequence numbers are nonzero on success.
|
* Returned sequence numbers are nonzero on success.
|
||||||
*/
|
*/
|
||||||
uint32_t
|
static u32
|
||||||
i915_ring_add_request(struct drm_device *dev)
|
render_ring_add_request(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
struct drm_file *file_priv,
|
||||||
|
u32 flush_domains)
|
||||||
{
|
{
|
||||||
|
u32 seqno;
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
uint32_t seqno;
|
seqno = intel_ring_get_seqno(dev, ring);
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
/* Grab the seqno we're going to make this request be, and bump the
|
|
||||||
* next (skipping 0 so it can be the reserved no-seqno value).
|
|
||||||
*/
|
|
||||||
seqno = dev_priv->mm.next_gem_seqno;
|
|
||||||
dev_priv->mm.next_gem_seqno++;
|
|
||||||
if (dev_priv->mm.next_gem_seqno == 0)
|
|
||||||
dev_priv->mm.next_gem_seqno++;
|
|
||||||
|
|
||||||
if (HAS_PIPE_CONTROL(dev)) {
|
if (HAS_PIPE_CONTROL(dev)) {
|
||||||
u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
|
u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
|
||||||
|
|
||||||
|
@ -181,13 +280,26 @@ i915_ring_add_request(struct drm_device *dev)
|
||||||
return seqno;
|
return seqno;
|
||||||
}
|
}
|
||||||
|
|
||||||
void i915_user_irq_get(struct drm_device *dev)
|
static u32
|
||||||
|
render_ring_get_gem_seqno(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||||
|
if (HAS_PIPE_CONTROL(dev))
|
||||||
|
return ((volatile u32 *)(dev_priv->seqno_page))[0];
|
||||||
|
else
|
||||||
|
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
render_ring_get_user_irq(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||||
unsigned long irqflags;
|
unsigned long irqflags;
|
||||||
|
|
||||||
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
||||||
if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
|
if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
|
||||||
if (HAS_PCH_SPLIT(dev))
|
if (HAS_PCH_SPLIT(dev))
|
||||||
ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
|
ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
|
||||||
else
|
else
|
||||||
|
@ -196,14 +308,16 @@ void i915_user_irq_get(struct drm_device *dev)
|
||||||
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
||||||
}
|
}
|
||||||
|
|
||||||
void i915_user_irq_put(struct drm_device *dev)
|
static void
|
||||||
|
render_ring_put_user_irq(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||||
unsigned long irqflags;
|
unsigned long irqflags;
|
||||||
|
|
||||||
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
||||||
BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
|
BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
|
||||||
if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
|
if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
|
||||||
if (HAS_PCH_SPLIT(dev))
|
if (HAS_PCH_SPLIT(dev))
|
||||||
ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
|
ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
|
||||||
else
|
else
|
||||||
|
@ -212,20 +326,31 @@ void i915_user_irq_put(struct drm_device *dev)
|
||||||
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Dispatch a batchbuffer to the ring
|
static void render_setup_status_page(struct drm_device *dev,
|
||||||
*/
|
struct intel_ring_buffer *ring)
|
||||||
int
|
{
|
||||||
i915_dispatch_gem_execbuffer(struct drm_device *dev,
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
struct drm_i915_gem_execbuffer2 *exec,
|
if (IS_GEN6(dev)) {
|
||||||
struct drm_clip_rect *cliprects,
|
I915_WRITE(HWS_PGA_GEN6, ring->status_page.gfx_addr);
|
||||||
uint64_t exec_offset)
|
I915_READ(HWS_PGA_GEN6); /* posting read */
|
||||||
|
} else {
|
||||||
|
I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
|
||||||
|
I915_READ(HWS_PGA); /* posting read */
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
struct drm_i915_gem_execbuffer2 *exec,
|
||||||
|
struct drm_clip_rect *cliprects,
|
||||||
|
uint64_t exec_offset)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
int nbox = exec->num_cliprects;
|
int nbox = exec->num_cliprects;
|
||||||
int i = 0, count;
|
int i = 0, count;
|
||||||
uint32_t exec_start, exec_len;
|
uint32_t exec_start, exec_len;
|
||||||
RING_LOCALS;
|
|
||||||
|
|
||||||
exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
|
exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
|
||||||
exec_len = (uint32_t) exec->batch_len;
|
exec_len = (uint32_t) exec->batch_len;
|
||||||
|
|
||||||
|
@ -242,74 +367,61 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (IS_I830(dev) || IS_845G(dev)) {
|
if (IS_I830(dev) || IS_845G(dev)) {
|
||||||
BEGIN_LP_RING(4);
|
intel_ring_begin(dev, ring, 4);
|
||||||
OUT_RING(MI_BATCH_BUFFER);
|
intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
|
||||||
OUT_RING(exec_start | MI_BATCH_NON_SECURE);
|
intel_ring_emit(dev, ring,
|
||||||
OUT_RING(exec_start + exec_len - 4);
|
exec_start | MI_BATCH_NON_SECURE);
|
||||||
OUT_RING(0);
|
intel_ring_emit(dev, ring, exec_start + exec_len - 4);
|
||||||
ADVANCE_LP_RING();
|
intel_ring_emit(dev, ring, 0);
|
||||||
} else {
|
} else {
|
||||||
BEGIN_LP_RING(2);
|
intel_ring_begin(dev, ring, 4);
|
||||||
if (IS_I965G(dev)) {
|
if (IS_I965G(dev)) {
|
||||||
OUT_RING(MI_BATCH_BUFFER_START |
|
intel_ring_emit(dev, ring,
|
||||||
(2 << 6) |
|
MI_BATCH_BUFFER_START | (2 << 6)
|
||||||
MI_BATCH_NON_SECURE_I965);
|
| MI_BATCH_NON_SECURE_I965);
|
||||||
OUT_RING(exec_start);
|
intel_ring_emit(dev, ring, exec_start);
|
||||||
} else {
|
} else {
|
||||||
OUT_RING(MI_BATCH_BUFFER_START |
|
intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START
|
||||||
(2 << 6));
|
| (2 << 6));
|
||||||
OUT_RING(exec_start | MI_BATCH_NON_SECURE);
|
intel_ring_emit(dev, ring, exec_start |
|
||||||
|
MI_BATCH_NON_SECURE);
|
||||||
}
|
}
|
||||||
ADVANCE_LP_RING();
|
|
||||||
}
|
}
|
||||||
|
intel_ring_advance(dev, ring);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* XXX breadcrumb */
|
/* XXX breadcrumb */
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void cleanup_status_page(struct drm_device *dev,
|
||||||
i915_gem_cleanup_hws(struct drm_device *dev)
|
struct intel_ring_buffer *ring)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
struct drm_gem_object *obj;
|
struct drm_gem_object *obj;
|
||||||
struct drm_i915_gem_object *obj_priv;
|
struct drm_i915_gem_object *obj_priv;
|
||||||
|
|
||||||
if (dev_priv->hws_obj == NULL)
|
obj = ring->status_page.obj;
|
||||||
|
if (obj == NULL)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
obj = dev_priv->hws_obj;
|
|
||||||
obj_priv = to_intel_bo(obj);
|
obj_priv = to_intel_bo(obj);
|
||||||
|
|
||||||
kunmap(obj_priv->pages[0]);
|
kunmap(obj_priv->pages[0]);
|
||||||
i915_gem_object_unpin(obj);
|
i915_gem_object_unpin(obj);
|
||||||
drm_gem_object_unreference(obj);
|
drm_gem_object_unreference(obj);
|
||||||
dev_priv->hws_obj = NULL;
|
ring->status_page.obj = NULL;
|
||||||
|
|
||||||
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
||||||
dev_priv->hw_status_page = NULL;
|
|
||||||
|
|
||||||
if (HAS_PIPE_CONTROL(dev))
|
|
||||||
i915_gem_cleanup_pipe_control(dev);
|
|
||||||
|
|
||||||
/* Write high address into HWS_PGA when disabling. */
|
|
||||||
I915_WRITE(HWS_PGA, 0x1ffff000);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int
|
static int init_status_page(struct drm_device *dev,
|
||||||
i915_gem_init_hws(struct drm_device *dev)
|
struct intel_ring_buffer *ring)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||||
struct drm_gem_object *obj;
|
struct drm_gem_object *obj;
|
||||||
struct drm_i915_gem_object *obj_priv;
|
struct drm_i915_gem_object *obj_priv;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* If we need a physical address for the status page, it's already
|
|
||||||
* initialized at driver load time.
|
|
||||||
*/
|
|
||||||
if (!I915_NEED_GFX_HWS(dev))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
obj = i915_gem_alloc_object(dev, 4096);
|
obj = i915_gem_alloc_object(dev, 4096);
|
||||||
if (obj == NULL) {
|
if (obj == NULL) {
|
||||||
DRM_ERROR("Failed to allocate status page\n");
|
DRM_ERROR("Failed to allocate status page\n");
|
||||||
|
@ -321,36 +433,21 @@ i915_gem_init_hws(struct drm_device *dev)
|
||||||
|
|
||||||
ret = i915_gem_object_pin(obj, 4096);
|
ret = i915_gem_object_pin(obj, 4096);
|
||||||
if (ret != 0) {
|
if (ret != 0) {
|
||||||
drm_gem_object_unreference(obj);
|
|
||||||
goto err_unref;
|
goto err_unref;
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_priv->status_gfx_addr = obj_priv->gtt_offset;
|
ring->status_page.gfx_addr = obj_priv->gtt_offset;
|
||||||
|
ring->status_page.page_addr = kmap(obj_priv->pages[0]);
|
||||||
dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
|
if (ring->status_page.page_addr == NULL) {
|
||||||
if (dev_priv->hw_status_page == NULL) {
|
|
||||||
DRM_ERROR("Failed to map status page.\n");
|
|
||||||
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
||||||
ret = -EINVAL;
|
|
||||||
goto err_unpin;
|
goto err_unpin;
|
||||||
}
|
}
|
||||||
|
ring->status_page.obj = obj;
|
||||||
|
memset(ring->status_page.page_addr, 0, PAGE_SIZE);
|
||||||
|
|
||||||
if (HAS_PIPE_CONTROL(dev)) {
|
ring->setup_status_page(dev, ring);
|
||||||
ret = i915_gem_init_pipe_control(dev);
|
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
|
||||||
if (ret)
|
ring->name, ring->status_page.gfx_addr);
|
||||||
goto err_unpin;
|
|
||||||
}
|
|
||||||
|
|
||||||
dev_priv->hws_obj = obj;
|
|
||||||
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
|
|
||||||
if (IS_GEN6(dev)) {
|
|
||||||
I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
|
|
||||||
I915_READ(HWS_PGA_GEN6); /* posting read */
|
|
||||||
} else {
|
|
||||||
I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
|
|
||||||
I915_READ(HWS_PGA); /* posting read */
|
|
||||||
}
|
|
||||||
DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
@ -359,43 +456,42 @@ i915_gem_init_hws(struct drm_device *dev)
|
||||||
err_unref:
|
err_unref:
|
||||||
drm_gem_object_unreference(obj);
|
drm_gem_object_unreference(obj);
|
||||||
err:
|
err:
|
||||||
return 0;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
int
|
|
||||||
i915_gem_init_ringbuffer(struct drm_device *dev)
|
int intel_init_ring_buffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
||||||
struct drm_gem_object *obj;
|
|
||||||
struct drm_i915_gem_object *obj_priv;
|
|
||||||
drm_i915_ring_buffer_t *ring = &dev_priv->render_ring;
|
|
||||||
int ret;
|
int ret;
|
||||||
u32 head;
|
struct drm_i915_gem_object *obj_priv;
|
||||||
|
struct drm_gem_object *obj;
|
||||||
|
ring->dev = dev;
|
||||||
|
|
||||||
ret = i915_gem_init_hws(dev);
|
if (I915_NEED_GFX_HWS(dev)) {
|
||||||
if (ret != 0)
|
ret = init_status_page(dev, ring);
|
||||||
return ret;
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
obj = i915_gem_alloc_object(dev, 128 * 1024);
|
obj = i915_gem_alloc_object(dev, ring->size);
|
||||||
if (obj == NULL) {
|
if (obj == NULL) {
|
||||||
DRM_ERROR("Failed to allocate ringbuffer\n");
|
DRM_ERROR("Failed to allocate ringbuffer\n");
|
||||||
i915_gem_cleanup_hws(dev);
|
ret = -ENOMEM;
|
||||||
return -ENOMEM;
|
goto cleanup;
|
||||||
}
|
}
|
||||||
obj_priv = to_intel_bo(obj);
|
|
||||||
|
|
||||||
ret = i915_gem_object_pin(obj, 4096);
|
ring->gem_object = obj;
|
||||||
|
|
||||||
|
ret = i915_gem_object_pin(obj, ring->alignment);
|
||||||
if (ret != 0) {
|
if (ret != 0) {
|
||||||
drm_gem_object_unreference(obj);
|
drm_gem_object_unreference(obj);
|
||||||
i915_gem_cleanup_hws(dev);
|
goto cleanup;
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Set up the kernel mapping for the ring. */
|
obj_priv = to_intel_bo(obj);
|
||||||
ring->Size = obj->size;
|
ring->map.size = ring->size;
|
||||||
|
|
||||||
ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
|
ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
|
||||||
ring->map.size = obj->size;
|
|
||||||
ring->map.type = 0;
|
ring->map.type = 0;
|
||||||
ring->map.flags = 0;
|
ring->map.flags = 0;
|
||||||
ring->map.mtrr = 0;
|
ring->map.mtrr = 0;
|
||||||
|
@ -403,143 +499,85 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
|
||||||
drm_core_ioremap_wc(&ring->map, dev);
|
drm_core_ioremap_wc(&ring->map, dev);
|
||||||
if (ring->map.handle == NULL) {
|
if (ring->map.handle == NULL) {
|
||||||
DRM_ERROR("Failed to map ringbuffer.\n");
|
DRM_ERROR("Failed to map ringbuffer.\n");
|
||||||
memset(&dev_priv->render_ring, 0, sizeof(dev_priv->render_ring));
|
|
||||||
i915_gem_object_unpin(obj);
|
i915_gem_object_unpin(obj);
|
||||||
drm_gem_object_unreference(obj);
|
drm_gem_object_unreference(obj);
|
||||||
i915_gem_cleanup_hws(dev);
|
ret = -EINVAL;
|
||||||
return -EINVAL;
|
goto cleanup;
|
||||||
}
|
}
|
||||||
ring->ring_obj = obj;
|
|
||||||
ring->virtual_start = ring->map.handle;
|
ring->virtual_start = ring->map.handle;
|
||||||
|
ret = ring->init(dev, ring);
|
||||||
/* Stop the ring if it's running. */
|
if (ret != 0) {
|
||||||
I915_WRITE(PRB0_CTL, 0);
|
intel_cleanup_ring_buffer(dev, ring);
|
||||||
I915_WRITE(PRB0_TAIL, 0);
|
return ret;
|
||||||
I915_WRITE(PRB0_HEAD, 0);
|
|
||||||
|
|
||||||
/* Initialize the ring. */
|
|
||||||
I915_WRITE(PRB0_START, obj_priv->gtt_offset);
|
|
||||||
head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
|
||||||
|
|
||||||
/* G45 ring initialization fails to reset head to zero */
|
|
||||||
if (head != 0) {
|
|
||||||
DRM_ERROR("Ring head not reset to zero "
|
|
||||||
"ctl %08x head %08x tail %08x start %08x\n",
|
|
||||||
I915_READ(PRB0_CTL),
|
|
||||||
I915_READ(PRB0_HEAD),
|
|
||||||
I915_READ(PRB0_TAIL),
|
|
||||||
I915_READ(PRB0_START));
|
|
||||||
I915_WRITE(PRB0_HEAD, 0);
|
|
||||||
|
|
||||||
DRM_ERROR("Ring head forced to zero "
|
|
||||||
"ctl %08x head %08x tail %08x start %08x\n",
|
|
||||||
I915_READ(PRB0_CTL),
|
|
||||||
I915_READ(PRB0_HEAD),
|
|
||||||
I915_READ(PRB0_TAIL),
|
|
||||||
I915_READ(PRB0_START));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
I915_WRITE(PRB0_CTL,
|
|
||||||
((obj->size - 4096) & RING_NR_PAGES) |
|
|
||||||
RING_NO_REPORT |
|
|
||||||
RING_VALID);
|
|
||||||
|
|
||||||
head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
|
||||||
|
|
||||||
/* If the head is still not zero, the ring is dead */
|
|
||||||
if (head != 0) {
|
|
||||||
DRM_ERROR("Ring initialization failed "
|
|
||||||
"ctl %08x head %08x tail %08x start %08x\n",
|
|
||||||
I915_READ(PRB0_CTL),
|
|
||||||
I915_READ(PRB0_HEAD),
|
|
||||||
I915_READ(PRB0_TAIL),
|
|
||||||
I915_READ(PRB0_START));
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Update our cache of the ring state */
|
|
||||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||||
i915_kernel_lost_context(dev);
|
i915_kernel_lost_context(dev);
|
||||||
else {
|
else {
|
||||||
ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
ring->head = ring->get_head(dev, ring);
|
||||||
ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
|
ring->tail = ring->get_tail(dev, ring);
|
||||||
ring->space = ring->head - (ring->tail + 8);
|
ring->space = ring->head - (ring->tail + 8);
|
||||||
if (ring->space < 0)
|
if (ring->space < 0)
|
||||||
ring->space += ring->Size;
|
ring->space += ring->size;
|
||||||
}
|
}
|
||||||
|
INIT_LIST_HEAD(&ring->active_list);
|
||||||
if (IS_I9XX(dev) && !IS_GEN3(dev)) {
|
INIT_LIST_HEAD(&ring->request_list);
|
||||||
I915_WRITE(MI_MODE,
|
return ret;
|
||||||
(VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
|
cleanup:
|
||||||
}
|
cleanup_status_page(dev, ring);
|
||||||
|
return ret;
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void intel_cleanup_ring_buffer(struct drm_device *dev,
|
||||||
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
|
struct intel_ring_buffer *ring)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
if (ring->gem_object == NULL)
|
||||||
|
|
||||||
if (dev_priv->render_ring.ring_obj == NULL)
|
|
||||||
return;
|
return;
|
||||||
|
|
||||||
drm_core_ioremapfree(&dev_priv->render_ring.map, dev);
|
drm_core_ioremapfree(&ring->map, dev);
|
||||||
|
|
||||||
i915_gem_object_unpin(dev_priv->render_ring.ring_obj);
|
i915_gem_object_unpin(ring->gem_object);
|
||||||
drm_gem_object_unreference(dev_priv->render_ring.ring_obj);
|
drm_gem_object_unreference(ring->gem_object);
|
||||||
dev_priv->render_ring.ring_obj = NULL;
|
ring->gem_object = NULL;
|
||||||
memset(&dev_priv->render_ring, 0, sizeof(dev_priv->render_ring));
|
cleanup_status_page(dev, ring);
|
||||||
|
|
||||||
i915_gem_cleanup_hws(dev);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* As a ringbuffer is only allowed to wrap between instructions, fill
|
int intel_wrap_ring_buffer(struct drm_device *dev,
|
||||||
* the tail with NOOPs.
|
struct intel_ring_buffer *ring)
|
||||||
*/
|
|
||||||
int i915_wrap_ring(struct drm_device *dev)
|
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
unsigned int *virt;
|
||||||
volatile unsigned int *virt;
|
|
||||||
int rem;
|
int rem;
|
||||||
|
rem = ring->size - ring->tail;
|
||||||
|
|
||||||
rem = dev_priv->render_ring.Size - dev_priv->render_ring.tail;
|
if (ring->space < rem) {
|
||||||
if (dev_priv->render_ring.space < rem) {
|
int ret = intel_wait_ring_buffer(dev, ring, rem);
|
||||||
int ret = i915_wait_ring(dev, rem, __func__);
|
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
dev_priv->render_ring.space -= rem;
|
|
||||||
|
|
||||||
virt = (unsigned int *)
|
virt = (unsigned int *)(ring->virtual_start + ring->tail);
|
||||||
(dev_priv->render_ring.virtual_start + dev_priv->render_ring.tail);
|
|
||||||
rem /= 4;
|
rem /= 4;
|
||||||
while (rem--)
|
while (rem--)
|
||||||
*virt++ = MI_NOOP;
|
*virt++ = MI_NOOP;
|
||||||
|
|
||||||
dev_priv->render_ring.tail = 0;
|
ring->tail = 0;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
|
int intel_wait_ring_buffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring, int n)
|
||||||
{
|
{
|
||||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
unsigned long end;
|
||||||
drm_i915_ring_buffer_t *ring = &(dev_priv->render_ring);
|
|
||||||
u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
|
|
||||||
u32 last_acthd = I915_READ(acthd_reg);
|
|
||||||
u32 acthd;
|
|
||||||
u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
trace_i915_ring_wait_begin (dev);
|
trace_i915_ring_wait_begin (dev);
|
||||||
|
end = jiffies + 3 * HZ;
|
||||||
for (i = 0; i < 100000; i++) {
|
do {
|
||||||
ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
|
ring->head = ring->get_head(dev, ring);
|
||||||
acthd = I915_READ(acthd_reg);
|
|
||||||
ring->space = ring->head - (ring->tail + 8);
|
ring->space = ring->head - (ring->tail + 8);
|
||||||
if (ring->space < 0)
|
if (ring->space < 0)
|
||||||
ring->space += ring->Size;
|
ring->space += ring->size;
|
||||||
if (ring->space >= n) {
|
if (ring->space >= n) {
|
||||||
trace_i915_ring_wait_end (dev);
|
trace_i915_ring_wait_end (dev);
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -550,19 +588,97 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
|
||||||
if (master_priv->sarea_priv)
|
if (master_priv->sarea_priv)
|
||||||
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
||||||
}
|
}
|
||||||
|
yield();
|
||||||
|
} while (!time_after(jiffies, end));
|
||||||
if (ring->head != last_head)
|
|
||||||
i = 0;
|
|
||||||
if (acthd != last_acthd)
|
|
||||||
i = 0;
|
|
||||||
|
|
||||||
last_head = ring->head;
|
|
||||||
last_acthd = acthd;
|
|
||||||
msleep_interruptible(10);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
trace_i915_ring_wait_end (dev);
|
trace_i915_ring_wait_end (dev);
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void intel_ring_begin(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring, int n)
|
||||||
|
{
|
||||||
|
if (unlikely(ring->tail + n > ring->size))
|
||||||
|
intel_wrap_ring_buffer(dev, ring);
|
||||||
|
if (unlikely(ring->space < n))
|
||||||
|
intel_wait_ring_buffer(dev, ring, n);
|
||||||
|
}
|
||||||
|
|
||||||
|
void intel_ring_emit(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring, unsigned int data)
|
||||||
|
{
|
||||||
|
unsigned int *virt = ring->virtual_start + ring->tail;
|
||||||
|
*virt = data;
|
||||||
|
ring->tail += 4;
|
||||||
|
ring->tail &= ring->size - 1;
|
||||||
|
ring->space -= 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
void intel_ring_advance(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
ring->advance_ring(dev, ring);
|
||||||
|
}
|
||||||
|
|
||||||
|
void intel_fill_struct(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
void *data,
|
||||||
|
unsigned int len)
|
||||||
|
{
|
||||||
|
unsigned int *virt = ring->virtual_start + ring->tail;
|
||||||
|
BUG_ON((len&~(4-1)) != 0);
|
||||||
|
intel_ring_begin(dev, ring, len);
|
||||||
|
memcpy(virt, data, len);
|
||||||
|
ring->tail += len;
|
||||||
|
ring->tail &= ring->size - 1;
|
||||||
|
ring->space -= len;
|
||||||
|
intel_ring_advance(dev, ring);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 intel_ring_get_seqno(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring)
|
||||||
|
{
|
||||||
|
u32 seqno;
|
||||||
|
seqno = ring->next_seqno;
|
||||||
|
|
||||||
|
/* reserve 0 for non-seqno */
|
||||||
|
if (++ring->next_seqno == 0)
|
||||||
|
ring->next_seqno = 1;
|
||||||
|
return seqno;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct intel_ring_buffer render_ring = {
|
||||||
|
.name = "render ring",
|
||||||
|
.regs = {
|
||||||
|
.ctl = PRB0_CTL,
|
||||||
|
.head = PRB0_HEAD,
|
||||||
|
.tail = PRB0_TAIL,
|
||||||
|
.start = PRB0_START
|
||||||
|
},
|
||||||
|
.ring_flag = I915_EXEC_RENDER,
|
||||||
|
.size = 32 * PAGE_SIZE,
|
||||||
|
.alignment = PAGE_SIZE,
|
||||||
|
.virtual_start = NULL,
|
||||||
|
.dev = NULL,
|
||||||
|
.gem_object = NULL,
|
||||||
|
.head = 0,
|
||||||
|
.tail = 0,
|
||||||
|
.space = 0,
|
||||||
|
.next_seqno = 1,
|
||||||
|
.user_irq_refcount = 0,
|
||||||
|
.irq_gem_seqno = 0,
|
||||||
|
.waiting_gem_seqno = 0,
|
||||||
|
.setup_status_page = render_setup_status_page,
|
||||||
|
.init = init_render_ring,
|
||||||
|
.get_head = render_ring_get_head,
|
||||||
|
.get_tail = render_ring_get_tail,
|
||||||
|
.get_active_head = render_ring_get_active_head,
|
||||||
|
.advance_ring = render_ring_advance_ring,
|
||||||
|
.flush = render_ring_flush,
|
||||||
|
.add_request = render_ring_add_request,
|
||||||
|
.get_gem_seqno = render_ring_get_gem_seqno,
|
||||||
|
.user_irq_get = render_ring_get_user_irq,
|
||||||
|
.user_irq_put = render_ring_put_user_irq,
|
||||||
|
.dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer,
|
||||||
|
.status_page = {NULL, 0, NULL},
|
||||||
|
.map = {0,}
|
||||||
|
};
|
||||||
|
|
124
drivers/gpu/drm/i915/intel_ringbuffer.h
Normal file
124
drivers/gpu/drm/i915/intel_ringbuffer.h
Normal file
|
@ -0,0 +1,124 @@
|
||||||
|
#ifndef _INTEL_RINGBUFFER_H_
|
||||||
|
#define _INTEL_RINGBUFFER_H_
|
||||||
|
|
||||||
|
struct intel_hw_status_page {
|
||||||
|
void *page_addr;
|
||||||
|
unsigned int gfx_addr;
|
||||||
|
struct drm_gem_object *obj;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct drm_i915_gem_execbuffer2;
|
||||||
|
struct intel_ring_buffer {
|
||||||
|
const char *name;
|
||||||
|
struct ring_regs {
|
||||||
|
u32 ctl;
|
||||||
|
u32 head;
|
||||||
|
u32 tail;
|
||||||
|
u32 start;
|
||||||
|
} regs;
|
||||||
|
unsigned int ring_flag;
|
||||||
|
unsigned long size;
|
||||||
|
unsigned int alignment;
|
||||||
|
void *virtual_start;
|
||||||
|
struct drm_device *dev;
|
||||||
|
struct drm_gem_object *gem_object;
|
||||||
|
|
||||||
|
unsigned int head;
|
||||||
|
unsigned int tail;
|
||||||
|
unsigned int space;
|
||||||
|
u32 next_seqno;
|
||||||
|
struct intel_hw_status_page status_page;
|
||||||
|
|
||||||
|
u32 irq_gem_seqno; /* last seq seem at irq time */
|
||||||
|
u32 waiting_gem_seqno;
|
||||||
|
int user_irq_refcount;
|
||||||
|
void (*user_irq_get)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
void (*user_irq_put)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
void (*setup_status_page)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
|
||||||
|
int (*init)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
|
||||||
|
unsigned int (*get_head)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
unsigned int (*get_tail)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
unsigned int (*get_active_head)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
void (*advance_ring)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
void (*flush)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
u32 invalidate_domains,
|
||||||
|
u32 flush_domains);
|
||||||
|
u32 (*add_request)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
struct drm_file *file_priv,
|
||||||
|
u32 flush_domains);
|
||||||
|
u32 (*get_gem_seqno)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
int (*dispatch_gem_execbuffer)(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
struct drm_i915_gem_execbuffer2 *exec,
|
||||||
|
struct drm_clip_rect *cliprects,
|
||||||
|
uint64_t exec_offset);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* List of objects currently involved in rendering from the
|
||||||
|
* ringbuffer.
|
||||||
|
*
|
||||||
|
* Includes buffers having the contents of their GPU caches
|
||||||
|
* flushed, not necessarily primitives. last_rendering_seqno
|
||||||
|
* represents when the rendering involved will be completed.
|
||||||
|
*
|
||||||
|
* A reference is held on the buffer while on this list.
|
||||||
|
*/
|
||||||
|
struct list_head active_list;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* List of breadcrumbs associated with GPU requests currently
|
||||||
|
* outstanding.
|
||||||
|
*/
|
||||||
|
struct list_head request_list;
|
||||||
|
|
||||||
|
wait_queue_head_t irq_queue;
|
||||||
|
drm_local_map_t map;
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline u32
|
||||||
|
intel_read_status_page(struct intel_ring_buffer *ring,
|
||||||
|
int reg)
|
||||||
|
{
|
||||||
|
u32 *regs = ring->status_page.page_addr;
|
||||||
|
return regs[reg];
|
||||||
|
}
|
||||||
|
|
||||||
|
int intel_init_ring_buffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
void intel_cleanup_ring_buffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
int intel_wait_ring_buffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring, int n);
|
||||||
|
int intel_wrap_ring_buffer(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
void intel_ring_begin(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring, int n);
|
||||||
|
void intel_ring_emit(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring, u32 data);
|
||||||
|
void intel_fill_struct(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring,
|
||||||
|
void *data,
|
||||||
|
unsigned int len);
|
||||||
|
void intel_ring_advance(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
|
||||||
|
u32 intel_ring_get_seqno(struct drm_device *dev,
|
||||||
|
struct intel_ring_buffer *ring);
|
||||||
|
|
||||||
|
extern struct intel_ring_buffer render_ring;
|
||||||
|
extern struct intel_ring_buffer bsd_ring;
|
||||||
|
|
||||||
|
#endif /* _INTEL_RINGBUFFER_H_ */
|
|
@ -616,7 +616,9 @@ struct drm_i915_gem_execbuffer2 {
|
||||||
__u32 num_cliprects;
|
__u32 num_cliprects;
|
||||||
/** This is a struct drm_clip_rect *cliprects */
|
/** This is a struct drm_clip_rect *cliprects */
|
||||||
__u64 cliprects_ptr;
|
__u64 cliprects_ptr;
|
||||||
__u64 flags; /* currently unused */
|
#define I915_EXEC_RENDER (1<<0)
|
||||||
|
#define I915_EXEC_BSD (1<<1)
|
||||||
|
__u64 flags;
|
||||||
__u64 rsvd1;
|
__u64 rsvd1;
|
||||||
__u64 rsvd2;
|
__u64 rsvd2;
|
||||||
};
|
};
|
||||||
|
|
Loading…
Reference in New Issue
Block a user