forked from luck/tmp_suning_uos_patched
coresight: etm4x: Add kernel configuration for CONTEXTID
Set the proper bit in the configuration register when contextID tracing has been requested by user space. That way PE_CONTEXT elements are generated by the tracers when a process is installed on a CPU. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Leo Yan <leo.yan@linaro.org> Tested-by: Robert Walker <robert.walker@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -75,6 +75,7 @@ config CORESIGHT_SOURCE_ETM4X
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bool "CoreSight Embedded Trace Macrocell 4.x driver"
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depends on ARM64
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select CORESIGHT_LINKS_AND_SINKS
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select PID_IN_CONTEXTIDR
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help
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This driver provides support for the ETM4.x tracer module, tracing the
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instructions that a processor is executing. This is primarily useful
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@ -29,6 +29,7 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
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/* ETMv3.5/PTM's ETMCR is 'config' */
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PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC));
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PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID));
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PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
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PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK));
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/* Sink ID - same for all ETMs */
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@ -36,6 +37,7 @@ PMU_FORMAT_ATTR(sinkid, "config2:0-31");
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static struct attribute *etm_config_formats_attr[] = {
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&format_attr_cycacc.attr,
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&format_attr_contextid.attr,
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&format_attr_timestamp.attr,
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&format_attr_retstack.attr,
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&format_attr_sinkid.attr,
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@ -239,6 +239,11 @@ static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
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if (attr->config & BIT(ETM_OPT_TS))
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/* bit[11], Global timestamp tracing bit */
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config->cfg |= BIT(11);
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if (attr->config & BIT(ETM_OPT_CTXTID))
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/* bit[6], Context ID tracing bit */
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config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
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/* return stack - enable if selected and supported */
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if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
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/* bit[12], Return stack enable bit */
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@ -12,11 +12,13 @@
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/* ETMv3.5/PTM's ETMCR config bit */
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#define ETM_OPT_CYCACC 12
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#define ETM_OPT_CTXTID 14
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#define ETM_OPT_TS 28
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#define ETM_OPT_RETSTK 29
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/* ETMv4 CONFIGR programming bits for the ETM OPTs */
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#define ETM4_CFG_BIT_CYCACC 4
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#define ETM4_CFG_BIT_CTXTID 6
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#define ETM4_CFG_BIT_TS 11
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#define ETM4_CFG_BIT_RETSTK 12
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@ -12,11 +12,13 @@
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/* ETMv3.5/PTM's ETMCR config bit */
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#define ETM_OPT_CYCACC 12
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#define ETM_OPT_CTXTID 14
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#define ETM_OPT_TS 28
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#define ETM_OPT_RETSTK 29
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/* ETMv4 CONFIGR programming bits for the ETM OPTs */
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#define ETM4_CFG_BIT_CYCACC 4
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#define ETM4_CFG_BIT_CTXTID 6
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#define ETM4_CFG_BIT_TS 11
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#define ETM4_CFG_BIT_RETSTK 12
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