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clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150

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This adds the USB3 PIPE clock and GDSC structures, so
that the USB driver can vote for these resources to be
enabled/disabled when required.  Both are needed for SS
and HS USB paths to operate properly.  The GDSC will
allow the USB system to be brought out of reset, while
the PIPE clock is needed for data transactions between
the PHY and controller.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Link: https://lkml.kernel.org/r/1584478412-7798-2-git-send-email-wcheng@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Wesley Cheng 2020-03-17 13:53:31 -07:00 committed by Stephen Boyd
parent 1aec193ea4
commit 8411aa5059
2 changed files with 56 additions and 0 deletions
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52
drivers/clk/qcom/gcc-sm8150.c
View File

@ -21,6 +21,7 @@
#include "clk-rcg.h" #include "clk-rcg.h"
#include "clk-regmap.h" #include "clk-regmap.h"
#include "reset.h" #include "reset.h"
#include "gdsc.h"
enum { enum {
P_BI_TCXO, P_BI_TCXO,
@ -3171,6 +3172,18 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
}, },
}; };
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0xf058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_sec_clkref_clk = { static struct clk_branch gcc_usb3_sec_clkref_clk = {
.halt_reg = 0x8c028, .halt_reg = 0x8c028,
.halt_check = BRANCH_HALT, .halt_check = BRANCH_HALT,
@ -3218,6 +3231,18 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
}, },
}; };
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x10058,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk",
.ops = &clk_branch2_ops,
},
},
};
/* /*
* Clock ON depends on external parent 'config noc', so cant poll * Clock ON depends on external parent 'config noc', so cant poll
* delay and also mark as crtitical for video boot * delay and also mark as crtitical for video boot
@ -3292,6 +3317,24 @@ static struct clk_branch gcc_video_xo_clk = {
}, },
}; };
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0xf004,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x10004,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR,
};
static struct clk_regmap *gcc_sm8150_clocks[] = { static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
@ -3480,10 +3523,12 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
@ -3527,6 +3572,11 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
}; };
static struct gdsc *gcc_sm8150_gdscs[] = {
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
};
static const struct regmap_config gcc_sm8150_regmap_config = { static const struct regmap_config gcc_sm8150_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.reg_stride = 4, .reg_stride = 4,
@ -3541,6 +3591,8 @@ static const struct qcom_cc_desc gcc_sm8150_desc = {
.num_clks = ARRAY_SIZE(gcc_sm8150_clocks), .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
.resets = gcc_sm8150_resets, .resets = gcc_sm8150_resets,
.num_resets = ARRAY_SIZE(gcc_sm8150_resets), .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
.gdscs = gcc_sm8150_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
}; };
static const struct of_device_id gcc_sm8150_match_table[] = { static const struct of_device_id gcc_sm8150_match_table[] = {

4
include/dt-bindings/clock/qcom,gcc-sm8150.h
View File

@ -240,4 +240,8 @@
#define GCC_USB30_SEC_BCR 27 #define GCC_USB30_SEC_BCR 27
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
/* GCC GDSCRs */
#define USB30_PRIM_GDSC 4
#define USB30_SEC_GDSC 5
#endif #endif