forked from luck/tmp_suning_uos_patched
MIPS: lib: memset: Whitespace fixes
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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@ -74,7 +74,7 @@
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.align 5
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LEAF(memset)
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beqz a1, 1f
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move v0, a0 /* result */
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move v0, a0 /* result */
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andi a1, 0xff /* spread fillword */
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LONG_SLL t1, a1, 8
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@ -90,7 +90,7 @@ LEAF(memset)
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FEXPORT(__bzero)
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sltiu t0, a2, STORSIZE /* very small region? */
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bnez t0, .Lsmall_memset
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andi t0, a0, STORMASK /* aligned? */
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andi t0, a0, STORMASK /* aligned? */
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#ifdef CONFIG_CPU_MICROMIPS
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move t8, a1 /* used by 'swp' instruction */
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@ -98,12 +98,12 @@ FEXPORT(__bzero)
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#endif
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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#else
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.set noat
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li AT, STORSIZE
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beqz t0, 1f
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PTR_SUBU t0, AT /* alignment in bytes */
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PTR_SUBU t0, AT /* alignment in bytes */
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.set at
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#endif
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@ -120,7 +120,7 @@ FEXPORT(__bzero)
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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beqz t1, .Lmemset_partial /* no block to fill */
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andi t0, a2, 0x40-STORSIZE
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andi t0, a2, 0x40-STORSIZE
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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@ -145,7 +145,7 @@ FEXPORT(__bzero)
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.set at
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#endif
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jr t1
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PTR_ADDU a0, t0 /* dest ptr */
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PTR_ADDU a0, t0 /* dest ptr */
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.set push
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.set noreorder
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@ -155,7 +155,7 @@ FEXPORT(__bzero)
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andi a2, STORMASK /* At most one long to go */
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beqz a2, 1f
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PTR_ADDU a0, a2 /* What's left */
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PTR_ADDU a0, a2 /* What's left */
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
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@ -164,24 +164,24 @@ FEXPORT(__bzero)
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EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
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#endif
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1: jr ra
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move a2, zero
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move a2, zero
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.Lsmall_memset:
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beqz a2, 2f
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PTR_ADDU t1, a0, a2
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PTR_ADDU t1, a0, a2
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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bne t1, a0, 1b
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sb a1, -1(a0)
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sb a1, -1(a0)
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2: jr ra /* done */
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move a2, zero
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move a2, zero
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END(memset)
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.Lfirst_fixup:
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jr ra
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nop
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nop
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.Lfwd_fixup:
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PTR_L t0, TI_TASK($28)
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@ -189,7 +189,7 @@ FEXPORT(__bzero)
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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LONG_SUBU a2, t0
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.Lpartial_fixup:
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PTR_L t0, TI_TASK($28)
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@ -197,8 +197,8 @@ FEXPORT(__bzero)
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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LONG_SUBU a2, t0
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.Llast_fixup:
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jr ra
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andi v1, a2, STORMASK
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andi v1, a2, STORMASK
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