forked from luck/tmp_suning_uos_patched
spi: spi-fsl-dspi: Fixup regmap configuration
Mark volatile registers to avoid caching bugs. Note: SPI_MCR is marked volatile because of CLR_TXF and CLR_RXF bits. Signed-off-by: Esben Haabendal <eha@deif.com> Acked-by: Martin Hundebøll <martin@geanix.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -943,11 +943,23 @@ static int dspi_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
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static const struct regmap_range dspi_volatile_ranges[] = {
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regmap_reg_range(SPI_MCR, SPI_TCR),
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regmap_reg_range(SPI_SR, SPI_SR),
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regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
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};
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static const struct regmap_access_table dspi_volatile_table = {
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.yes_ranges = dspi_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
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};
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static const struct regmap_config dspi_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x88,
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.volatile_table = &dspi_volatile_table,
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};
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static void dspi_init(struct fsl_dspi *dspi)
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