forked from luck/tmp_suning_uos_patched
drm/radeon: Sync ME and PFP after CP semaphore waits v4
Fixes lockups due to CP read GPUVM faults when running piglit on Cape Verde. v2 (chk): apply the fix to R600+ as well, on CIK only the GFX CP has a PFP, add more comments to R600 code, enable flushing again v3: (agd5f): only apply to 7xx+. r6xx does not have the packet. v4: (agd5f): split flush change into a separate patch, fix formatting Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com>
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@ -3920,6 +3920,17 @@ void cik_fence_compute_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(ring, 0);
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}
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/**
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* cik_semaphore_ring_emit - emit a semaphore on the CP ring
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring buffer object
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* @semaphore: radeon semaphore object
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* @emit_wait: Is this a sempahore wait?
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*
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* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
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* from running ahead of semaphore waits.
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*/
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bool cik_semaphore_ring_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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@ -3932,6 +3943,12 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(ring, lower_32_bits(addr));
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
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if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
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/* Prevent the PFP from running ahead of the semaphore wait */
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radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
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radeon_ring_write(ring, 0x0);
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}
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return true;
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}
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@ -2753,6 +2753,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
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}
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}
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/**
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* r600_semaphore_ring_emit - emit a semaphore on the CP ring
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring buffer object
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* @semaphore: radeon semaphore object
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* @emit_wait: Is this a sempahore wait?
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*
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* Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
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* from running ahead of semaphore waits.
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*/
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bool r600_semaphore_ring_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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@ -2768,6 +2779,13 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(ring, lower_32_bits(addr));
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
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/* PFP_SYNC_ME packet only exists on 7xx+ */
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if (emit_wait && (rdev->family >= CHIP_RV770)) {
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/* Prevent the PFP from running ahead of the semaphore wait */
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radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
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radeon_ring_write(ring, 0x0);
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}
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return true;
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}
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@ -1597,6 +1597,7 @@
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*/
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# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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#define PACKET3_PFP_SYNC_ME 0x42 /* r7xx+ only */
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
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