forked from luck/tmp_suning_uos_patched
MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.h
Define a generic MIPS_GIC_IRQ_BASE which should be suitable for all current boards in <mach-generic/irq.h>. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -36,4 +36,10 @@
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#endif /* CONFIG_IRQ_CPU */
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#ifdef CONFIG_MIPS_GIC
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#ifndef MIPS_GIC_IRQ_BASE
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#endif
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#endif /* CONFIG_MIPS_GIC */
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#endif /* __ASM_MACH_GENERIC_IRQ_H */
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@ -10,8 +10,6 @@
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#ifndef _MIPS_MALTAINT_H
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#define _MIPS_MALTAINT_H
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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/*
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* Interrupts 0..15 are used for Malta ISA compatible interrupts
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*/
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@ -14,6 +14,4 @@
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#define GIC_BASE_ADDR 0x1b1c0000
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#define GIC_ADDRSPACE_SZ (128 * 1024)
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#endif /* !(_MIPS_SEAD3INT_H) */
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