forked from luck/tmp_suning_uos_patched
NTB: Register and offset values fix for memory window
Due to incorrect limit and translation register values, NTB link was going down when the memory window was setup. Made appropriate changes as per spec. Fix limit register values for BAR1, which was overlapping with the BAR23 address. Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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@ -138,11 +138,11 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
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base_addr = pci_resource_start(ndev->ntb.pdev, bar);
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if (bar != 1) {
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xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 3);
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limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 3);
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xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2);
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limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 2);
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/* Set the limit if supported */
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limit = base_addr + size;
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limit = size;
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/* set and verify setting the translation address */
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write64(addr, peer_mmio + xlat_reg);
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@ -164,14 +164,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx,
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xlat_reg = AMD_BAR1XLAT_OFFSET;
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limit_reg = AMD_BAR1LMT_OFFSET;
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/* split bar addr range must all be 32 bit */
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if (addr & (~0ull << 32))
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return -EINVAL;
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if ((addr + size) & (~0ull << 32))
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return -EINVAL;
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/* Set the limit if supported */
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limit = base_addr + size;
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limit = size;
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/* set and verify setting the translation address */
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write64(addr, peer_mmio + xlat_reg);
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