forked from luck/tmp_suning_uos_patched
KVM: arm/arm64: vgic: Signal IRQs using their configured group
Now when we have a group configuration on the struct IRQ, use this state when populating the LR and signaling interrupts as either group 0 or group 1 to the VM. Depending on the model of the emulated GIC, and the guest's configuration of the VMCR, interrupts may be signaled as IRQs or FIQs to the VM. Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -104,6 +104,7 @@
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#define GICH_LR_PENDING_BIT (1 << 28)
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#define GICH_LR_ACTIVE_BIT (1 << 29)
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#define GICH_LR_EOI (1 << 19)
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#define GICH_LR_GROUP1 (1 << 30)
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#define GICH_LR_HW (1 << 31)
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#define GICH_VMCR_ENABLE_GRP0_SHIFT 0
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@ -159,6 +159,9 @@ void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
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}
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}
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if (irq->group)
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val |= GICH_LR_GROUP1;
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if (irq->hw) {
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val |= GICH_LR_HW;
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val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
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@ -197,11 +197,7 @@ void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
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if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
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irq->line_level = false;
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/*
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* We currently only support Group1 interrupts, which is a
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* known defect. This needs to be addressed at some point.
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*/
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if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
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if (irq->group)
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val |= ICH_LR_GROUP;
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val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
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