forked from luck/tmp_suning_uos_patched
arm64: Add boot time configuration of Intermediate Physical Address size
ARMv8 supports a range of physical address bit sizes. The PARange bits from ID_AA64MMFR0_EL1 register are read during boot-time and the intermediate physical address size bits are written in the translation control registers (TCR_EL1 and VTCR_EL2). There is no change in the VA bits and levels of translation. Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Will Deacon <Will.deacon@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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parent
71fdb6bf61
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87366d8cf7
arch/arm64
@ -106,7 +106,6 @@
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/* VTCR_EL2 Registers bits */
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#define VTCR_EL2_PS_MASK (7 << 16)
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#define VTCR_EL2_PS_40B (2 << 16)
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#define VTCR_EL2_TG0_MASK (1 << 14)
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#define VTCR_EL2_TG0_4K (0 << 14)
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#define VTCR_EL2_TG0_64K (1 << 14)
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@ -129,10 +128,9 @@
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* 64kB pages (TG0 = 1)
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* 2 level page tables (SL = 1)
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*/
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#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \
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VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
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VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
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VTCR_EL2_T0SZ_40B)
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#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \
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VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
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VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
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#define VTTBR_X (38 - VTCR_EL2_T0SZ_40B)
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#else
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/*
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@ -142,10 +140,9 @@
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* 4kB pages (TG0 = 0)
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* 3 level page tables (SL = 1)
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*/
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#define VTCR_EL2_FLAGS (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \
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VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
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VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
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VTCR_EL2_T0SZ_40B)
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#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \
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VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \
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VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)
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#define VTTBR_X (37 - VTCR_EL2_T0SZ_40B)
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#endif
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@ -100,9 +100,9 @@
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#define PTE_HYP PTE_USER
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/*
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* 40-bit physical address supported.
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* Highest possible physical address supported.
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*/
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#define PHYS_MASK_SHIFT (40)
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#define PHYS_MASK_SHIFT (48)
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#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
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/*
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@ -122,7 +122,6 @@
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#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
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#define TCR_TG0_64K (UL(1) << 14)
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#define TCR_TG1_64K (UL(1) << 30)
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#define TCR_IPS_40BIT (UL(2) << 32)
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#define TCR_ASID16 (UL(1) << 36)
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#define TCR_TBI0 (UL(1) << 37)
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@ -68,6 +68,12 @@ __do_hyp_init:
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msr tcr_el2, x4
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ldr x4, =VTCR_EL2_FLAGS
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/*
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* Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in
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* VTCR_EL2.
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*/
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mrs x5, ID_AA64MMFR0_EL1
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bfi x4, x5, #16, #3
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msr vtcr_el2, x4
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mrs x4, mair_el1
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@ -209,8 +209,14 @@ ENTRY(__cpu_setup)
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* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
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* both user and kernel.
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*/
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ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
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ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \
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TCR_ASID16 | TCR_TBI0 | (1 << 31)
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/*
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* Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
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* TCR_EL1.
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*/
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mrs x9, ID_AA64MMFR0_EL1
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bfi x10, x9, #32, #3
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#ifdef CONFIG_ARM64_64K_PAGES
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orr x10, x10, TCR_TG0_64K
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orr x10, x10, TCR_TG1_64K
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