forked from luck/tmp_suning_uos_patched
drm/nv50: rewrite display irq handler
The previous handler basically worked correctly for a full-blown mode change. However, it did nothing at all when a partial (encoder only) reconfiguation was necessary, leading to the display hanging on certain types of mode switch. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
835aadbef3
commit
87c0e0e513
@ -610,6 +610,11 @@ struct drm_nouveau_private {
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struct backlight_device *backlight;
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struct nouveau_channel *evo;
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struct {
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struct dcb_entry *dcb;
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u16 script;
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u32 pclk;
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} evo_irq;
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struct {
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struct dentry *channel_root;
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@ -559,131 +559,28 @@ int nv50_display_destroy(struct drm_device *dev)
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return 0;
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}
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static inline uint32_t
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nv50_display_mode_ctrl(struct drm_device *dev, bool sor, int or)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t mc;
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if (sor) {
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if (dev_priv->chipset < 0x90 ||
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dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
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mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(or));
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else
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mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(or));
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} else {
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mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(or));
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}
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return mc;
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}
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static int
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nv50_display_irq_head(struct drm_device *dev, int *phead,
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struct dcb_entry **pdcbent)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t unk30 = nv_rd32(dev, NV50_PDISPLAY_UNK30_CTRL);
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uint32_t dac = 0, sor = 0;
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int head, i, or = 0, type = OUTPUT_ANY;
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/* We're assuming that head 0 *or* head 1 will be active here,
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* and not both. I'm not sure if the hw will even signal both
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* ever, but it definitely shouldn't for us as we commit each
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* CRTC separately, and submission will be blocked by the GPU
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* until we handle each in turn.
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*/
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NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
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head = ffs((unk30 >> 9) & 3) - 1;
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if (head < 0)
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return -EINVAL;
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/* This assumes CRTCs are never bound to multiple encoders, which
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* should be the case.
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*/
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for (i = 0; i < 3 && type == OUTPUT_ANY; i++) {
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uint32_t mc = nv50_display_mode_ctrl(dev, false, i);
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if (!(mc & (1 << head)))
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continue;
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switch ((mc >> 8) & 0xf) {
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case 0: type = OUTPUT_ANALOG; break;
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case 1: type = OUTPUT_TV; break;
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default:
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NV_ERROR(dev, "unknown dac mode_ctrl: 0x%08x\n", dac);
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return -1;
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}
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or = i;
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}
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for (i = 0; i < 4 && type == OUTPUT_ANY; i++) {
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uint32_t mc = nv50_display_mode_ctrl(dev, true, i);
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if (!(mc & (1 << head)))
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continue;
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switch ((mc >> 8) & 0xf) {
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case 0: type = OUTPUT_LVDS; break;
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case 1: type = OUTPUT_TMDS; break;
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case 2: type = OUTPUT_TMDS; break;
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case 5: type = OUTPUT_TMDS; break;
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case 8: type = OUTPUT_DP; break;
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case 9: type = OUTPUT_DP; break;
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default:
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NV_ERROR(dev, "unknown sor mode_ctrl: 0x%08x\n", sor);
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return -1;
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}
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or = i;
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}
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NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
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if (type == OUTPUT_ANY) {
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NV_ERROR(dev, "unknown encoder!!\n");
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return -1;
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}
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for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
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struct dcb_entry *dcbent = &dev_priv->vbios.dcb.entry[i];
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if (dcbent->type != type)
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continue;
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if (!(dcbent->or & (1 << or)))
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continue;
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*phead = head;
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*pdcbent = dcbent;
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return 0;
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}
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NV_ERROR(dev, "no DCB entry for %d %d\n", dac != 0, or);
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return 0;
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}
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static uint32_t
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nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
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int pxclk)
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static u16
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nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
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u32 mc, int pxclk)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_connector *nv_connector = NULL;
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struct drm_encoder *encoder;
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struct nvbios *bios = &dev_priv->vbios;
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uint32_t mc, script = 0, or;
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u32 script = 0, or;
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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if (nv_encoder->dcb != dcbent)
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if (nv_encoder->dcb != dcb)
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continue;
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nv_connector = nouveau_encoder_connector_get(nv_encoder);
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break;
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}
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or = ffs(dcbent->or) - 1;
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mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
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switch (dcbent->type) {
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or = ffs(dcb->or) - 1;
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switch (dcb->type) {
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case OUTPUT_LVDS:
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script = (mc >> 8) & 0xf;
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if (bios->fp_no_ddc) {
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@ -774,17 +671,88 @@ nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
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static void
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nv50_display_unk10_handler(struct drm_device *dev)
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{
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struct dcb_entry *dcbent;
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int head, ret;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 unk30 = nv_rd32(dev, 0x610030), mc;
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int i, crtc, or, type = OUTPUT_ANY;
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ret = nv50_display_irq_head(dev, &head, &dcbent);
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if (ret)
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goto ack;
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NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
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dev_priv->evo_irq.dcb = NULL;
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nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
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nouveau_bios_run_display_table(dev, dcbent, 0, -1);
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/* Determine which CRTC we're dealing with, only 1 ever will be
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* signalled at the same time with the current nouveau code.
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*/
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crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
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if (crtc < 0)
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goto ack;
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/* Nothing needs to be done for the encoder */
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crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
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if (crtc < 0)
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goto ack;
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/* Find which encoder was connected to the CRTC */
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for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
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mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
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NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
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if (!(mc & (1 << crtc)))
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continue;
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switch ((mc & 0x00000f00) >> 8) {
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case 0: type = OUTPUT_ANALOG; break;
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case 1: type = OUTPUT_TV; break;
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default:
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NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
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goto ack;
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}
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or = i;
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}
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for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
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if (dev_priv->chipset < 0x90 ||
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dev_priv->chipset == 0x92 ||
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dev_priv->chipset == 0xa0)
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mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
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else
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mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
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NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
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if (!(mc & (1 << crtc)))
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continue;
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switch ((mc & 0x00000f00) >> 8) {
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case 0: type = OUTPUT_LVDS; break;
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case 1: type = OUTPUT_TMDS; break;
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case 2: type = OUTPUT_TMDS; break;
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case 5: type = OUTPUT_TMDS; break;
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case 8: type = OUTPUT_DP; break;
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case 9: type = OUTPUT_DP; break;
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default:
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NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
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goto ack;
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}
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or = i;
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}
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/* There was no encoder to disable */
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if (type == OUTPUT_ANY)
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goto ack;
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/* Disable the encoder */
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for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
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struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
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if (dcb->type == type && (dcb->or & (1 << or))) {
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nouveau_bios_run_display_table(dev, dcb, 0, -1);
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dev_priv->evo_irq.dcb = dcb;
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goto ack;
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}
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}
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NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
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ack:
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nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
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nv_wr32(dev, 0x610030, 0x80000000);
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@ -854,34 +822,104 @@ nv50_display_unk20_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
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static void
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nv50_display_unk20_handler(struct drm_device *dev)
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{
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struct dcb_entry *dcbent;
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uint32_t tmp, pclk, script;
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int head, or, ret;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
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struct dcb_entry *dcb;
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int i, crtc, or, type = OUTPUT_ANY;
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ret = nv50_display_irq_head(dev, &head, &dcbent);
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if (ret)
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NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
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dcb = dev_priv->evo_irq.dcb;
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if (dcb) {
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nouveau_bios_run_display_table(dev, dcb, 0, -2);
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dev_priv->evo_irq.dcb = NULL;
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}
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/* CRTC clock change requested? */
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crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
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if (crtc >= 0) {
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pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
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pclk &= 0x003fffff;
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nv50_crtc_set_clock(dev, crtc, pclk);
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tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
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tmp &= ~0x000000f;
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nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
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}
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/* Nothing needs to be done for the encoder */
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crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
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if (crtc < 0)
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goto ack;
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or = ffs(dcbent->or) - 1;
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pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
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script = nv50_display_script_select(dev, dcbent, pclk);
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pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
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NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
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/* Find which encoder is connected to the CRTC */
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for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
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mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
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NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
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if (!(mc & (1 << crtc)))
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continue;
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if (dcbent->type != OUTPUT_DP)
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nouveau_bios_run_display_table(dev, dcbent, 0, -2);
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switch ((mc & 0x00000f00) >> 8) {
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case 0: type = OUTPUT_ANALOG; break;
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case 1: type = OUTPUT_TV; break;
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default:
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NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
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goto ack;
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}
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nv50_crtc_set_clock(dev, head, pclk);
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or = i;
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}
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nouveau_bios_run_display_table(dev, dcbent, script, pclk);
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for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
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if (dev_priv->chipset < 0x90 ||
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dev_priv->chipset == 0x92 ||
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dev_priv->chipset == 0xa0)
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mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
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else
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mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
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nv50_display_unk20_dp_hack(dev, dcbent);
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nv50_display_unk20_dp_set_tmds(dev, dcbent);
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NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
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if (!(mc & (1 << crtc)))
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continue;
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tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
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tmp &= ~0x000000f;
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nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);
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switch ((mc & 0x00000f00) >> 8) {
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case 0: type = OUTPUT_LVDS; break;
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case 1: type = OUTPUT_TMDS; break;
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case 2: type = OUTPUT_TMDS; break;
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case 5: type = OUTPUT_TMDS; break;
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case 8: type = OUTPUT_DP; break;
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case 9: type = OUTPUT_DP; break;
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default:
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NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
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goto ack;
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}
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if (dcbent->type != OUTPUT_ANALOG) {
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or = i;
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}
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if (type == OUTPUT_ANY)
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goto ack;
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/* Enable the encoder */
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for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
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dcb = &dev_priv->vbios.dcb.entry[i];
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if (dcb->type == type && (dcb->or & (1 << or)))
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break;
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}
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if (i == dev_priv->vbios.dcb.entries) {
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NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
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goto ack;
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}
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script = nv50_display_script_select(dev, dcb, mc, pclk);
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nouveau_bios_run_display_table(dev, dcb, script, pclk);
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nv50_display_unk20_dp_hack(dev, dcb);
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nv50_display_unk20_dp_set_tmds(dev, dcb);
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if (dcb->type != OUTPUT_ANALOG) {
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tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
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tmp &= ~0x00000f0f;
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if (script & 0x0100)
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@ -891,6 +929,10 @@ nv50_display_unk20_handler(struct drm_device *dev)
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nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
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}
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dev_priv->evo_irq.dcb = dcb;
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dev_priv->evo_irq.pclk = pclk;
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dev_priv->evo_irq.script = script;
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ack:
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nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
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nv_wr32(dev, 0x610030, 0x80000000);
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@ -899,17 +941,17 @@ nv50_display_unk20_handler(struct drm_device *dev)
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static void
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nv50_display_unk40_handler(struct drm_device *dev)
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{
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struct dcb_entry *dcbent;
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int head, pclk, script, ret;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
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u16 script = dev_priv->evo_irq.script;
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u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
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ret = nv50_display_irq_head(dev, &head, &dcbent);
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if (ret)
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NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
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dev_priv->evo_irq.dcb = NULL;
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if (!dcb)
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goto ack;
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pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
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script = nv50_display_script_select(dev, dcbent, pclk);
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nouveau_bios_run_display_table(dev, dcbent, script, -pclk);
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nouveau_bios_run_display_table(dev, dcb, script, -pclk);
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ack:
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nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
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nv_wr32(dev, 0x610030, 0x80000000);
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