forked from luck/tmp_suning_uos_patched
[IA64] Schedule ia64_leave_syscall() to read ar.bsp earlier
Reschedule code to read ar.bsp as early as possible. To enable this, don't bother clearing some of the registers when we're returning to kernel stacks. Also, instead of trying to support the pNonSys case (which makes no sense), do a bugcheck instead (with break 0). Finally, remove a clear of r14 which is a left-over from the previous patch. Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -694,22 +694,22 @@ ENTRY(ia64_leave_syscall)
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ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
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nop.i 0
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;;
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ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
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mov r16=ar.bsp // M2 get existing backing store pointer
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ld8 r18=[r2],PT(R9)-PT(B6) // load b6
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(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
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;;
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mov r16=ar.bsp // M2 get existing backing store pointer
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ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
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(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
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(p6) br.cond.spnt .work_pending_syscall
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;;
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// start restoring the state saved on the kernel stack (struct pt_regs):
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ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
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ld8 r11=[r3],PT(CR_IIP)-PT(R11)
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nop.i 0
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(pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
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;;
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invala // M0|1 invalidate ALAT
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rsm psr.i | psr.ic // M2 initiate turning off of interrupt and interruption collection
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nop.i 0
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cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
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ld8 r29=[r2],16 // load cr.ipsr
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ld8 r28=[r3],16 // load cr.iip
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@ -717,11 +717,11 @@ ENTRY(ia64_leave_syscall)
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;;
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ld8 r30=[r2],16 // M0|1 load cr.ifs
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ld8 r25=[r3],16 // M0|1 load ar.unat
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cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
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(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
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;;
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ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
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(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled
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(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
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nop 0
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;;
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ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // load b0
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ld8 r27=[r3],PT(PR)-PT(AR_RSC) // load ar.rsc
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@ -735,40 +735,35 @@ ENTRY(ia64_leave_syscall)
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ld8.fill r1=[r3],16 // load r1
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(pUStk) mov r17=1
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;;
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srlz.d // M0 ensure interruption collection is off
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(pUStk) st1 [r14]=r17
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ld8.fill r13=[r3],16
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mov f8=f0 // clear f8
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;;
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ld8.fill r12=[r2] // restore r12 (sp)
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mov.m ar.ssd=r0 // M2 clear ar.ssd
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ld8.fill r15=[r3] // restore r15
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mov b6=r18 // I0 restore b6
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nop.m 0
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addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0
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mov f9=f0 // clear f9
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(pKStk) br.cond.dpnt.many skip_rbs_switch
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srlz.d // M0 ensure interruption collection is off
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shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
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cover // B add current frame into dirty partition and set cr.ifs
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;;
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ld8.fill r15=[r3] // restore r15
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(pUStk) st1 [r14]=r17
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addl r3=THIS_CPU(ia64_phys_stacked_size_p8),r0
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;;
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(pUStk) ld4 r17=[r3] // r17 = cpu_data->phys_stacked_size_p8
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mov.m ar.csd=r0 // M2 clear ar.csd
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(pUStk) ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8
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mov r19=ar.bsp // M2 get new backing store pointer
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mov f10=f0 // clear f10
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nop.m 0
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movl r14=__kernel_syscall_via_epc // X
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;;
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nop.m 0
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nop.m 0
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mov.m ar.csd=r0 // M2 clear ar.csd
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mov.m ar.ccv=r0 // clear ar.ccv
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mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
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mov r14=r0 // clear r14
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mov.m ar.ssd=r0 // M2 clear ar.ssd
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mov f11=f0 // clear f11
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(pKStk) br.cond.dpnt.many skip_rbs_switch
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mov.m ar.ccv=r0 // clear ar.ccv
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(pNonSys) br.cond.dpnt.many dont_preserve_current_frame
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br.cond.sptk.many rbs_switch
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END(ia64_leave_syscall)
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@ -946,10 +941,10 @@ GLOBAL_ENTRY(ia64_leave_kernel)
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*/
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(pNonSys) br.cond.dpnt dont_preserve_current_frame
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rbs_switch:
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cover // add current frame into dirty partition and set cr.ifs
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;;
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mov r19=ar.bsp // get new backing store pointer
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rbs_switch:
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sub r16=r16,r18 // krbs = old bsp - size of dirty partition
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cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
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;;
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