forked from luck/tmp_suning_uos_patched
clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related clk pointer gets cached in the driver's private data and can be used later instead of a __clk_lookup() call. With that we have all clocks used in the clk_prepare_enable() calls in the clk provider init callback cached in clk_data.hws[] and we can reference the clk pointers directly rather than using __clk_lookup() with global names. Link: https://lore.kernel.org/r/20200811151251.31613-2-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -712,8 +712,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
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SRC_TOP12, 8, 1),
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MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
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SRC_TOP12, 12, 1),
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MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
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CLK_SET_RATE_PARENT, 0),
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MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
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SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
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MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
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SRC_TOP12, 20, 1),
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MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
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@ -1560,6 +1560,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
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enum exynos5x_soc soc)
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{
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struct samsung_clk_provider *ctx;
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struct clk_hw **hws;
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if (np) {
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reg_base = of_iomap(np, 0);
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@ -1649,17 +1650,18 @@ static void __init exynos5x_clk_init(struct device_node *np,
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exynos5x_subcmus);
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}
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hws = ctx->clk_data.hws;
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/*
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* Keep top part of G3D clock path enabled permanently to ensure
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* that the internal busses get their clock regardless of the
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* main G3D clock enablement status.
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*/
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clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
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clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
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/*
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* Keep top BPLL mux enabled permanently to ensure that DRAM operates
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* properly.
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*/
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clk_prepare_enable(__clk_lookup("mout_bpll"));
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clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
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samsung_clk_of_add_provider(np, ctx);
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}
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