forked from luck/tmp_suning_uos_patched
ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file
G2D clock registers are different in EXYNOS4210 and EXYNOS4X12 SoCs. Hence moving the SoC specific G2D clock entries from common clock file (clock-exynos4.c) to EXYNOS4210 specific clock file (clock-exynos4210.c). Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -619,10 +619,6 @@ static struct clk exynos4_init_clocks_off[] = {
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.devname = "samsung-ac97",
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 27),
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "mfc",
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.devname = "s5p-mfc",
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@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = {
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[1] = &exynos4_clk_sclk_apll.clk,
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};
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static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
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struct clksrc_sources exynos4_clkset_mout_g2d0 = {
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.sources = exynos4_clkset_mout_g2d0_list,
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.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
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};
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static struct clksrc_clk exynos4_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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};
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static struct clk *exynos4_clkset_mout_g2d1_list[] = {
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[0] = &exynos4_clk_mout_epll.clk,
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[1] = &exynos4_clk_sclk_vpll.clk,
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};
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static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
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struct clksrc_sources exynos4_clkset_mout_g2d1 = {
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.sources = exynos4_clkset_mout_g2d1_list,
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.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
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};
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static struct clksrc_clk exynos4_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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};
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static struct clk *exynos4_clkset_mout_g2d_list[] = {
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[0] = &exynos4_clk_mout_g2d0.clk,
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[1] = &exynos4_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4_clkset_mout_g2d = {
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.sources = exynos4_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
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};
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static struct clk *exynos4_clkset_mout_mfc0_list[] = {
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[0] = &exynos4_clk_mout_mpll.clk,
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[1] = &exynos4_clk_sclk_apll.clk,
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@ -1124,13 +1094,6 @@ static struct clksrc_clk exynos4_clksrcs[] = {
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.sources = &exynos4_clkset_group,
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.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mfc",
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@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group;
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extern struct clk *exynos4_clkset_aclk_top_list[];
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extern struct clk *exynos4_clkset_group_list[];
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extern struct clksrc_sources exynos4_clkset_mout_g2d0;
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extern struct clksrc_sources exynos4_clkset_mout_g2d1;
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extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
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extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
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@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = {
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/* nothing here yet */
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};
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static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
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.clk = {
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.name = "mout_g2d0",
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},
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.sources = &exynos4_clkset_mout_g2d0,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
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.clk = {
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.name = "mout_g2d1",
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},
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.sources = &exynos4_clkset_mout_g2d1,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
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};
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static struct clk *exynos4210_clkset_mout_g2d_list[] = {
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[0] = &exynos4210_clk_mout_g2d0.clk,
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[1] = &exynos4210_clk_mout_g2d1.clk,
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};
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static struct clksrc_sources exynos4210_clkset_mout_g2d = {
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.sources = exynos4210_clkset_mout_g2d_list,
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.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
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};
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static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
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@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = {
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.sources = &exynos4_clkset_group,
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.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
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.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimg2d",
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},
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.sources = &exynos4210_clkset_mout_g2d,
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.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
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.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
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},
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};
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@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = {
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.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "fimg2d",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 0),
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},
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};
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