forked from luck/tmp_suning_uos_patched
net: dsa: microchip: add KSZ9893 switch support
Add KSZ9893 switch support in KSZ9477 driver. This switch is similar to KSZ9477 except the ingress tail tag has 1 byte instead of 2 bytes, so KSZ9893 tagging will be used. The XMII register that governs how the host port communicates with the MAC also has different register definitions. Signed-off-by: Tristram Ha <Tristram.Ha@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tristram Ha
David S. Miller
parent
88b573af91
commit
8c29bebb1f
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@ -18,6 +18,11 @@
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#include "ksz9477_reg.h"
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#include "ksz_common.h"
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/* Used with variable features to indicate capabilities. */
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#define GBIT_SUPPORT BIT(0)
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#define NEW_XMII BIT(1)
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#define IS_9893 BIT(2)
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static const struct {
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int index;
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char string[ETH_GSTRING_LEN];
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@ -328,7 +333,12 @@ static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
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static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
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int port)
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{
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return DSA_TAG_PROTO_KSZ9477;
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enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
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struct ksz_device *dev = ds->priv;
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if (dev->features & IS_9893)
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proto = DSA_TAG_PROTO_KSZ9893;
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return proto;
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}
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static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
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@ -389,6 +399,10 @@ static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
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/* No real PHY after this. */
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if (addr >= dev->phy_port_cnt)
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return 0;
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/* No gigabit support. Do not write to this register. */
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if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
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return 0;
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ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
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return 0;
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@ -998,13 +1012,158 @@ static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
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static void ksz9477_phy_setup(struct ksz_device *dev, int port,
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struct phy_device *phy)
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{
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if (port < dev->phy_port_cnt) {
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/* The MAC actually cannot run in 1000 half-duplex mode. */
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/* Only apply to port with PHY. */
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if (port >= dev->phy_port_cnt)
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return;
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/* The MAC actually cannot run in 1000 half-duplex mode. */
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phy_remove_link_mode(phy,
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ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
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/* PHY does not support gigabit. */
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if (!(dev->features & GBIT_SUPPORT))
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phy_remove_link_mode(phy,
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ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
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ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
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}
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static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
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{
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bool gbit;
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if (dev->features & NEW_XMII)
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gbit = !(data & PORT_MII_NOT_1GBIT);
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else
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gbit = !!(data & PORT_MII_1000MBIT_S1);
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return gbit;
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}
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static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
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{
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if (dev->features & NEW_XMII) {
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if (gbit)
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*data &= ~PORT_MII_NOT_1GBIT;
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else
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*data |= PORT_MII_NOT_1GBIT;
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} else {
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if (gbit)
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*data |= PORT_MII_1000MBIT_S1;
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else
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*data &= ~PORT_MII_1000MBIT_S1;
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}
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}
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static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
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{
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int mode;
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if (dev->features & NEW_XMII) {
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switch (data & PORT_MII_SEL_M) {
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case PORT_MII_SEL:
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mode = 0;
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break;
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case PORT_RMII_SEL:
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mode = 1;
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break;
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case PORT_GMII_SEL:
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mode = 2;
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break;
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default:
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mode = 3;
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}
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} else {
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switch (data & PORT_MII_SEL_M) {
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case PORT_MII_SEL_S1:
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mode = 0;
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break;
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case PORT_RMII_SEL_S1:
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mode = 1;
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break;
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case PORT_GMII_SEL_S1:
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mode = 2;
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break;
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default:
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mode = 3;
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}
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}
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return mode;
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}
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static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
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{
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u8 xmii;
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if (dev->features & NEW_XMII) {
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switch (mode) {
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case 0:
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xmii = PORT_MII_SEL;
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break;
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case 1:
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xmii = PORT_RMII_SEL;
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break;
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case 2:
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xmii = PORT_GMII_SEL;
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break;
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default:
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xmii = PORT_RGMII_SEL;
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break;
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}
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} else {
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switch (mode) {
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case 0:
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xmii = PORT_MII_SEL_S1;
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break;
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case 1:
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xmii = PORT_RMII_SEL_S1;
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break;
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case 2:
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xmii = PORT_GMII_SEL_S1;
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break;
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default:
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xmii = PORT_RGMII_SEL_S1;
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break;
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}
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}
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*data &= ~PORT_MII_SEL_M;
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*data |= xmii;
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}
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static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
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{
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phy_interface_t interface;
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bool gbit;
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int mode;
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u8 data8;
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if (port < dev->phy_port_cnt)
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return PHY_INTERFACE_MODE_NA;
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ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
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gbit = ksz9477_get_gbit(dev, data8);
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mode = ksz9477_get_xmii(dev, data8);
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switch (mode) {
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case 2:
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interface = PHY_INTERFACE_MODE_GMII;
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if (gbit)
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break;
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case 0:
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interface = PHY_INTERFACE_MODE_MII;
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break;
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case 1:
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interface = PHY_INTERFACE_MODE_RMII;
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break;
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default:
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interface = PHY_INTERFACE_MODE_RGMII;
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if (data8 & PORT_RGMII_ID_EG_ENABLE)
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interface = PHY_INTERFACE_MODE_RGMII_TXID;
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if (data8 & PORT_RGMII_ID_IG_ENABLE) {
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interface = PHY_INTERFACE_MODE_RGMII_RXID;
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if (data8 & PORT_RGMII_ID_EG_ENABLE)
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interface = PHY_INTERFACE_MODE_RGMII_ID;
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}
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break;
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}
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return interface;
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}
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static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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{
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u8 data8;
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@ -1051,24 +1210,25 @@ static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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/* configure MAC to 1G & RGMII mode */
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ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
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data8 &= ~PORT_MII_NOT_1GBIT;
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data8 &= ~PORT_MII_SEL_M;
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switch (dev->interface) {
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case PHY_INTERFACE_MODE_MII:
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data8 |= PORT_MII_NOT_1GBIT;
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data8 |= PORT_MII_SEL;
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ksz9477_set_xmii(dev, 0, &data8);
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ksz9477_set_gbit(dev, false, &data8);
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p->phydev.speed = SPEED_100;
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break;
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case PHY_INTERFACE_MODE_RMII:
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data8 |= PORT_MII_NOT_1GBIT;
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data8 |= PORT_RMII_SEL;
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ksz9477_set_xmii(dev, 1, &data8);
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ksz9477_set_gbit(dev, false, &data8);
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p->phydev.speed = SPEED_100;
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break;
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case PHY_INTERFACE_MODE_GMII:
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data8 |= PORT_GMII_SEL;
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ksz9477_set_xmii(dev, 2, &data8);
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ksz9477_set_gbit(dev, true, &data8);
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p->phydev.speed = SPEED_1000;
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break;
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default:
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ksz9477_set_xmii(dev, 3, &data8);
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ksz9477_set_gbit(dev, true, &data8);
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data8 &= ~PORT_RGMII_ID_IG_ENABLE;
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data8 &= ~PORT_RGMII_ID_EG_ENABLE;
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if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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@ -1077,7 +1237,6 @@ static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
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if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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data8 |= PORT_RGMII_ID_EG_ENABLE;
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data8 |= PORT_RGMII_SEL;
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p->phydev.speed = SPEED_1000;
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break;
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}
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@ -1115,10 +1274,25 @@ static void ksz9477_config_cpu_port(struct dsa_switch *ds)
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for (i = 0; i < dev->port_cnt; i++) {
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if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
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phy_interface_t interface;
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dev->cpu_port = i;
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dev->host_mask = (1 << dev->cpu_port);
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dev->port_mask |= dev->host_mask;
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/* Read from XMII register to determine host port
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* interface. If set specifically in device tree
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* note the difference to help debugging.
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*/
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interface = ksz9477_get_interface(dev, i);
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if (!dev->interface)
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dev->interface = interface;
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if (interface && interface != dev->interface)
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dev_info(dev->dev,
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"use %s instead of %s\n",
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phy_modes(dev->interface),
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phy_modes(interface));
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/* enable cpu port */
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ksz9477_port_setup(dev, i, true);
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p = &dev->ports[dev->cpu_port];
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@ -1172,6 +1346,9 @@ static int ksz9477_setup(struct dsa_switch *ds)
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ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
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true);
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/* Do not work correctly with tail tagging. */
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ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
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/* accept packet up to 2000bytes */
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ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
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@ -1230,6 +1407,8 @@ static u32 ksz9477_get_port_addr(int port, int offset)
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static int ksz9477_switch_detect(struct ksz_device *dev)
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{
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u8 data8;
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u8 id_hi;
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u8 id_lo;
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u32 id32;
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int ret;
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@ -1245,6 +1424,9 @@ static int ksz9477_switch_detect(struct ksz_device *dev)
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/* read chip id */
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ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
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if (ret)
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return ret;
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ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
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if (ret)
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return ret;
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@ -1252,6 +1434,32 @@ static int ksz9477_switch_detect(struct ksz_device *dev)
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dev->mib_port_cnt = TOTAL_PORT_NUM;
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dev->phy_port_cnt = 5;
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/* Default capability is gigabit capable. */
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dev->features = GBIT_SUPPORT;
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id_hi = (u8)(id32 >> 16);
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id_lo = (u8)(id32 >> 8);
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if ((id_lo & 0xf) == 3) {
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/* Chip is from KSZ9893 design. */
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dev->features |= IS_9893;
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/* Chip does not support gigabit. */
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if (data8 & SW_QW_ABLE)
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dev->features &= ~GBIT_SUPPORT;
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dev->mib_port_cnt = 3;
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dev->phy_port_cnt = 2;
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} else {
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/* Chip uses new XMII register definitions. */
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dev->features |= NEW_XMII;
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/* Chip does not support gigabit. */
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if (!(data8 & SW_GIGABIT_ABLE))
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dev->features &= ~GBIT_SUPPORT;
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}
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/* Change chip id to known ones so it can be matched against them. */
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id32 = (id_hi << 16) | (id_lo << 8);
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dev->chip_id = id32;
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return 0;
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@ -1286,6 +1494,15 @@ static const struct ksz_chip_data ksz9477_switch_chips[] = {
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.cpu_ports = 0x7F, /* can be configured as cpu port */
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.port_cnt = 7, /* total physical port count */
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},
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{
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.chip_id = 0x00989300,
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.dev_name = "KSZ9893",
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.num_vlans = 4096,
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.num_alus = 4096,
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.num_statics = 16,
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.cpu_ports = 0x07, /* can be configured as cpu port */
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.port_cnt = 3, /* total port count */
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},
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};
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static int ksz9477_switch_init(struct ksz_device *dev)
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@ -1333,7 +1550,6 @@ static int ksz9477_switch_init(struct ksz_device *dev)
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if (!dev->ports[i].mib.counters)
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return -ENOMEM;
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}
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dev->interface = PHY_INTERFACE_MODE_RGMII_TXID;
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return 0;
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}
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@ -2,7 +2,7 @@
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/*
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* Microchip KSZ9477 series register access through SPI
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*
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* Copyright (C) 2017-2018 Microchip Technology Inc.
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* Copyright (C) 2017-2019 Microchip Technology Inc.
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*/
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#include <asm/unaligned.h>
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@ -155,6 +155,8 @@ static void ksz9477_spi_shutdown(struct spi_device *spi)
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static const struct of_device_id ksz9477_dt_ids[] = {
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{ .compatible = "microchip,ksz9477" },
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{ .compatible = "microchip,ksz9897" },
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{ .compatible = "microchip,ksz9893" },
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{ .compatible = "microchip,ksz9563" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ksz9477_dt_ids);
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@ -453,7 +453,9 @@ int ksz_switch_register(struct ksz_device *dev,
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if (ret)
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return ret;
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dev->interface = PHY_INTERFACE_MODE_MII;
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/* Host port interface will be self detected, or specifically set in
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* device tree.
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*/
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if (dev->dev->of_node) {
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ret = of_get_phy_mode(dev->dev->of_node);
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if (ret >= 0)
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