forked from luck/tmp_suning_uos_patched
Allwinner Clock Changes for 5.7
Changes consist mainly of cleanups for the display engine clock driver, correcting clocks that don't exist. Also, the MBUS clock on the A64 is exported for the device tree to consume. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAl5rBewOHHdlbnNAY3Np ZS5vcmcACgkQOJpUIZwPJDA8MBAAqb/5ZoKoHpQVtRxU7MyUjOs5yLZ4UP3nJ8kw fEDl4YipPrQslYRvoSndPqXTEP48hlxBsdipYNiydxpRwuVtGb2cnqIphZNDb0jQ QLxhMi7QF0UbzZSHWZxYS6CxZavHz1RdALKQfpUbtTMy+LcbHxxsrxPiiFo+JNvv WeaMrq2aJZ97BG5rCGZtOmP0VFjqnz0V5AcHwFeChi4f8uve5vbogSYM2+4cOB2K BKVCV9uQd39J2bcuUkQdvZqQpRiJ/npr88RbOnoGIaiNQDHDQLRakMRUx0vkBP77 aTDkYqXAIyodmCFSyBdIaElrZV3p2jXI54VtRBUG/w/NIB8W18zqIzgFMHOs10H0 VY8txlEgslZJ1/gJThSdLO+zRldrSDrsOj+r6CYjwb52ESC16dwaWwZx8pWwfrU7 4K8Mkh0Odsq0e8GAAE9DUrKy3f3yY6/mEIT2tpTORHytxlR+0vvRdqVJxbOQBgvb GCqn/DPszoT11+zjKoEPm69qzDAZMwro+KnMtVw3QVPwbPnmxkgRWk2Q8OkZ327s 6GcljaPdYYMqYdyIyAqBxgk5WIQJ+NkWOlUDfJGIdD6UXSmpJlR2y574kSdJC+ZE Yd3sxgcY90fbzqx3Yo3ciypoEmbxF96jJ/vxI70HHgRrU5tfIN155APHJtbKA1kP vem/GDc= =mI1n -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Chen-Yu Tsai: Changes consist mainly of cleanups for the display engine clock driver, correcting clocks that don't exist. Also, the MBUS clock on the A64 is exported for the device tree to consume. * tag 'sunxi-clk-for-5.7' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock
This commit is contained in:
Stephen Boyd
commit
8ca1f3c06f
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@ -55,10 +55,6 @@
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_MBUS 112
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/* And the DSI and GPU module clock is exported */
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#define CLK_NUMBER (CLK_GPU + 1)
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@ -50,24 +50,8 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
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CLK_SET_RATE_PARENT);
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static struct ccu_common *sun50i_h6_de3_clks[] = {
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&mixer0_clk.common,
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&mixer1_clk.common,
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&wb_clk.common,
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&bus_mixer0_clk.common,
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&bus_mixer1_clk.common,
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&bus_wb_clk.common,
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&mixer0_div_clk.common,
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&mixer1_div_clk.common,
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&wb_div_clk.common,
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&bus_rot_clk.common,
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&rot_clk.common,
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&rot_div_clk.common,
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};
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static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
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CLK_SET_RATE_PARENT);
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static struct ccu_common *sun8i_a83t_de2_clks[] = {
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&mixer0_clk.common,
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@ -81,6 +65,10 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
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&mixer0_div_a83_clk.common,
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&mixer1_div_a83_clk.common,
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&wb_div_a83_clk.common,
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&bus_rot_clk.common,
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&rot_clk.common,
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&rot_div_a83_clk.common,
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};
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static struct ccu_common *sun8i_h3_de2_clks[] = {
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@ -108,21 +96,42 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {
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&wb_div_clk.common,
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};
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static struct ccu_common *sun50i_a64_de2_clks[] = {
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&mixer0_clk.common,
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&mixer1_clk.common,
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&wb_clk.common,
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&bus_mixer0_clk.common,
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&bus_mixer1_clk.common,
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&bus_wb_clk.common,
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&mixer0_div_clk.common,
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&mixer1_div_clk.common,
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&wb_div_clk.common,
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&bus_rot_clk.common,
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&rot_clk.common,
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&rot_div_clk.common,
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};
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static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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[CLK_MIXER1] = &mixer1_clk.common.hw,
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[CLK_WB] = &wb_clk.common.hw,
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[CLK_ROT] = &rot_clk.common.hw,
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[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
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[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
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[CLK_BUS_WB] = &bus_wb_clk.common.hw,
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[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
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[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
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[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
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[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
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[CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
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},
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.num = CLK_NUMBER_WITHOUT_ROT,
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.num = CLK_NUMBER_WITH_ROT,
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};
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static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
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@ -156,7 +165,7 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
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.num = CLK_NUMBER_WITHOUT_ROT,
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};
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static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
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static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
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.hws = {
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[CLK_MIXER0] = &mixer0_clk.common.hw,
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[CLK_MIXER1] = &mixer1_clk.common.hw,
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@ -179,9 +188,19 @@ static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
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static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
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[RST_MIXER0] = { 0x08, BIT(0) },
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/*
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* For A83T, H3 and R40, mixer1 reset line is shared with wb, so
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* only RST_WB is exported here.
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* For V3s there's just no mixer1, so it also shares this struct.
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* Mixer1 reset line is shared with wb, so only RST_WB is
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* exported here.
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*/
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[RST_WB] = { 0x08, BIT(2) },
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[RST_ROT] = { 0x08, BIT(3) },
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};
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static struct ccu_reset_map sun8i_h3_de2_resets[] = {
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[RST_MIXER0] = { 0x08, BIT(0) },
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/*
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* Mixer1 reset line is shared with wb, so only RST_WB is
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* exported here.
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* V3s doesn't have mixer1, so it also shares this struct.
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*/
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[RST_WB] = { 0x08, BIT(2) },
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};
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@ -190,13 +209,13 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
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[RST_MIXER0] = { 0x08, BIT(0) },
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[RST_MIXER1] = { 0x08, BIT(1) },
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[RST_WB] = { 0x08, BIT(2) },
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[RST_ROT] = { 0x08, BIT(3) },
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};
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static struct ccu_reset_map sun50i_h6_de3_resets[] = {
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static struct ccu_reset_map sun50i_h5_de2_resets[] = {
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[RST_MIXER0] = { 0x08, BIT(0) },
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[RST_MIXER1] = { 0x08, BIT(1) },
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[RST_WB] = { 0x08, BIT(2) },
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[RST_ROT] = { 0x08, BIT(3) },
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};
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static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
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@ -215,30 +234,20 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun8i_h3_de2_resets,
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.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
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};
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static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
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.ccu_clks = sun50i_a64_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
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.hw_clks = &sun50i_a64_de2_hw_clks,
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.resets = sun8i_a83t_de2_resets,
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
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.ccu_clks = sun8i_h3_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun50i_a64_de2_resets,
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.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
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.ccu_clks = sun50i_h6_de3_clks,
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.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
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.hw_clks = &sun50i_h6_de3_hw_clks,
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.resets = sun50i_h6_de3_resets,
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.num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
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};
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static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
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.ccu_clks = sun8i_v3s_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
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@ -249,6 +258,26 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
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.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
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.ccu_clks = sun50i_a64_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
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.hw_clks = &sun50i_a64_de2_hw_clks,
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.resets = sun50i_a64_de2_resets,
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.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
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};
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static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
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.ccu_clks = sun8i_h3_de2_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
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.hw_clks = &sun8i_h3_de2_hw_clks,
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.resets = sun50i_h5_de2_resets,
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.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
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};
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static int sunxi_de2_clk_probe(struct platform_device *pdev)
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{
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struct resource *res;
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@ -337,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
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.compatible = "allwinner,sun8i-h3-de2-clk",
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.data = &sun8i_h3_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun8i-r40-de2-clk",
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.data = &sun8i_r40_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun8i-v3s-de2-clk",
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.data = &sun8i_v3s_de2_clk_desc,
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@ -347,11 +380,11 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
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},
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{
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.compatible = "allwinner,sun50i-h5-de2-clk",
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.data = &sun50i_a64_de2_clk_desc,
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.data = &sun50i_h5_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun50i-h6-de3-clk",
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.data = &sun50i_h6_de3_clk_desc,
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.data = &sun50i_h5_de2_clk_desc,
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},
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{ }
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};
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@ -131,7 +131,7 @@
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#define CLK_AVS 109
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#define CLK_HDMI 110
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#define CLK_HDMI_DDC 111
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#define CLK_MBUS 112
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#define CLK_DSI_DPHY 113
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#define CLK_GPU 114
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