forked from luck/tmp_suning_uos_patched
dt-bindings: phy: qcom,qusb2: Convert QUSB2 phy bindings to yaml
Convert QUSB2 phy bindings to DT schema format using json-schema. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Sandeep Maheswaram
Kishon Vijay Abraham I
parent
b263bfa5a7
commit
8ce65d8d38
149
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
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149
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm QUSB2 phy controller
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maintainers:
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- Manu Gautam <mgautam@codeaurora.org>
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description:
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QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
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properties:
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compatible:
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enum:
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- qcom,msm8996-qusb2-phy
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- qcom,msm8998-qusb2-phy
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- qcom,sdm845-qusb2-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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clocks:
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minItems: 2
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maxItems: 3
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items:
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- description: phy config clock
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- description: 19.2 MHz ref clk
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- description: phy interface clock (Optional)
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clock-names:
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minItems: 2
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maxItems: 3
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items:
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- const: cfg_ahb
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- const: ref
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- const: iface
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vdda-pll-supply:
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description:
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Phandle to 1.8V regulator supply to PHY refclk pll block.
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vdda-phy-dpdm-supply:
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description:
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Phandle to 3.1V regulator supply to Dp/Dm port signals.
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resets:
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maxItems: 1
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description:
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Phandle to reset to phy block.
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nvmem-cells:
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maxItems: 1
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description:
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Phandle to nvmem cell that contains 'HS Tx trim'
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tuning parameter value for qusb2 phy.
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qcom,tcsr-syscon:
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description:
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Phandle to TCSR syscon register region.
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$ref: /schemas/types.yaml#/definitions/phandle
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if:
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properties:
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compatible:
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contains:
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const: qcom,sdm845-qusb2-phy
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then:
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properties:
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qcom,imp-res-offset-value:
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description:
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It is a 6 bit value that specifies offset to be
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added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
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tuning parameter that may vary for different boards of same SOC.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 0
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maximum: 63
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default: 0
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qcom,hstx-trim-value:
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description:
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It is a 4 bit value that specifies tuning for HSTX
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output current.
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Possible range is - 15mA to 24mA (stepsize of 600 uA).
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 0
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maximum: 15
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default: 3
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qcom,preemphasis-level:
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description:
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It is a 2 bit value that specifies pre-emphasis level.
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Possible range is 0 to 15% (stepsize of 5%).
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 0
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maximum: 3
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default: 2
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qcom,preemphasis-width:
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description:
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It is a 1 bit value that specifies how long the HSTX
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pre-emphasis (specified using qcom,preemphasis-level) must be in
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effect. Duration could be half-bit of full-bit.
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 0
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maximum: 1
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default: 0
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- vdda-pll-supply
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- vdda-phy-dpdm-supply
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- resets
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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hsusb_phy: phy@7411000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7411000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_RX1_USB2_CLKREF_CLK>;
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clock-names = "cfg_ahb", "ref";
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vdda-pll-supply = <&pm8994_l12>;
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vdda-phy-dpdm-supply = <&pm8994_l24>;
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2p_hstx_trim>;
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};
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@ -1,68 +0,0 @@
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Qualcomm QUSB2 phy controller
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=============================
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QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
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Required properties:
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- compatible: compatible list, contains
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"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
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"qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
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"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
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- reg: offset and length of the PHY register set.
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- #phy-cells: must be 0.
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: must be "cfg_ahb" for phy config clock,
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"ref" for 19.2 MHz ref clk,
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"iface" for phy interface clock (Optional).
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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- vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
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- resets: Phandle to reset to phy block.
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Optional properties:
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- nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
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tuning parameter value for qusb2 phy.
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- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
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- qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be
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added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
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tuning parameter that may vary for different boards of same SOC.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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- qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX
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output current.
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Possible range is - 15mA to 24mA (stepsize of 600 uA).
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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Default value is 22.2mA for sdm845.
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- qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level.
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Possible range is 0 to 15% (stepsize of 5%).
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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Default value is 10% for sdm845.
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- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX
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pre-emphasis (specified using qcom,preemphasis-level) must be in
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effect. Duration could be half-bit of full-bit.
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See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
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This property is applicable to only QUSB2 v2 PHY (sdm845).
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Default value is full-bit width for sdm845.
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Example:
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hsusb_phy: phy@7411000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7411000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_RX1_USB2_CLKREF_CLK>,
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clock-names = "cfg_ahb", "ref";
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vdda-pll-supply = <&pm8994_l12>;
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vdda-phy-dpdm-supply = <&pm8994_l24>;
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2p_hstx_trim>;
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};
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