forked from luck/tmp_suning_uos_patched
ASoC: uniphier: add support for multichannel output
This patch adds multichannel PCM output support for LD11/LD20. Currently driver tested and supported only 2ch, 6ch, and 8ch. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -264,6 +264,57 @@ void aio_port_reset(struct uniphier_aio_sub *sub)
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}
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}
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/**
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* aio_port_set_ch - set channels of LPCM
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* @sub: the AIO substream pointer, PCM substream only
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* @ch : count of channels
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*
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* Set suitable slot selecting to input/output port block of AIO.
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*
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* This function may return error if non-PCM substream.
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*
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* Return: Zero if successful, otherwise a negative value on error.
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*/
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static int aio_port_set_ch(struct uniphier_aio_sub *sub)
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{
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struct regmap *r = sub->aio->chip->regmap;
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u32 slotsel_2ch[] = {
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0, 0, 0, 0, 0,
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};
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u32 slotsel_multi[] = {
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OPORTMXTYSLOTCTR_SLOTSEL_SLOT0,
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OPORTMXTYSLOTCTR_SLOTSEL_SLOT1,
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OPORTMXTYSLOTCTR_SLOTSEL_SLOT2,
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OPORTMXTYSLOTCTR_SLOTSEL_SLOT3,
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OPORTMXTYSLOTCTR_SLOTSEL_SLOT4,
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};
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u32 mode, *slotsel;
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int i;
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switch (params_channels(&sub->params)) {
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case 8:
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case 6:
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mode = OPORTMXTYSLOTCTR_MODE;
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slotsel = slotsel_multi;
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break;
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case 2:
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mode = 0;
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slotsel = slotsel_2ch;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < AUD_MAX_SLOTSEL; i++) {
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regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i),
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OPORTMXTYSLOTCTR_MODE, mode);
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regmap_update_bits(r, OPORTMXTYSLOTCTR(sub->swm->oport.map, i),
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OPORTMXTYSLOTCTR_SLOTSEL_MASK, slotsel[i]);
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}
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return 0;
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}
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/**
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* aio_port_set_rate - set sampling rate of LPCM
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* @sub: the AIO substream pointer, PCM substream only
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@ -575,6 +626,10 @@ int aio_port_set_param(struct uniphier_aio_sub *sub, int pass_through,
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rate = params_rate(params);
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}
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ret = aio_port_set_ch(sub);
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if (ret)
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return ret;
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ret = aio_port_set_rate(sub, rate);
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if (ret)
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return ret;
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@ -731,15 +786,28 @@ void aio_port_set_volume(struct uniphier_aio_sub *sub, int vol)
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int aio_if_set_param(struct uniphier_aio_sub *sub, int pass_through)
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{
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struct regmap *r = sub->aio->chip->regmap;
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u32 v;
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u32 memfmt, v;
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if (sub->swm->dir == PORT_DIR_OUTPUT) {
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if (pass_through)
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if (pass_through) {
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v = PBOUTMXCTR0_ENDIAN_0123 |
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PBOUTMXCTR0_MEMFMT_STREAM;
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else
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v = PBOUTMXCTR0_ENDIAN_3210 |
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PBOUTMXCTR0_MEMFMT_2CH;
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} else {
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switch (params_channels(&sub->params)) {
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case 2:
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memfmt = PBOUTMXCTR0_MEMFMT_2CH;
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break;
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case 6:
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memfmt = PBOUTMXCTR0_MEMFMT_6CH;
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break;
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case 8:
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memfmt = PBOUTMXCTR0_MEMFMT_8CH;
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break;
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default:
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return -EINVAL;
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}
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v = PBOUTMXCTR0_ENDIAN_3210 | memfmt;
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}
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regmap_write(r, PBOUTMXCTR0(sub->swm->oif.map), v);
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regmap_write(r, PBOUTMXCTR1(sub->swm->oif.map), 0);
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@ -286,7 +286,7 @@ static struct snd_soc_dai_driver uniphier_aio_dai_ld11[] = {
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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.rates = SNDRV_PCM_RATE_48000,
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.channels_min = 2,
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.channels_max = 2,
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.channels_max = 8,
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},
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.ops = &uniphier_aio_i2s_ops,
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},
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@ -374,6 +374,7 @@
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#define OPORTMXTYVOLGAINSTATUS(n, m) (0x42108 + 0x400 * (n) + 0x20 * (m))
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#define OPORTMXTYVOLGAINSTATUS_CUR_MASK GENMASK(15, 0)
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#define OPORTMXTYSLOTCTR(n, m) (0x42114 + 0x400 * (n) + 0x20 * (m))
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#define OPORTMXTYSLOTCTR_MODE BIT(15)
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#define OPORTMXTYSLOTCTR_SLOTSEL_MASK GENMASK(11, 8)
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#define OPORTMXTYSLOTCTR_SLOTSEL_SLOT0 (0x8 << 8)
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#define OPORTMXTYSLOTCTR_SLOTSEL_SLOT1 (0x9 << 8)
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@ -141,6 +141,9 @@ enum IEC61937_PC {
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#define AUD_MIN_FRAGMENT_SIZE (4 * 1024)
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#define AUD_MAX_FRAGMENT_SIZE (16 * 1024)
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/* max 5 slots, 10 channels, 2 channel in 1 slot */
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#define AUD_MAX_SLOTSEL 5
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/*
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* This is a selector for virtual register map of AIO.
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*
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