forked from luck/tmp_suning_uos_patched
x86: mtrr: Fix high_width computation when phys-addr is >= 44bit
found one system where cpu address line is 44bits, mtrr printout is not right: [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 0 00000000 mask FF0 00000000 write-back [ 0.000000] 1 base 10 00000000 mask FFF 80000000 write-back [ 0.000000] 2 base 0 80000000 mask FFF 80000000 uncachable [ 0.000000] 3 base 0 7F800000 mask FFF FF800000 uncachable Li Zefan and Frederic pointed out the high_width could be -4 some how. It turns out when phys_addr is 44bit, size_or_mask will be ffffffff,00000000 so ffs(size_or_mask) will be 0. Try to check low 32 bit, to get correct high_width. Signed-off-by: Yinghai Lu <yinghai@kerne.org> Also-analyzed-by: Frederic Weisbecker <fweisbec@gmail.com> Also-analyzed-by: Li Zefan <lizf@cn.fujitsu.com> Cc: Jeremy Fitzhardinge <jeremy@goop.org> Cc: Zhaolei <zhaolei@cn.fujitsu.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Vegard Nossum <vegard.nossum@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> LKML-Reference: <4A026540.8060504@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -275,7 +275,11 @@ static void __init print_mtrr_state(void)
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}
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printk(KERN_DEBUG "MTRR variable ranges %sabled:\n",
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mtrr_state.enabled & 2 ? "en" : "dis");
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high_width = ((size_or_mask ? ffs(size_or_mask) - 1 : 32) - (32 - PAGE_SHIFT) + 3) / 4;
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if (size_or_mask & 0xffffffffUL)
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high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
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else
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high_width = ffs(size_or_mask>>32) + 32 - 1;
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high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
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for (i = 0; i < num_var_ranges; ++i) {
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if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
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printk(KERN_DEBUG " %u base %0*X%05X000 mask %0*X%05X000 %s\n",
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