forked from luck/tmp_suning_uos_patched
[PATCH] ppc iomem annotations: ->io_base_virt
* ->io_base_virt in struct pci_controller is iomem pointer. Marked as such. Most of the places that used it are already annotated to expect iomem. * places that did gratitious (and wrong) casts a-la isa_io_base = (unsigned long)ioremap(...); hose->io_base_virt = (void *)isa_io_base; turned into hose->io_base_virt = ioremap(...); isa_io_base = (unsigned long)hose->io_base_virt; * pci_bus_io_base() annotated as returning iomem pointer. Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -1432,7 +1432,7 @@ pci_bus_to_hose(int bus)
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return NULL;
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}
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void*
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void __iomem *
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pci_bus_io_base(unsigned int bus)
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{
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struct pci_controller *hose;
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@ -210,9 +210,8 @@ ebony_setup_hose(void)
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hose->io_space.end = EBONY_PCI_UPPER_IO;
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hose->mem_space.start = EBONY_PCI_LOWER_MEM;
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hose->mem_space.end = EBONY_PCI_UPPER_MEM;
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isa_io_base =
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(unsigned long)ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
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hose->io_base_virt = (void *)isa_io_base;
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hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
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isa_io_base = (unsigned long)hose->io_base_virt;
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setup_indirect_pci(hose,
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EBONY_PCI_CFGA_PLB32,
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@ -223,9 +223,8 @@ luan_setup_hose(struct pci_controller *hose,
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hose->io_space.end = LUAN_PCIX_UPPER_IO;
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hose->mem_space.start = lower_mem;
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hose->mem_space.end = upper_mem;
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isa_io_base =
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(unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
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hose->io_base_virt = (void *)isa_io_base;
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hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
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isa_io_base = (unsigned long) hose->io_base_virt;
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setup_indirect_pci(hose, cfga, cfgd);
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hose->set_cfg_type = 1;
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@ -227,9 +227,8 @@ ocotea_setup_hose(void)
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hose->io_space.end = OCOTEA_PCI_UPPER_IO;
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hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
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hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
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isa_io_base =
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(unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
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hose->io_base_virt = (void *)isa_io_base;
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hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
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isa_io_base = (unsigned long) hose->io_base_virt;
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setup_indirect_pci(hose,
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OCOTEA_PCI_CFGA_PLB32,
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@ -171,10 +171,9 @@ void __init m8260_find_bridges(void)
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m8260_setup_pci(hose);
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hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
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isa_io_base =
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(unsigned long) ioremap(MPC826x_PCI_IO_BASE,
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hose->io_base_virt = ioremap(MPC826x_PCI_IO_BASE,
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MPC826x_PCI_IO_SIZE);
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hose->io_base_virt = (void *) isa_io_base;
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isa_io_base = (unsigned long) hose->io_base_virt;
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/* setup resources */
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pci_init_resource(&hose->mem_resources[0],
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@ -205,13 +205,11 @@ mpc52xx_find_bridges(void)
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hose->pci_mem_offset = MPC52xx_PCI_MEM_OFFSET;
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isa_io_base =
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(unsigned long) ioremap(MPC52xx_PCI_IO_BASE,
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MPC52xx_PCI_IO_SIZE);
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hose->io_base_virt = (void *) isa_io_base;
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hose->io_base_virt = ioremap(MPC52xx_PCI_IO_BASE, MPC52xx_PCI_IO_SIZE);
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isa_io_base = (unsigned long) hose->io_base_virt;
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hose->cfg_addr = &pci_regs->car;
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hose->cfg_data = (void __iomem *) isa_io_base;
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hose->cfg_data = hose->io_base_virt;
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/* Setup resources */
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pci_init_resource(&hose->mem_resources[0],
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@ -280,16 +280,14 @@ mpc85xx_setup_hose(void)
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hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
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hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
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#ifdef CONFIG_85xx_PCI2
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isa_io_base =
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(unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
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hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
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MPC85XX_PCI1_IO_SIZE +
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MPC85XX_PCI2_IO_SIZE);
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#else
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isa_io_base =
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(unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
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hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE,
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MPC85XX_PCI1_IO_SIZE);
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#endif
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hose_a->io_base_virt = (void *) isa_io_base;
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isa_io_base = (unsigned long)hose_a->io_base_virt;
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/* setup resources */
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pci_init_resource(&hose_a->mem_resources[0],
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@ -329,8 +327,8 @@ mpc85xx_setup_hose(void)
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hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
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hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
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hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
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hose_b->io_base_virt = (void *) isa_io_base + MPC85XX_PCI1_IO_SIZE;
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hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE;
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/* setup resources */
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pci_init_resource(&hose_b->mem_resources[0],
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MPC85XX_PCI2_LOWER_MEM,
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@ -12,7 +12,7 @@ struct pci_controller;
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* pci_io_base returns the memory address at which you can access
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* the I/O space for PCI bus number `bus' (or NULL on error).
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*/
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extern void *pci_bus_io_base(unsigned int bus);
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extern void __iomem *pci_bus_io_base(unsigned int bus);
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extern unsigned long pci_bus_io_base_phys(unsigned int bus);
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extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
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@ -48,7 +48,7 @@ struct pci_controller {
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int last_busno;
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int bus_offset;
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void *io_base_virt;
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void __iomem *io_base_virt;
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unsigned long io_base_phys;
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/* Some machines (PReP) have a non 1:1 mapping of
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