forked from luck/tmp_suning_uos_patched
[POWERPC] irqtrace support for 64-bit powerpc
This adds the low level irq tracing hooks to the powerpc architecture needed to enable full lockdep functionality. This is partly based on Johannes Berg's initial version. I removed the asm trampoline that isn't needed (thus improving performance) and modified all sorts of bits and pieces, reworking most of the assembly, etc... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
fd3e0bbc60
commit
945feb174b
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@ -53,6 +53,15 @@ config STACKTRACE_SUPPORT
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bool
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default y
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config TRACE_IRQFLAGS_SUPPORT
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bool
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depends on PPC64
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default y
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config LOCKDEP_SUPPORT
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bool
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default y
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config RWSEM_GENERIC_SPINLOCK
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bool
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@ -30,6 +30,7 @@
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#include <asm/firmware.h>
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#include <asm/bug.h>
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#include <asm/ptrace.h>
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#include <asm/irqflags.h>
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/*
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* System calls.
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@ -89,6 +90,14 @@ system_call_common:
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addi r9,r1,STACK_FRAME_OVERHEAD
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ld r11,exception_marker@toc(r2)
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std r11,-16(r9) /* "regshere" marker */
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl .trace_hardirqs_on
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REST_GPR(0,r1)
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REST_4GPRS(3,r1)
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REST_2GPRS(7,r1)
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addi r9,r1,STACK_FRAME_OVERHEAD
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ld r12,_MSR(r1)
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#endif /* CONFIG_TRACE_IRQFLAGS */
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li r10,1
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stb r10,PACASOFTIRQEN(r13)
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stb r10,PACAHARDIRQEN(r13)
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@ -103,7 +112,7 @@ BEGIN_FW_FTR_SECTION
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b hardware_interrupt_entry
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2:
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif
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#endif /* CONFIG_PPC_ISERIES */
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mfmsr r11
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ori r11,r11,MSR_EE
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mtmsrd r11,1
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@ -505,6 +514,10 @@ BEGIN_FW_FTR_SECTION
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li r3,0
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stb r3,PACASOFTIRQEN(r13) /* ensure we are soft-disabled */
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl .trace_hardirqs_off
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mfmsr r10
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#endif
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ori r10,r10,MSR_EE
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mtmsrd r10 /* hard-enable again */
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addi r3,r1,STACK_FRAME_OVERHEAD
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@ -513,7 +526,7 @@ BEGIN_FW_FTR_SECTION
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4:
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif
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stb r5,PACASOFTIRQEN(r13)
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TRACE_AND_RESTORE_IRQ(r5);
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/* extract EE bit and use it to restore paca->hard_enabled */
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ld r3,_MSR(r1)
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@ -581,6 +594,16 @@ do_work:
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bne restore
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/* here we are preempting the current task */
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1:
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl .trace_hardirqs_on
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/* Note: we just clobbered r10 which used to contain the previous
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* MSR before the hard-disabling done by the caller of do_work.
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* We don't have that value anymore, but it doesn't matter as
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* we will hard-enable unconditionally, we can just reload the
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* current MSR into r10
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*/
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mfmsr r10
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#endif /* CONFIG_TRACE_IRQFLAGS */
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li r0,1
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stb r0,PACASOFTIRQEN(r13)
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stb r0,PACAHARDIRQEN(r13)
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@ -36,8 +36,7 @@
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#include <asm/firmware.h>
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#include <asm/page_64.h>
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#include <asm/exception.h>
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#define DO_SOFT_DISABLE
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#include <asm/irqflags.h>
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/*
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* We layout physical memory as follows:
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@ -450,8 +449,8 @@ bad_stack:
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*/
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fast_exc_return_irq: /* restores irq state too */
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ld r3,SOFTE(r1)
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TRACE_AND_RESTORE_IRQ(r3);
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ld r12,_MSR(r1)
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stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
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rldicl r4,r12,49,63 /* get MSR_EE to LSB */
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stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
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b 1f
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@ -824,7 +823,7 @@ _STATIC(load_up_altivec)
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* Hash table stuff
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*/
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.align 7
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_GLOBAL(do_hash_page)
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_STATIC(do_hash_page)
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std r3,_DAR(r1)
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std r4,_DSISR(r1)
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@ -835,6 +834,27 @@ BEGIN_FTR_SECTION
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bne- do_ste_alloc /* If so handle it */
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END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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/*
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* On iSeries, we soft-disable interrupts here, then
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* hard-enable interrupts so that the hash_page code can spin on
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* the hash_table_lock without problems on a shared processor.
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*/
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DISABLE_INTS
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/*
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* Currently, trace_hardirqs_off() will be called by DISABLE_INTS
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* and will clobber volatile registers when irq tracing is enabled
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* so we need to reload them. It may be possible to be smarter here
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* and move the irq tracing elsewhere but let's keep it simple for
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* now
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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ld r3,_DAR(r1)
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ld r4,_DSISR(r1)
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ld r5,_TRAP(r1)
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ld r12,_MSR(r1)
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clrrdi r5,r5,4
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#endif /* CONFIG_TRACE_IRQFLAGS */
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/*
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* We need to set the _PAGE_USER bit if MSR_PR is set or if we are
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* accessing a userspace segment (even from the kernel). We assume
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@ -847,13 +867,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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ori r4,r4,1 /* add _PAGE_PRESENT */
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rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
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/*
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* On iSeries, we soft-disable interrupts here, then
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* hard-enable interrupts so that the hash_page code can spin on
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* the hash_table_lock without problems on a shared processor.
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*/
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DISABLE_INTS
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/*
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* r3 contains the faulting address
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* r4 contains the required access permissions
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@ -864,7 +877,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
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bl .hash_page /* build HPTE if possible */
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cmpdi r3,0 /* see if hash_page succeeded */
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#ifdef DO_SOFT_DISABLE
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BEGIN_FW_FTR_SECTION
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/*
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* If we had interrupts soft-enabled at the point where the
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@ -876,7 +888,7 @@ BEGIN_FW_FTR_SECTION
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*/
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beq 13f
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#endif
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BEGIN_FW_FTR_SECTION
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/*
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* Here we have interrupts hard-disabled, so it is sufficient
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@ -890,11 +902,12 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
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/*
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* hash_page couldn't handle it, set soft interrupt enable back
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* to what it was before the trap. Note that .local_irq_restore
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* to what it was before the trap. Note that .raw_local_irq_restore
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* handles any interrupts pending at this point.
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*/
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ld r3,SOFTE(r1)
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bl .local_irq_restore
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TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
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bl .raw_local_irq_restore
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b 11f
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/* Here we have a page fault that hash_page can't handle. */
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@ -1493,6 +1506,10 @@ _INIT_STATIC(start_here_multiplatform)
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addi r2,r2,0x4000
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add r2,r2,r26
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/* Set initial ptr to current */
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LOAD_REG_IMMEDIATE(r4, init_task)
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std r4,PACACURRENT(r13)
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/* Do very early kernel initializations, including initial hash table,
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* stab and slb setup before we turn on relocation. */
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@ -114,7 +114,7 @@ static inline void set_soft_enabled(unsigned long enable)
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: : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
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}
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void local_irq_restore(unsigned long en)
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void raw_local_irq_restore(unsigned long en)
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{
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/*
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* get_paca()->soft_enabled = en;
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@ -174,6 +174,7 @@ void local_irq_restore(unsigned long en)
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__hard_irq_enable();
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}
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EXPORT_SYMBOL(raw_local_irq_restore);
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#endif /* CONFIG_PPC64 */
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int show_interrupts(struct seq_file *p, void *v)
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@ -45,10 +45,6 @@
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#include <asm/signal.h>
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#include <asm/dcr.h>
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#ifdef CONFIG_PPC64
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EXPORT_SYMBOL(local_irq_restore);
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#endif
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#ifdef CONFIG_PPC32
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extern void transfer_to_handler(void);
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extern void do_IRQ(struct pt_regs *regs);
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@ -33,6 +33,7 @@
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#include <linux/serial_8250.h>
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#include <linux/bootmem.h>
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#include <linux/pci.h>
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#include <linux/lockdep.h>
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#include <linux/lmb.h>
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#include <asm/io.h>
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#include <asm/kdump.h>
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@ -178,6 +179,9 @@ void __init early_setup(unsigned long dt_ptr)
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/* Enable early debugging if any specified (see udbg.h) */
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udbg_early_init();
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/* Initialize lockdep early or else spinlocks will blow */
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lockdep_init();
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DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
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/*
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@ -228,18 +228,18 @@ label##_pSeries: \
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BEGIN_FW_FTR_SECTION; \
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stb r11,PACAHARDIRQEN(r13); \
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END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
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TRACE_DISABLE_INTS; \
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BEGIN_FW_FTR_SECTION; \
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mfmsr r10; \
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ori r10,r10,MSR_EE; \
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mtmsrd r10,1; \
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END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
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#else
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#define DISABLE_INTS \
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li r11,0; \
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stb r11,PACASOFTIRQEN(r13); \
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stb r11,PACAHARDIRQEN(r13)
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stb r11,PACAHARDIRQEN(r13); \
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TRACE_DISABLE_INTS
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#endif /* CONFIG_PPC_ISERIES */
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#define ENABLE_INTS \
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@ -27,7 +27,7 @@ static inline unsigned long local_get_flags(void)
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return flags;
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}
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static inline unsigned long local_irq_disable(void)
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static inline unsigned long raw_local_irq_disable(void)
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{
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unsigned long flags, zero;
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@ -39,14 +39,15 @@ static inline unsigned long local_irq_disable(void)
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return flags;
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}
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extern void local_irq_restore(unsigned long);
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extern void raw_local_irq_restore(unsigned long);
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extern void iseries_handle_interrupts(void);
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#define local_irq_enable() local_irq_restore(1)
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#define local_save_flags(flags) ((flags) = local_get_flags())
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#define local_irq_save(flags) ((flags) = local_irq_disable())
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#define raw_local_irq_enable() raw_local_irq_restore(1)
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#define raw_local_save_flags(flags) ((flags) = local_get_flags())
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#define raw_local_irq_save(flags) ((flags) = raw_local_irq_disable())
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#define irqs_disabled() (local_get_flags() == 0)
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#define raw_irqs_disabled() (local_get_flags() == 0)
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#define raw_irqs_disabled_flags(flags) ((flags) == 0)
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#define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1)
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#define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1)
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@ -2,30 +2,43 @@
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* include/asm-powerpc/irqflags.h
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*
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* IRQ flags handling
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*
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* This file gets included from lowlevel asm headers too, to provide
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* wrapped versions of the local_irq_*() APIs, based on the
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* raw_local_irq_*() macros from the lowlevel headers.
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*/
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#ifndef _ASM_IRQFLAGS_H
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#define _ASM_IRQFLAGS_H
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#ifndef __ASSEMBLY__
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/*
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* Get definitions for raw_local_save_flags(x), etc.
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*/
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#include <asm-powerpc/hw_irq.h>
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/*
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* Do the CPU's IRQ-state tracing from assembly code. We call a
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* C function, so save all the C-clobbered registers:
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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#error No support on PowerPC yet for CONFIG_TRACE_IRQFLAGS
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#else
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# define TRACE_IRQS_ON
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# define TRACE_IRQS_OFF
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#ifdef CONFIG_TRACE_IRQFLAGS
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/*
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* Most of the CPU's IRQ-state tracing is done from assembly code; we
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* have to call a C function so call a wrapper that saves all the
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* C-clobbered registers.
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*/
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#define TRACE_ENABLE_INTS bl .trace_hardirqs_on
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#define TRACE_DISABLE_INTS bl .trace_hardirqs_off
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#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip) \
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cmpdi en, 0; \
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bne 95f; \
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stb en,PACASOFTIRQEN(r13); \
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bl .trace_hardirqs_off; \
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b skip; \
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95: bl .trace_hardirqs_on; \
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li en,1;
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#define TRACE_AND_RESTORE_IRQ(en) \
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TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f); \
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96: stb en,PACASOFTIRQEN(r13)
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#else
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#define TRACE_ENABLE_INTS
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#define TRACE_DISABLE_INTS
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#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
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#define TRACE_AND_RESTORE_IRQ(en) \
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stb en,PACASOFTIRQEN(r13)
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#endif
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#endif
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#endif
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@ -32,11 +32,20 @@ struct rw_semaphore {
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#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
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spinlock_t wait_lock;
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struct list_head wait_list;
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#ifdef CONFIG_DEBUG_LOCK_ALLOC
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struct lockdep_map dep_map;
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#endif
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};
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#ifdef CONFIG_DEBUG_LOCK_ALLOC
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# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
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#else
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# define __RWSEM_DEP_MAP_INIT(lockname)
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#endif
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#define __RWSEM_INITIALIZER(name) \
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{ RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
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LIST_HEAD_INIT((name).wait_list) }
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{ RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
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LIST_HEAD_INIT((name).wait_list) __RWSEM_DEP_MAP_INIT(name) }
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#define DECLARE_RWSEM(name) \
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struct rw_semaphore name = __RWSEM_INITIALIZER(name)
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@ -46,12 +55,15 @@ extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
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extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
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extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
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static inline void init_rwsem(struct rw_semaphore *sem)
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{
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sem->count = RWSEM_UNLOCKED_VALUE;
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spin_lock_init(&sem->wait_lock);
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INIT_LIST_HEAD(&sem->wait_list);
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}
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extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
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struct lock_class_key *key);
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#define init_rwsem(sem) \
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do { \
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static struct lock_class_key __key; \
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\
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__init_rwsem((sem), #sem, &__key); \
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} while (0)
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/*
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* lock for reading
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@ -78,7 +90,7 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
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/*
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* lock for writing
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*/
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static inline void __down_write(struct rw_semaphore *sem)
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static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
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{
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int tmp;
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@ -88,6 +100,11 @@ static inline void __down_write(struct rw_semaphore *sem)
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rwsem_down_write_failed(sem);
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}
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static inline void __down_write(struct rw_semaphore *sem)
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{
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__down_write_nested(sem, 0);
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}
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||||
|
||||
static inline int __down_write_trylock(struct rw_semaphore *sem)
|
||||
{
|
||||
int tmp;
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
*
|
||||
* (the type definitions are in asm/spinlock_types.h)
|
||||
*/
|
||||
#include <linux/irqflags.h>
|
||||
#ifdef CONFIG_PPC64
|
||||
#include <asm/paca.h>
|
||||
#include <asm/hvcall.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user