forked from luck/tmp_suning_uos_patched
phy: stm32: add support for STM32 USB PHY Controller (USBPHYC)
This patch adds phy transceiver driver for STM32 USB PHY Controller (USBPHYC) that provides dual port High-Speed phy for OTG (single port) and EHCI/OHCI host controller (two ports). One port of the phy is shared between the two USB controllers through a UTMI+ switch. [fengguang.wu@intel.com: Make stm32_usbphyc_get_pll_params() to be static] Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Amelie Delaunay
Kishon Vijay Abraham I
parent
194303d60b
commit
94c358da3a
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@ -31,3 +31,17 @@ config PHY_STIH407_USB
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help
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Enable this support to enable the picoPHY device used by USB2
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and USB3 controllers on STMicroelectronics STiH407 SoC families.
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config PHY_STM32_USBPHYC
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tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
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depends on ARCH_STM32 || COMPILE_TEST
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select GENERIC_PHY
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help
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Enable this to support the High-Speed USB transceivers that are part
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of some STMicroelectronics STM32 SoCs.
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This driver controls the entire USB PHY block: the USB PHY controller
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(USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
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used by an HS USB Host controller, and the second one is shared
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between an HS USB OTG controller and an HS USB Host controller,
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selected by a USB switch.
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@ -2,3 +2,4 @@ obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
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obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
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obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
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obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
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obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
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461
drivers/phy/st/phy-stm32-usbphyc.c
Normal file
461
drivers/phy/st/phy-stm32-usbphyc.c
Normal file
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@ -0,0 +1,461 @@
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// SPDX-Licence-Identifier: GPL-2.0
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/*
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* STMicroelectronics STM32 USB PHY Controller driver
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*
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* Copyright (C) 2018 STMicroelectronics
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* Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/reset.h>
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#define STM32_USBPHYC_PLL 0x0
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#define STM32_USBPHYC_MISC 0x8
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#define STM32_USBPHYC_VERSION 0x3F4
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/* STM32_USBPHYC_PLL bit fields */
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#define PLLNDIV GENMASK(6, 0)
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#define PLLFRACIN GENMASK(25, 10)
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#define PLLEN BIT(26)
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#define PLLSTRB BIT(27)
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#define PLLSTRBYP BIT(28)
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#define PLLFRACCTL BIT(29)
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#define PLLDITHEN0 BIT(30)
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#define PLLDITHEN1 BIT(31)
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/* STM32_USBPHYC_MISC bit fields */
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#define SWITHOST BIT(0)
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/* STM32_USBPHYC_VERSION bit fields */
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#define MINREV GENMASK(3, 0)
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#define MAJREV GENMASK(7, 4)
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static const char * const supplies_names[] = {
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"vdda1v1", /* 1V1 */
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"vdda1v8", /* 1V8 */
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};
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#define NUM_SUPPLIES ARRAY_SIZE(supplies_names)
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#define PLL_LOCK_TIME_US 100
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#define PLL_PWR_DOWN_TIME_US 5
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#define PLL_FVCO_MHZ 2880
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#define PLL_INFF_MIN_RATE_HZ 19200000
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#define PLL_INFF_MAX_RATE_HZ 38400000
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#define HZ_PER_MHZ 1000000L
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struct pll_params {
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u8 ndiv;
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u16 frac;
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};
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struct stm32_usbphyc_phy {
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struct phy *phy;
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struct stm32_usbphyc *usbphyc;
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struct regulator_bulk_data supplies[NUM_SUPPLIES];
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u32 index;
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bool active;
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};
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struct stm32_usbphyc {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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struct reset_control *rst;
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struct stm32_usbphyc_phy **phys;
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int nphys;
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int switch_setup;
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bool pll_enabled;
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};
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static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
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{
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writel_relaxed(readl_relaxed(reg) | bits, reg);
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}
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static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
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{
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writel_relaxed(readl_relaxed(reg) & ~bits, reg);
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}
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static void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
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{
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unsigned long long fvco, ndiv, frac;
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/* _
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* | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
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* | FVCO = 2880MHz
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* <
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* | NDIV = integer part of input bits to set the LDF
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* |_FRACT = fractional part of input bits to set the LDF
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* => PLLNDIV = integer part of (FVCO / (INFF*2))
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* => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
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* <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
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*/
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fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
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ndiv = fvco;
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do_div(ndiv, (clk_rate * 2));
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pll_params->ndiv = (u8)ndiv;
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frac = fvco * (1 << 16);
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do_div(frac, (clk_rate * 2));
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frac = frac - (ndiv * (1 << 16));
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pll_params->frac = (u16)frac;
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}
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static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
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{
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struct pll_params pll_params;
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u32 clk_rate = clk_get_rate(usbphyc->clk);
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u32 ndiv, frac;
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u32 usbphyc_pll;
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if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
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(clk_rate > PLL_INFF_MAX_RATE_HZ)) {
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dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
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clk_rate);
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return -EINVAL;
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}
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stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
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ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
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frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
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usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
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if (pll_params.frac)
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usbphyc_pll |= PLLFRACCTL | frac;
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writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
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dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
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clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
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FIELD_GET(PLLFRACIN, usbphyc_pll));
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return 0;
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}
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static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
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{
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int i;
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for (i = 0; i < usbphyc->nphys; i++)
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if (usbphyc->phys[i]->active)
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return true;
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return false;
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}
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static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
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{
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void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
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bool pllen = (readl_relaxed(pll_reg) & PLLEN);
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int ret;
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/* Check if one phy port has already configured the pll */
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if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
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return 0;
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if (pllen) {
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stm32_usbphyc_clr_bits(pll_reg, PLLEN);
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/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
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udelay(PLL_PWR_DOWN_TIME_US);
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}
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ret = stm32_usbphyc_pll_init(usbphyc);
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if (ret)
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return ret;
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stm32_usbphyc_set_bits(pll_reg, PLLEN);
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/* Wait for maximum lock time */
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udelay(PLL_LOCK_TIME_US);
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if (!(readl_relaxed(pll_reg) & PLLEN)) {
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dev_err(usbphyc->dev, "PLLEN not set\n");
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return -EIO;
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}
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return 0;
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}
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static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
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{
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void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
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/* Check if other phy port active */
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if (stm32_usbphyc_has_one_phy_active(usbphyc))
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return 0;
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stm32_usbphyc_clr_bits(pll_reg, PLLEN);
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/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
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udelay(PLL_PWR_DOWN_TIME_US);
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if (readl_relaxed(pll_reg) & PLLEN) {
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dev_err(usbphyc->dev, "PLL not reset\n");
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return -EIO;
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}
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return 0;
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}
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static int stm32_usbphyc_phy_init(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
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int ret;
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ret = stm32_usbphyc_pll_enable(usbphyc);
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if (ret)
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return ret;
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usbphyc_phy->active = true;
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return 0;
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}
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static int stm32_usbphyc_phy_exit(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
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usbphyc_phy->active = false;
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return stm32_usbphyc_pll_disable(usbphyc);
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}
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static int stm32_usbphyc_phy_power_on(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
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}
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static int stm32_usbphyc_phy_power_off(struct phy *phy)
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{
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struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
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return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
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}
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static const struct phy_ops stm32_usbphyc_phy_ops = {
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.init = stm32_usbphyc_phy_init,
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.exit = stm32_usbphyc_phy_exit,
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.power_on = stm32_usbphyc_phy_power_on,
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.power_off = stm32_usbphyc_phy_power_off,
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.owner = THIS_MODULE,
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};
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static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
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u32 utmi_switch)
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{
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if (!utmi_switch)
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stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
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SWITHOST);
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else
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stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
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SWITHOST);
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usbphyc->switch_setup = utmi_switch;
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}
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static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
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struct stm32_usbphyc_phy *usbphyc_phy = NULL;
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struct device_node *phynode = args->np;
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int port = 0;
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for (port = 0; port < usbphyc->nphys; port++) {
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if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
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usbphyc_phy = usbphyc->phys[port];
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break;
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}
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}
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if (!usbphyc_phy) {
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dev_err(dev, "failed to find phy\n");
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return ERR_PTR(-EINVAL);
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}
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if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
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((usbphyc_phy->index == 1) && (args->args_count != 1))) {
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dev_err(dev, "invalid number of cells for phy port%d\n",
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usbphyc_phy->index);
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return ERR_PTR(-EINVAL);
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}
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/* Configure the UTMI switch for PHY port#2 */
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if (usbphyc_phy->index == 1) {
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if (usbphyc->switch_setup < 0) {
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stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
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} else {
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if (args->args[0] != usbphyc->switch_setup) {
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dev_err(dev, "phy port1 already used\n");
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return ERR_PTR(-EBUSY);
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}
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}
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}
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return usbphyc_phy->phy;
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}
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static int stm32_usbphyc_probe(struct platform_device *pdev)
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{
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struct stm32_usbphyc *usbphyc;
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struct device *dev = &pdev->dev;
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struct device_node *child, *np = dev->of_node;
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struct resource *res;
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struct phy_provider *phy_provider;
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u32 version;
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int ret, port = 0;
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usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
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if (!usbphyc)
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return -ENOMEM;
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usbphyc->dev = dev;
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dev_set_drvdata(dev, usbphyc);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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usbphyc->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(usbphyc->base))
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return PTR_ERR(usbphyc->base);
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usbphyc->clk = devm_clk_get(dev, 0);
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if (IS_ERR(usbphyc->clk)) {
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ret = PTR_ERR(usbphyc->clk);
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dev_err(dev, "clk get failed: %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(usbphyc->clk);
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if (ret) {
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dev_err(dev, "clk enable failed: %d\n", ret);
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return ret;
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}
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usbphyc->rst = devm_reset_control_get(dev, 0);
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if (!IS_ERR(usbphyc->rst)) {
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reset_control_assert(usbphyc->rst);
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udelay(2);
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reset_control_deassert(usbphyc->rst);
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}
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usbphyc->switch_setup = -EINVAL;
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usbphyc->nphys = of_get_child_count(np);
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usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
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sizeof(*usbphyc->phys), GFP_KERNEL);
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if (!usbphyc->phys) {
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ret = -ENOMEM;
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goto clk_disable;
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}
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for_each_child_of_node(np, child) {
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struct stm32_usbphyc_phy *usbphyc_phy;
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struct phy *phy;
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u32 index;
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int i;
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phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
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if (IS_ERR(phy)) {
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ret = PTR_ERR(phy);
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if (ret != -EPROBE_DEFER)
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dev_err(dev,
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"failed to create phy%d: %d\n", i, ret);
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goto put_child;
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}
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usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
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GFP_KERNEL);
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if (!usbphyc_phy) {
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ret = -ENOMEM;
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goto put_child;
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}
|
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for (i = 0; i < NUM_SUPPLIES; i++)
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usbphyc_phy->supplies[i].supply = supplies_names[i];
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ret = devm_regulator_bulk_get(&phy->dev, NUM_SUPPLIES,
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usbphyc_phy->supplies);
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if (ret) {
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if (ret != -EPROBE_DEFER)
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dev_err(&phy->dev,
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"failed to get regulators: %d\n", ret);
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goto put_child;
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}
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ret = of_property_read_u32(child, "reg", &index);
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if (ret || index > usbphyc->nphys) {
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dev_err(&phy->dev, "invalid reg property: %d\n", ret);
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goto put_child;
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}
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usbphyc->phys[port] = usbphyc_phy;
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phy_set_bus_width(phy, 8);
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phy_set_drvdata(phy, usbphyc_phy);
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usbphyc->phys[port]->phy = phy;
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usbphyc->phys[port]->usbphyc = usbphyc;
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usbphyc->phys[port]->index = index;
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usbphyc->phys[port]->active = false;
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port++;
|
||||
}
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev,
|
||||
stm32_usbphyc_of_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
ret = PTR_ERR(phy_provider);
|
||||
dev_err(dev, "failed to register phy provider: %d\n", ret);
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
|
||||
dev_info(dev, "registered rev:%lu.%lu\n",
|
||||
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
|
||||
|
||||
return 0;
|
||||
|
||||
put_child:
|
||||
of_node_put(child);
|
||||
clk_disable:
|
||||
clk_disable_unprepare(usbphyc->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_usbphyc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
clk_disable_unprepare(usbphyc->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id stm32_usbphyc_of_match[] = {
|
||||
{ .compatible = "st,stm32mp1-usbphyc", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
|
||||
|
||||
static struct platform_driver stm32_usbphyc_driver = {
|
||||
.probe = stm32_usbphyc_probe,
|
||||
.remove = stm32_usbphyc_remove,
|
||||
.driver = {
|
||||
.of_match_table = stm32_usbphyc_of_match,
|
||||
.name = "stm32-usbphyc",
|
||||
}
|
||||
};
|
||||
module_platform_driver(stm32_usbphyc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
|
||||
MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue
Block a user