forked from luck/tmp_suning_uos_patched
[PATCH] forcedeth config: diagnostics
This patch adds support for diagnostic tests through ethtool support. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ayaz Abdulla
Jeff Garzik
parent
7a1854b797
commit
9589c77a0d
@ -166,6 +166,7 @@
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#define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
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#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
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#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
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#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
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enum {
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NvRegIrqStatus = 0x000,
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@ -222,6 +223,7 @@ enum {
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#define NVREG_PFF_ALWAYS 0x7F0000
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#define NVREG_PFF_PROMISC 0x80
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#define NVREG_PFF_MYADDR 0x20
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#define NVREG_PFF_LOOPBACK 0x10
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NvRegOffloadConfig = 0x90,
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#define NVREG_OFFLOAD_HOMEPHY 0x601
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@ -634,6 +636,32 @@ struct nv_ethtool_stats {
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u64 rx_errors_total;
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};
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/* diagnostics */
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#define NV_TEST_COUNT_BASE 3
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#define NV_TEST_COUNT_EXTENDED 4
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static const struct nv_ethtool_str nv_etests_str[] = {
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{ "link (online/offline)" },
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{ "register (offline) " },
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{ "interrupt (offline) " },
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{ "loopback (offline) " }
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};
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struct register_test {
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u32 reg;
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u32 mask;
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};
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static const struct register_test nv_registers_test[] = {
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{ NvRegUnknownSetupReg6, 0x01 },
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{ NvRegMisc1, 0x03c },
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{ NvRegOffloadConfig, 0x03ff },
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{ NvRegMulticastAddrA, 0xffffffff },
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{ NvRegUnknownSetupReg3, 0x0ff },
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{ NvRegWakeUpFlags, 0x07777 },
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{ 0,0 }
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};
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/*
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* SMP locking:
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* All hardware access under dev->priv->lock, except the performance
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@ -662,6 +690,7 @@ struct fe_priv {
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int wolenabled;
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unsigned int phy_oui;
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u16 gigabit;
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int intr_test;
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/* General data: RO fields */
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dma_addr_t ring_addr;
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@ -2502,6 +2531,36 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
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return IRQ_RETVAL(i);
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}
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static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
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{
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struct net_device *dev = (struct net_device *) data;
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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u32 events;
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dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
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if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
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events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
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writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
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} else {
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events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
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writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
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}
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pci_push(base);
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dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
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if (!(events & NVREG_IRQ_TIMER))
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return IRQ_RETVAL(0);
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spin_lock(&np->lock);
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np->intr_test = 1;
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spin_unlock(&np->lock);
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dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
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return IRQ_RETVAL(1);
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}
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static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
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{
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u8 __iomem *base = get_hwbase(dev);
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@ -2528,7 +2587,7 @@ static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
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writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
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}
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static int nv_request_irq(struct net_device *dev)
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static int nv_request_irq(struct net_device *dev, int intr_test)
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{
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struct fe_priv *np = get_nvpriv(dev);
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u8 __iomem *base = get_hwbase(dev);
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@ -2541,7 +2600,7 @@ static int nv_request_irq(struct net_device *dev)
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}
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if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
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np->msi_flags |= NV_MSI_X_ENABLED;
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if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
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if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
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/* Request irq for rx handling */
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if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) {
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printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
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@ -2571,7 +2630,10 @@ static int nv_request_irq(struct net_device *dev)
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set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
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} else {
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/* Request irq for all interrupts */
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if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
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if ((!intr_test &&
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request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) ||
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(intr_test &&
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request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) {
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printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
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pci_disable_msix(np->pci_dev);
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np->msi_flags &= ~NV_MSI_X_ENABLED;
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@ -2587,7 +2649,8 @@ static int nv_request_irq(struct net_device *dev)
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if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
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if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
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np->msi_flags |= NV_MSI_ENABLED;
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if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) {
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if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) ||
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(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) {
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printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
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pci_disable_msi(np->pci_dev);
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np->msi_flags &= ~NV_MSI_ENABLED;
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@ -2602,8 +2665,10 @@ static int nv_request_irq(struct net_device *dev)
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}
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}
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if (ret != 0) {
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if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0)
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if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) ||
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(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0))
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goto out_err;
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}
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return 0;
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@ -3387,12 +3452,335 @@ static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *e
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memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
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}
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static int nv_self_test_count(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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if (np->driver_data & DEV_HAS_TEST_EXTENDED)
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return NV_TEST_COUNT_EXTENDED;
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else
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return NV_TEST_COUNT_BASE;
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}
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static int nv_link_test(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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int mii_status;
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mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
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mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
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/* check phy link status */
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if (!(mii_status & BMSR_LSTATUS))
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return 0;
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else
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return 1;
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}
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static int nv_register_test(struct net_device *dev)
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{
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u8 __iomem *base = get_hwbase(dev);
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int i = 0;
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u32 orig_read, new_read;
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do {
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orig_read = readl(base + nv_registers_test[i].reg);
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/* xor with mask to toggle bits */
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orig_read ^= nv_registers_test[i].mask;
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writel(orig_read, base + nv_registers_test[i].reg);
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new_read = readl(base + nv_registers_test[i].reg);
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if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
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return 0;
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/* restore original value */
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orig_read ^= nv_registers_test[i].mask;
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writel(orig_read, base + nv_registers_test[i].reg);
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} while (nv_registers_test[++i].reg != 0);
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return 1;
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}
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static int nv_interrupt_test(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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int ret = 1;
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int testcnt;
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u32 save_msi_flags, save_poll_interval = 0;
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if (netif_running(dev)) {
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/* free current irq */
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nv_free_irq(dev);
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save_poll_interval = readl(base+NvRegPollingInterval);
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}
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/* flag to test interrupt handler */
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np->intr_test = 0;
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/* setup test irq */
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save_msi_flags = np->msi_flags;
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np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
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np->msi_flags |= 0x001; /* setup 1 vector */
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if (nv_request_irq(dev, 1))
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return 0;
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/* setup timer interrupt */
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writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
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writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
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nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
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/* wait for at least one interrupt */
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msleep(100);
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spin_lock_irq(&np->lock);
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/* flag should be set within ISR */
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testcnt = np->intr_test;
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if (!testcnt)
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ret = 2;
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nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
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if (!(np->msi_flags & NV_MSI_X_ENABLED))
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writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
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else
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writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
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spin_unlock_irq(&np->lock);
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nv_free_irq(dev);
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np->msi_flags = save_msi_flags;
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if (netif_running(dev)) {
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writel(save_poll_interval, base + NvRegPollingInterval);
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writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
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/* restore original irq */
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if (nv_request_irq(dev, 0))
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return 0;
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}
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return ret;
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}
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static int nv_loopback_test(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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struct sk_buff *tx_skb, *rx_skb;
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dma_addr_t test_dma_addr;
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u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
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u32 Flags;
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int len, i, pkt_len;
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u8 *pkt_data;
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u32 filter_flags = 0;
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u32 misc1_flags = 0;
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int ret = 1;
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if (netif_running(dev)) {
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nv_disable_irq(dev);
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filter_flags = readl(base + NvRegPacketFilterFlags);
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misc1_flags = readl(base + NvRegMisc1);
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} else {
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nv_txrx_reset(dev);
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}
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/* reinit driver view of the rx queue */
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set_bufsize(dev);
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nv_init_ring(dev);
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/* setup hardware for loopback */
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writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
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writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
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/* reinit nic view of the rx queue */
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writel(np->rx_buf_sz, base + NvRegOffloadConfig);
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setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
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writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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pci_push(base);
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/* restart rx engine */
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nv_start_rx(dev);
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nv_start_tx(dev);
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/* setup packet for tx */
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pkt_len = ETH_DATA_LEN;
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tx_skb = dev_alloc_skb(pkt_len);
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pkt_data = skb_put(tx_skb, pkt_len);
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for (i = 0; i < pkt_len; i++)
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pkt_data[i] = (u8)(i & 0xff);
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test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
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tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr);
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np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
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} else {
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np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32;
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np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
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np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
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}
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writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
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pci_push(get_hwbase(dev));
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msleep(500);
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/* check for rx of the packet */
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
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len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
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} else {
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Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
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len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
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}
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if (Flags & NV_RX_AVAIL) {
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ret = 0;
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} else if (np->desc_ver == DESC_VER_1) {
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if (Flags & NV_RX_ERROR)
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ret = 0;
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} else {
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if (Flags & NV_RX2_ERROR) {
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ret = 0;
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}
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}
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if (ret) {
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if (len != pkt_len) {
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ret = 0;
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dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
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dev->name, len, pkt_len);
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} else {
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rx_skb = np->rx_skbuff[0];
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for (i = 0; i < pkt_len; i++) {
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if (rx_skb->data[i] != (u8)(i & 0xff)) {
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ret = 0;
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dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
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dev->name, i);
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break;
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}
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}
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}
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} else {
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dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
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}
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pci_unmap_page(np->pci_dev, test_dma_addr,
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tx_skb->end-tx_skb->data,
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PCI_DMA_TODEVICE);
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dev_kfree_skb_any(tx_skb);
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/* stop engines */
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nv_stop_rx(dev);
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nv_stop_tx(dev);
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nv_txrx_reset(dev);
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/* drain rx queue */
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nv_drain_rx(dev);
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nv_drain_tx(dev);
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if (netif_running(dev)) {
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writel(misc1_flags, base + NvRegMisc1);
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writel(filter_flags, base + NvRegPacketFilterFlags);
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nv_enable_irq(dev);
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}
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return ret;
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}
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static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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int result;
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memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
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if (!nv_link_test(dev)) {
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test->flags |= ETH_TEST_FL_FAILED;
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buffer[0] = 1;
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}
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if (test->flags & ETH_TEST_FL_OFFLINE) {
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if (netif_running(dev)) {
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netif_stop_queue(dev);
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spin_lock_bh(&dev->xmit_lock);
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||||
spin_lock_irq(&np->lock);
|
||||
nv_disable_hw_interrupts(dev, np->irqmask);
|
||||
if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
|
||||
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
|
||||
} else {
|
||||
writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
|
||||
}
|
||||
/* stop engines */
|
||||
nv_stop_rx(dev);
|
||||
nv_stop_tx(dev);
|
||||
nv_txrx_reset(dev);
|
||||
/* drain rx queue */
|
||||
nv_drain_rx(dev);
|
||||
nv_drain_tx(dev);
|
||||
spin_unlock_irq(&np->lock);
|
||||
spin_unlock_bh(&dev->xmit_lock);
|
||||
}
|
||||
|
||||
if (!nv_register_test(dev)) {
|
||||
test->flags |= ETH_TEST_FL_FAILED;
|
||||
buffer[1] = 1;
|
||||
}
|
||||
|
||||
result = nv_interrupt_test(dev);
|
||||
if (result != 1) {
|
||||
test->flags |= ETH_TEST_FL_FAILED;
|
||||
buffer[2] = 1;
|
||||
}
|
||||
if (result == 0) {
|
||||
/* bail out */
|
||||
return;
|
||||
}
|
||||
|
||||
if (!nv_loopback_test(dev)) {
|
||||
test->flags |= ETH_TEST_FL_FAILED;
|
||||
buffer[3] = 1;
|
||||
}
|
||||
|
||||
if (netif_running(dev)) {
|
||||
/* reinit driver view of the rx queue */
|
||||
set_bufsize(dev);
|
||||
if (nv_init_ring(dev)) {
|
||||
if (!np->in_shutdown)
|
||||
mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
|
||||
}
|
||||
/* reinit nic view of the rx queue */
|
||||
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
|
||||
setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
|
||||
writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
|
||||
base + NvRegRingSizes);
|
||||
pci_push(base);
|
||||
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
|
||||
pci_push(base);
|
||||
/* restart rx engine */
|
||||
nv_start_rx(dev);
|
||||
nv_start_tx(dev);
|
||||
netif_start_queue(dev);
|
||||
nv_enable_hw_interrupts(dev, np->irqmask);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
|
||||
{
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
|
||||
break;
|
||||
case ETH_SS_TEST:
|
||||
memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -3422,6 +3810,8 @@ static struct ethtool_ops ops = {
|
||||
.get_strings = nv_get_strings,
|
||||
.get_stats_count = nv_get_stats_count,
|
||||
.get_ethtool_stats = nv_get_ethtool_stats,
|
||||
.self_test_count = nv_self_test_count,
|
||||
.self_test = nv_self_test,
|
||||
};
|
||||
|
||||
static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
|
||||
@ -3554,7 +3944,7 @@ static int nv_open(struct net_device *dev)
|
||||
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
|
||||
pci_push(base);
|
||||
|
||||
if (nv_request_irq(dev)) {
|
||||
if (nv_request_irq(dev, 0)) {
|
||||
goto out_drain;
|
||||
}
|
||||
|
||||
@ -4049,11 +4439,11 @@ static struct pci_device_id pci_tbl[] = {
|
||||
},
|
||||
{ /* MCP55 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
|
||||
},
|
||||
{ /* MCP55 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
|
||||
},
|
||||
{0,},
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user