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dt-bindings: firmware: imx-scu: remove unused resources from scu resource table

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Removes below resources which were defined during
pre-silicon phase and the real silicons do NOT have
them, they have never been used, latest system
controller firmware also removed them:

	IMX_SC_R_DC_0_CAPTURE0
	IMX_SC_R_DC_0_CAPTURE1
	IMX_SC_R_DC_0_INTEGRAL0
	IMX_SC_R_DC_0_INTEGRAL1
	IMX_SC_R_DC_0_FRAC1
	IMX_SC_R_DC_1_CAPTURE0
	IMX_SC_R_DC_1_CAPTURE1
	IMX_SC_R_DC_1_INTEGRAL0
	IMX_SC_R_DC_1_INTEGRAL1
	IMX_SC_R_DC_1_FRAC1
	IMX_SC_R_GPU_3_PID0
	IMX_SC_R_M4_0_SIM
	IMX_SC_R_M4_0_WDOG
	IMX_SC_R_M4_1_SIM
	IMX_SC_R_M4_1_WDOG

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Anson Huang 2019-02-27 00:53:04 +00:00 committed by Shawn Guo
parent 9e98c678c2
commit 9613163a28
1 changed files with 0 additions and 15 deletions
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15
include/dt-bindings/firmware/imx/rsrc.h
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@ -36,15 +36,10 @@
#define IMX_SC_R_DC_0_BLIT1 20 #define IMX_SC_R_DC_0_BLIT1 20
#define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT2 21
#define IMX_SC_R_DC_0_BLIT_OUT 22 #define IMX_SC_R_DC_0_BLIT_OUT 22
#define IMX_SC_R_DC_0_CAPTURE0 23
#define IMX_SC_R_DC_0_CAPTURE1 24
#define IMX_SC_R_DC_0_WARP 25 #define IMX_SC_R_DC_0_WARP 25
#define IMX_SC_R_DC_0_INTEGRAL0 26
#define IMX_SC_R_DC_0_INTEGRAL1 27
#define IMX_SC_R_DC_0_VIDEO0 28 #define IMX_SC_R_DC_0_VIDEO0 28
#define IMX_SC_R_DC_0_VIDEO1 29 #define IMX_SC_R_DC_0_VIDEO1 29
#define IMX_SC_R_DC_0_FRAC0 30 #define IMX_SC_R_DC_0_FRAC0 30
#define IMX_SC_R_DC_0_FRAC1 31
#define IMX_SC_R_DC_0 32 #define IMX_SC_R_DC_0 32
#define IMX_SC_R_GPU_2_PID0 33 #define IMX_SC_R_GPU_2_PID0 33
#define IMX_SC_R_DC_0_PLL_0 34 #define IMX_SC_R_DC_0_PLL_0 34
@ -53,17 +48,11 @@
#define IMX_SC_R_DC_1_BLIT1 37 #define IMX_SC_R_DC_1_BLIT1 37
#define IMX_SC_R_DC_1_BLIT2 38 #define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39 #define IMX_SC_R_DC_1_BLIT_OUT 39
#define IMX_SC_R_DC_1_CAPTURE0 40
#define IMX_SC_R_DC_1_CAPTURE1 41
#define IMX_SC_R_DC_1_WARP 42 #define IMX_SC_R_DC_1_WARP 42
#define IMX_SC_R_DC_1_INTEGRAL0 43
#define IMX_SC_R_DC_1_INTEGRAL1 44
#define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47 #define IMX_SC_R_DC_1_FRAC0 47
#define IMX_SC_R_DC_1_FRAC1 48
#define IMX_SC_R_DC_1 49 #define IMX_SC_R_DC_1 49
#define IMX_SC_R_GPU_3_PID0 50
#define IMX_SC_R_DC_1_PLL_0 51 #define IMX_SC_R_DC_1_PLL_0 51
#define IMX_SC_R_DC_1_PLL_1 52 #define IMX_SC_R_DC_1_PLL_1 52
#define IMX_SC_R_SPI_0 53 #define IMX_SC_R_SPI_0 53
@ -303,8 +292,6 @@
#define IMX_SC_R_M4_0_UART 287 #define IMX_SC_R_M4_0_UART 287
#define IMX_SC_R_M4_0_I2C 288 #define IMX_SC_R_M4_0_I2C 288
#define IMX_SC_R_M4_0_INTMUX 289 #define IMX_SC_R_M4_0_INTMUX 289
#define IMX_SC_R_M4_0_SIM 290
#define IMX_SC_R_M4_0_WDOG 291
#define IMX_SC_R_M4_0_MU_0B 292 #define IMX_SC_R_M4_0_MU_0B 292
#define IMX_SC_R_M4_0_MU_0A0 293 #define IMX_SC_R_M4_0_MU_0A0 293
#define IMX_SC_R_M4_0_MU_0A1 294 #define IMX_SC_R_M4_0_MU_0A1 294
@ -323,8 +310,6 @@
#define IMX_SC_R_M4_1_UART 307 #define IMX_SC_R_M4_1_UART 307
#define IMX_SC_R_M4_1_I2C 308 #define IMX_SC_R_M4_1_I2C 308
#define IMX_SC_R_M4_1_INTMUX 309 #define IMX_SC_R_M4_1_INTMUX 309
#define IMX_SC_R_M4_1_SIM 310
#define IMX_SC_R_M4_1_WDOG 311
#define IMX_SC_R_M4_1_MU_0B 312 #define IMX_SC_R_M4_1_MU_0B 312
#define IMX_SC_R_M4_1_MU_0A0 313 #define IMX_SC_R_M4_1_MU_0A0 313
#define IMX_SC_R_M4_1_MU_0A1 314 #define IMX_SC_R_M4_1_MU_0A1 314