forked from luck/tmp_suning_uos_patched
* Drop support for 10-bit I2C addresses
* Add support for limited bus mode * Fix the Cadence DT binding doc * Use struct_size() to allocate a DEFSLVS packet -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEKmCqpbOU668PNA69Ze02AX4ItwAFAl0gTH0ACgkQZe02AX4I twCTwRAAhuaDKLP5fI16392s0G+66V82u9Kdn1pF8bD6r8wcyRjkBsp2p73VPu4D ASIKH+XDDegy8H9+N7kZ7w4dYPqei/Rb4VhsUuaaC608iDvN8DCYG2ciMOr5eggv ejFt56MeMiON9BYUbk9KQJvNfaiN4d4dtFGuRETpYEGR9NG9V8Y3oQhWOG+EcWO3 RBKYNi6QDo1y5NEhrsr8m7fdz0S1F8A7DgPirwkARYAAl9LBmdUllt8+h+WHUt7I 1GJwA4ZCgXJYSGXw6Vf2p8RYakzAz6G7fTqx9maMRCwMqYKvucb0Opxe7jRnhS3s JPBVqwMdk3Dn4EWpWENgbGHIdJVwqOGxueKf1vtP64+WaUxG7AioS1QFcgPgSqPg 7yRbGreO0nCPmW1v2X+2DEYE4iTyB5Sf2xcRrNYyLjAyO2elVjNuzx+IMA2d3nK3 BS0kMaKjanSP1INCUsIiE/ISRQxQypTrYcoD4jpo/wV43MnOLDn93M9KrlhY5dOn M4rQg3FXiLeBhj+1NQPs6ac7LKkUgIIVl8+z2C8z+4DoY1LT+DsxI31YGqRly/H3 quRtBIpCXVDxd69V9bPWpINZhXeP9ccgHDBTwfQJQk8bNfdJk4dh5ydntnO9rqmp nXhBPKgww0BlHecihrIf+RpxH4q6XmvFdpCDNTH1pgdtLCwblcQ= =Uj8o -----END PGP SIGNATURE----- Merge tag 'i3c/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux Pull ic3 updates from Boris Brezillon: - Drop support for 10-bit I2C addresses - Add support for limited bus mode - Fix the Cadence DT binding doc - Use struct_size() to allocate a DEFSLVS packet * tag 'i3c/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux: i3c: master: Use struct_size() helper dt-bindings: i3c: cdns: Use correct cells for I2C device i3c: dw: add limited bus mode support i3c: add mixed limited bus mode i3c: fix i2c and i3c scl rate by bus mode dt-bindings: i3c: Document dropped support for I2C 10 bit devices i3c: Drop support for I2C 10 bit addresing
This commit is contained in:
Linus Torvalds
commit
96407298ff
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@ -38,6 +38,6 @@ Example:
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nunchuk: nunchuk@52 {
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compatible = "nintendo,nunchuk";
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reg = <0x52 0x80000010 0>;
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reg = <0x52 0x0 0x10>;
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};
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};
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@ -39,7 +39,9 @@ valid here, but several new properties have been added.
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New constraint on existing properties:
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--------------------------------------
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- reg: contains 3 cells
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+ first cell : still encoding the I2C address
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+ first cell : still encoding the I2C address. 10 bit addressing is not
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supported. Devices with 10 bit address can't be properly passed through
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DEFSLVS command.
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+ second cell: shall be 0
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@ -91,6 +91,12 @@ void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
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up_read(&bus->lock);
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}
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static struct i3c_master_controller *
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i3c_bus_to_i3c_master(struct i3c_bus *i3cbus)
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{
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return container_of(i3cbus, struct i3c_master_controller, bus);
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}
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static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev)
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{
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return container_of(dev, struct i3c_master_controller, dev);
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@ -464,6 +470,7 @@ static int i3c_bus_init(struct i3c_bus *i3cbus)
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static const char * const i3c_bus_mode_strings[] = {
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[I3C_BUS_MODE_PURE] = "pure",
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[I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",
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[I3C_BUS_MODE_MIXED_LIMITED] = "mixed-limited",
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[I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",
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};
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@ -565,20 +572,39 @@ static const struct device_type i3c_masterdev_type = {
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.groups = i3c_masterdev_groups,
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};
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int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode)
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int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode,
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unsigned long max_i2c_scl_rate)
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{
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struct i3c_master_controller *master = i3c_bus_to_i3c_master(i3cbus);
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i3cbus->mode = mode;
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if (!i3cbus->scl_rate.i3c)
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i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
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if (!i3cbus->scl_rate.i2c) {
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if (i3cbus->mode == I3C_BUS_MODE_MIXED_SLOW)
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i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
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else
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i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
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switch (i3cbus->mode) {
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case I3C_BUS_MODE_PURE:
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if (!i3cbus->scl_rate.i3c)
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i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
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break;
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case I3C_BUS_MODE_MIXED_FAST:
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case I3C_BUS_MODE_MIXED_LIMITED:
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if (!i3cbus->scl_rate.i3c)
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i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
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if (!i3cbus->scl_rate.i2c)
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i3cbus->scl_rate.i2c = max_i2c_scl_rate;
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break;
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case I3C_BUS_MODE_MIXED_SLOW:
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if (!i3cbus->scl_rate.i2c)
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i3cbus->scl_rate.i2c = max_i2c_scl_rate;
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if (!i3cbus->scl_rate.i3c ||
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i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c)
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i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c;
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break;
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default:
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return -EINVAL;
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}
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dev_dbg(&master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n",
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i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c);
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/*
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* I3C/I2C frequency may have been overridden, check that user-provided
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* values are not exceeding max possible frequency.
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@ -924,9 +950,8 @@ int i3c_master_defslvs_locked(struct i3c_master_controller *master)
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ndevs++;
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defslvs = i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR,
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sizeof(*defslvs) +
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((ndevs - 1) *
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sizeof(struct i3c_ccc_dev_desc)));
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struct_size(defslvs, slaves,
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ndevs - 1));
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if (!defslvs)
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return -ENOMEM;
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@ -1963,12 +1988,19 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
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if (ret)
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return ret;
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/*
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* The I3C Specification does not clearly say I2C devices with 10-bit
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* address are supported. These devices can't be passed properly through
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* DEFSLVS command.
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*/
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if (boardinfo->base.flags & I2C_CLIENT_TEN) {
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dev_err(&master->dev, "I2C device with 10 bit address not supported.");
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return -ENOTSUPP;
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}
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/* LVR is encoded in reg[2]. */
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boardinfo->lvr = reg[2];
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if (boardinfo->lvr & I3C_LVR_I2C_FM_MODE)
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master->bus.scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
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list_add_tail(&boardinfo->node, &master->boardinfo.i2c);
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of_node_get(node);
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@ -2111,16 +2143,14 @@ static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
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return ret ? ret : nxfers;
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}
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static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
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static u32 i3c_master_i2c_funcs(struct i2c_adapter *adapter)
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{
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struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
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return master->ops->i2c_funcs(master);
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return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
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}
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static const struct i2c_algorithm i3c_master_i2c_algo = {
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.master_xfer = i3c_master_i2c_adapter_xfer,
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.functionality = i3c_master_i2c_functionalities,
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.functionality = i3c_master_i2c_funcs,
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};
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static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
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@ -2379,8 +2409,7 @@ EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot);
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static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops)
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{
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if (!ops || !ops->bus_init || !ops->priv_xfers ||
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!ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers ||
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!ops->i2c_funcs)
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!ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers)
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return -EINVAL;
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if (ops->request_ibi &&
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@ -2417,6 +2446,7 @@ int i3c_master_register(struct i3c_master_controller *master,
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const struct i3c_master_controller_ops *ops,
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bool secondary)
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{
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unsigned long i2c_scl_rate = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
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struct i3c_bus *i3cbus = i3c_master_get_bus(master);
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enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
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struct i2c_dev_boardinfo *i2cbi;
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@ -2458,6 +2488,9 @@ int i3c_master_register(struct i3c_master_controller *master,
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mode = I3C_BUS_MODE_MIXED_FAST;
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break;
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case I3C_LVR_I2C_INDEX(1):
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if (mode < I3C_BUS_MODE_MIXED_LIMITED)
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mode = I3C_BUS_MODE_MIXED_LIMITED;
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break;
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case I3C_LVR_I2C_INDEX(2):
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if (mode < I3C_BUS_MODE_MIXED_SLOW)
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mode = I3C_BUS_MODE_MIXED_SLOW;
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@ -2466,9 +2499,12 @@ int i3c_master_register(struct i3c_master_controller *master,
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ret = -EINVAL;
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goto err_put_dev;
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}
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if (i2cbi->lvr & I3C_LVR_I2C_FM_MODE)
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i2c_scl_rate = I3C_BUS_I2C_FM_SCL_RATE;
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}
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ret = i3c_bus_set_mode(i3cbus, mode);
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ret = i3c_bus_set_mode(i3cbus, mode, i2c_scl_rate);
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if (ret)
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goto err_put_dev;
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@ -599,6 +599,7 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
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switch (bus->mode) {
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case I3C_BUS_MODE_MIXED_FAST:
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case I3C_BUS_MODE_MIXED_LIMITED:
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ret = dw_i2c_clk_cfg(master);
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if (ret)
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return ret;
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@ -1060,11 +1061,6 @@ static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
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kfree(data);
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}
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static u32 dw_i3c_master_i2c_funcs(struct i3c_master_controller *m)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
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{
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struct dw_i3c_master *master = dev_id;
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@ -1099,7 +1095,6 @@ static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
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.attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
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.detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
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.i2c_xfers = dw_i3c_master_i2c_xfers,
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.i2c_funcs = dw_i3c_master_i2c_funcs,
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};
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static int dw_i3c_probe(struct platform_device *pdev)
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@ -864,11 +864,6 @@ static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
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return ret;
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}
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static u32 cdns_i3c_master_i2c_funcs(struct i3c_master_controller *m)
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{
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return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
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}
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struct cdns_i3c_i2c_dev_data {
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u16 id;
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s16 ibi;
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@ -1010,9 +1005,7 @@ static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
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master->free_rr_slots &= ~BIT(slot);
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i2c_dev_set_master_data(dev, data);
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writel(prepare_rr0_dev_address(dev->boardinfo->base.addr) |
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(dev->boardinfo->base.flags & I2C_CLIENT_TEN ?
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DEV_ID_RR0_LVR_EXT_ADDR : 0),
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writel(prepare_rr0_dev_address(dev->boardinfo->base.addr),
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master->regs + DEV_ID_RR0(data->id));
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writel(dev->boardinfo->lvr, master->regs + DEV_ID_RR2(data->id));
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writel(readl(master->regs + DEVS_CTRL) |
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@ -1518,7 +1511,6 @@ static const struct i3c_master_controller_ops cdns_i3c_master_ops = {
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.send_ccc_cmd = cdns_i3c_master_send_ccc_cmd,
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.priv_xfers = cdns_i3c_master_priv_xfers,
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.i2c_xfers = cdns_i3c_master_i2c_xfers,
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.i2c_funcs = cdns_i3c_master_i2c_funcs,
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.enable_ibi = cdns_i3c_master_enable_ibi,
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.disable_ibi = cdns_i3c_master_disable_ibi,
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.request_ibi = cdns_i3c_master_request_ibi,
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@ -48,7 +48,7 @@ struct i3c_i2c_dev_desc {
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#define I3C_LVR_I2C_INDEX(x) ((x) << 5)
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#define I3C_LVR_I2C_FM_MODE BIT(4)
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#define I2C_MAX_ADDR GENMASK(9, 0)
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#define I2C_MAX_ADDR GENMASK(6, 0)
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/**
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* struct i2c_dev_boardinfo - I2C device board information
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@ -250,12 +250,17 @@ struct i3c_device {
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* the bus. The only impact in this mode is that the
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* high SCL pulse has to stay below 50ns to trick I2C
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* devices when transmitting I3C frames
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* @I3C_BUS_MODE_MIXED_LIMITED: I2C devices without 50ns spike filter are
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* present on the bus. However they allow
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* compliance up to the maximum SDR SCL clock
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* frequency.
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* @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present
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* on the bus
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*/
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enum i3c_bus_mode {
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I3C_BUS_MODE_PURE,
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I3C_BUS_MODE_MIXED_FAST,
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I3C_BUS_MODE_MIXED_LIMITED,
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I3C_BUS_MODE_MIXED_SLOW,
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};
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@ -390,8 +395,6 @@ struct i3c_bus {
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* and i2c_put_dma_safe_msg_buf() helpers provided by the I2C
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* framework.
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* This method is mandatory.
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* @i2c_funcs: expose the supported I2C functionalities.
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* This method is mandatory.
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* @request_ibi: attach an IBI handler to an I3C device. This implies defining
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* an IBI handler and the constraints of the IBI (maximum payload
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* length and number of pre-allocated slots).
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@ -437,7 +440,6 @@ struct i3c_master_controller_ops {
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void (*detach_i2c_dev)(struct i2c_dev_desc *dev);
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int (*i2c_xfers)(struct i2c_dev_desc *dev,
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const struct i2c_msg *xfers, int nxfers);
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u32 (*i2c_funcs)(struct i3c_master_controller *master);
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int (*request_ibi)(struct i3c_dev_desc *dev,
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const struct i3c_ibi_setup *req);
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void (*free_ibi)(struct i3c_dev_desc *dev);
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|
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