forked from luck/tmp_suning_uos_patched
ARM: OMAP: Add DMTIMER definitions for posted mode
For OMAP2+ devices, when using DMTIMERs for system timers (clock-events and clock-source) the posted mode configuration of the timers is used. To allow the compiler to optimise the functions for configuring and reading the system timers, the posted flag variable is hard-coded with the value 1. To make it clear that posted mode is being used add some definitions so that it is more readable. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -108,7 +108,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
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0xffffffff - cycles, 1);
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0xffffffff - cycles, OMAP_TIMER_POSTED);
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return 0;
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}
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@ -118,7 +118,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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{
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u32 period;
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__omap_dm_timer_stop(&clkev, 1, clkev.rate);
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__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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@ -126,10 +126,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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period -= 1;
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/* Looks like we need to first set the load value separately */
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__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
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0xffffffff - period, 1);
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0xffffffff - period, OMAP_TIMER_POSTED);
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__omap_dm_timer_load_start(&clkev,
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OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
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0xffffffff - period, 1);
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0xffffffff - period, OMAP_TIMER_POSTED);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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@ -359,7 +359,8 @@ static bool use_gptimer_clksrc;
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*/
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static cycle_t clocksource_read_cycles(struct clocksource *cs)
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{
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return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
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return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
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OMAP_TIMER_POSTED);
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}
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static struct clocksource clocksource_gpt = {
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@ -373,7 +374,8 @@ static struct clocksource clocksource_gpt = {
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static u32 notrace dmtimer_read_sched_clock(void)
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{
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if (clksrc.reserved)
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return __omap_dm_timer_read_counter(&clksrc, 1);
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return __omap_dm_timer_read_counter(&clksrc,
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OMAP_TIMER_POSTED);
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return 0;
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}
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@ -455,7 +457,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
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BUG_ON(res);
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__omap_dm_timer_load_start(&clksrc,
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OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
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OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
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OMAP_TIMER_POSTED);
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setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
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if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
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@ -55,6 +55,10 @@
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#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
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#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
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/* posted mode types */
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#define OMAP_TIMER_NONPOSTED 0x00
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#define OMAP_TIMER_POSTED 0x01
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/* timer capabilities used in hwmod database */
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#define OMAP_TIMER_SECURE 0x80000000
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#define OMAP_TIMER_ALWON 0x40000000
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