forked from luck/tmp_suning_uos_patched
usb: dwc3: ulpi: Replace CPU-based busyloop with Protocol-based one
commit fca3f138105727c3a22edda32d02f91ce1bf11c9 upstream.
Originally the procedure of the ULPI transaction finish detection has been
developed as a simple busy-loop with just decrementing counter and no
delays. It's wrong since on different systems the loop will take a
different time to complete. So if the system bus and CPU are fast enough
to overtake the ULPI bus and the companion PHY reaction, then we'll get to
take a false timeout error. Fix this by converting the busy-loop procedure
to take the standard bus speed, address value and the registers access
mode into account for the busy-loop delay calculation.
Here is the way the fix works. It's known that the ULPI bus is clocked
with 60MHz signal. In accordance with [1] the ULPI bus protocol is created
so to spend 5 and 6 clock periods for immediate register write and read
operations respectively, and 6 and 7 clock periods - for the extended
register writes and reads. Based on that we can easily pre-calculate the
time which will be needed for the controller to perform a requested IO
operation. Note we'll still preserve the attempts counter in case if the
DWC USB3 controller has got some internals delays.
[1] UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1,
October 20, 2004, pp. 30 - 36.
Fixes: 88bc9d194f
("usb: dwc3: add ULPI interface support")
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20201210085008.13264-3-Sergey.Semin@baikalelectronics.ru
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
b51963e9f5
commit
97abe6663f
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@ -7,6 +7,8 @@
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* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
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*/
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#include <linux/delay.h>
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#include <linux/time64.h>
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#include <linux/ulpi/regs.h>
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#include "core.h"
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@ -17,12 +19,22 @@
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DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
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DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
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static int dwc3_ulpi_busyloop(struct dwc3 *dwc)
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#define DWC3_ULPI_BASE_DELAY DIV_ROUND_UP(NSEC_PER_SEC, 60000000L)
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static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read)
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{
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unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY;
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unsigned int count = 1000;
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u32 reg;
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if (addr >= ULPI_EXT_VENDOR_SPECIFIC)
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ns += DWC3_ULPI_BASE_DELAY;
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if (read)
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ns += DWC3_ULPI_BASE_DELAY;
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while (count--) {
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ndelay(ns);
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
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if (reg & DWC3_GUSB2PHYACC_DONE)
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return 0;
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@ -47,7 +59,7 @@ static int dwc3_ulpi_read(struct device *dev, u8 addr)
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reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
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ret = dwc3_ulpi_busyloop(dwc);
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ret = dwc3_ulpi_busyloop(dwc, addr, true);
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if (ret)
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return ret;
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@ -71,7 +83,7 @@ static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
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reg |= DWC3_GUSB2PHYACC_WRITE | val;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
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return dwc3_ulpi_busyloop(dwc);
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return dwc3_ulpi_busyloop(dwc, addr, false);
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}
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static const struct ulpi_ops dwc3_ulpi_ops = {
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