AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

amd64_edac: remove early hw support check

Browse Source 
The .probe_valid_hardware low_ops member checked whether the DCTs are in
DDR3 mode and bailed out if so. Now that all the needed changes for DDR3
support is in place, remove it.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov 2009-11-11 20:42:46 +01:00
parent 6b4c0bdeb0
commit 986a42a250
2 changed files with 1 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
drivers/edac/amd64_edac.c
View File

@ -1738,42 +1738,6 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
}
}
/*
* Very early hardware probe on pci_probe thread to determine if this module
* supports the hardware.
*
* Return:
* 0 for OK
* 1 for error
*/
static int f10_probe_valid_hardware(struct amd64_pvt *pvt)
{
int ret = 0;
/*
* If we are on a DDR3 machine, we don't know yet if
* we support that properly at this time
*/
if ((pvt->dchr0 & DDR3_MODE) ||
(pvt->dchr1 & DDR3_MODE)) {
amd64_printk(KERN_WARNING,
"%s() This machine is running with DDR3 memory. "
"This is not currently supported. "
"DCHR0=0x%x DCHR1=0x%x\n",
__func__, pvt->dchr0, pvt->dchr1);
amd64_printk(KERN_WARNING,
" Contact '%s' module MAINTAINER to help add"
" support.\n",
EDAC_MOD_STR);
ret = 1;
}
return ret;
}
/*
* There currently are 3 types type of MC devices for AMD Athlon/Opterons
* (as per PCI DEVICE_IDs):
@ -1803,7 +1767,6 @@ static struct amd64_family_type amd64_family_types[] = {
.addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP,
.misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC,
.ops = {
.probe_valid_hardware = f10_probe_valid_hardware,
.early_channel_count = f10_early_channel_count,
.get_error_address = f10_get_error_address,
.read_dram_base_limit = f10_read_dram_base_limit,
@ -1817,7 +1780,6 @@ static struct amd64_family_type amd64_family_types[] = {
.addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP,
.misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC,
.ops = {
.probe_valid_hardware = f10_probe_valid_hardware,
.early_channel_count = f10_early_channel_count,
.get_error_address = f10_get_error_address,
.read_dram_base_limit = f10_read_dram_base_limit,
@ -2851,17 +2813,10 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
{
int node_id = pvt->mc_node_id;
struct mem_ctl_info *mci;
int ret, err = 0;
int ret;
amd64_read_mc_registers(pvt);
ret = -ENODEV;
if (pvt->ops->probe_valid_hardware) {
err = pvt->ops->probe_valid_hardware(pvt);
if (err)
goto err_exit;
}
/*
* We need to determine how many memory channels there are. Then use
* that information for calculating the size of the dynamic instance

1
drivers/edac/amd64_edac.h
View File

@ -526,7 +526,6 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
* functions and per device encoding/decoding logic.
*/
struct low_ops {
int (*probe_valid_hardware) (struct amd64_pvt *pvt);
int (*early_channel_count) (struct amd64_pvt *pvt);
u64 (*get_error_address) (struct mem_ctl_info *mci,