forked from luck/tmp_suning_uos_patched
Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6
* 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6: [PATCH] x86: Don't probe for DDC on VBE1.2 [PATCH] x86-64: Increase NMI watchdog probing timeout [PATCH] x86-64: Let oprofile reserve MSR on all CPUs [PATCH] x86-64: Disable local APIC timer use on AMD systems with C1E
This commit is contained in:
Linus Torvalds
commit
9a5ee4cc9e
@ -571,6 +571,16 @@ setr1: lodsw
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jmp _m_s
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check_vesa:
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#ifdef CONFIG_FIRMWARE_EDID
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leaw modelist+1024, %di
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movw $0x4f00, %ax
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int $0x10
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cmpw $0x004f, %ax
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jnz setbad
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movw 4(%di), %ax
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movw %ax, vbe_version
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#endif
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leaw modelist+1024, %di
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subb $VIDEO_FIRST_VESA>>8, %bh
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movw %bx, %cx # Get mode information structure
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@ -1945,6 +1955,9 @@ store_edid:
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rep
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stosl
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cmpw $0x0200, vbe_version # only do EDID on >= VBE2.0
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jl no_edid
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pushw %es # save ES
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xorw %di, %di # Report Capability
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pushw %di
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@ -1987,6 +2000,7 @@ do_restore: .byte 0 # Screen contents altered during mode change
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svga_prefix: .byte VIDEO_FIRST_BIOS>>8 # Default prefix for BIOS modes
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graphic_mode: .byte 0 # Graphic mode with a linear frame buffer
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dac_size: .byte 6 # DAC bit depth
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vbe_version: .word 0 # VBE bios version
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# Status messages
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keymsg: .ascii "Press <RETURN> to see video modes available, "
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@ -271,32 +271,6 @@ static void __devinit setup_APIC_timer(void)
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clockevents_register_device(levt);
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}
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/*
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* Detect systems with known broken BIOS implementations
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*/
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static int __init lapic_check_broken_bios(struct dmi_system_id *d)
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{
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printk(KERN_NOTICE "%s detected: disabling lapic timer.\n",
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d->ident);
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local_apic_timer_disabled = 1;
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return 0;
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}
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static struct dmi_system_id __initdata broken_bios_dmi_table[] = {
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{
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/*
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* BIOS exports only C1 state, but uses deeper power
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* modes behind the kernels back.
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*/
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.callback = lapic_check_broken_bios,
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.ident = "HP nx6325",
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"),
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},
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},
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{}
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};
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/*
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* In this functions we calibrate APIC bus clocks to the external timer.
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*
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@ -372,12 +346,12 @@ void __init setup_boot_APIC_clock(void)
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long delta, deltapm;
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int pm_referenced = 0;
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/* Detect know broken systems */
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dmi_check_system(broken_bios_dmi_table);
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if (boot_cpu_has(X86_FEATURE_LAPIC_TIMER_BROKEN))
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local_apic_timer_disabled = 1;
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/*
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* The local apic timer can be disabled via the kernel
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* commandline or from the dmi quirk above. Register the lapic
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* commandline or from the test above. Register the lapic
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* timer as a dummy clock event source on SMP systems, so the
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* broadcast mechanism is used. On UP systems simply ignore it.
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*/
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@ -22,6 +22,37 @@
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extern void vide(void);
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__asm__(".align 4\nvide: ret");
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#define ENABLE_C1E_MASK 0x18000000
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#define CPUID_PROCESSOR_SIGNATURE 1
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#define CPUID_XFAM 0x0ff00000
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#define CPUID_XFAM_K8 0x00000000
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#define CPUID_XFAM_10H 0x00100000
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#define CPUID_XFAM_11H 0x00200000
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#define CPUID_XMOD 0x000f0000
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#define CPUID_XMOD_REV_F 0x00040000
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/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
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static __cpuinit int amd_apic_timer_broken(void)
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{
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u32 lo, hi;
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u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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switch (eax & CPUID_XFAM) {
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case CPUID_XFAM_K8:
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if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
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break;
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case CPUID_XFAM_10H:
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case CPUID_XFAM_11H:
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rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
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if (lo & ENABLE_C1E_MASK)
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return 1;
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break;
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default:
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/* err on the side of caution */
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return 1;
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}
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return 0;
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}
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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@ -241,6 +272,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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if (cpuid_eax(0x80000000) >= 0x80000006)
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num_cache_leaves = 3;
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if (amd_apic_timer_broken())
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set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);
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}
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
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@ -122,64 +122,129 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
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/* checks for a bit availability (hack for oprofile) */
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int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
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{
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int cpu;
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
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for_each_possible_cpu (cpu) {
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if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
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return 0;
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}
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return 1;
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}
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/* checks the an msr for availability */
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int avail_to_resrv_perfctr_nmi(unsigned int msr)
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{
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unsigned int counter;
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int cpu;
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counter = nmi_perfctr_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
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for_each_possible_cpu (cpu) {
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if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
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return 0;
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}
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return 1;
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}
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static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
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{
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unsigned int counter;
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if (cpu < 0)
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cpu = smp_processor_id();
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counter = nmi_perfctr_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
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return 1;
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return 0;
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}
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static void __release_perfctr_nmi(int cpu, unsigned int msr)
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{
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unsigned int counter;
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if (cpu < 0)
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cpu = smp_processor_id();
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counter = nmi_perfctr_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu));
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}
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int reserve_perfctr_nmi(unsigned int msr)
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{
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unsigned int counter;
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counter = nmi_perfctr_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
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return 1;
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return 0;
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int cpu, i;
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for_each_possible_cpu (cpu) {
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if (!__reserve_perfctr_nmi(cpu, msr)) {
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for_each_possible_cpu (i) {
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if (i >= cpu)
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break;
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__release_perfctr_nmi(i, msr);
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}
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return 0;
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}
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}
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return 1;
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}
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void release_perfctr_nmi(unsigned int msr)
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{
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unsigned int counter;
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counter = nmi_perfctr_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
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int cpu;
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for_each_possible_cpu (cpu) {
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__release_perfctr_nmi(cpu, msr);
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}
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}
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int reserve_evntsel_nmi(unsigned int msr)
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int __reserve_evntsel_nmi(int cpu, unsigned int msr)
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{
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unsigned int counter;
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if (cpu < 0)
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cpu = smp_processor_id();
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counter = nmi_evntsel_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]))
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if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
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return 1;
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return 0;
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}
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void release_evntsel_nmi(unsigned int msr)
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static void __release_evntsel_nmi(int cpu, unsigned int msr)
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{
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unsigned int counter;
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if (cpu < 0)
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cpu = smp_processor_id();
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counter = nmi_evntsel_msr_to_bit(msr);
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]);
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clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
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}
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int reserve_evntsel_nmi(unsigned int msr)
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{
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int cpu, i;
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for_each_possible_cpu (cpu) {
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if (!__reserve_evntsel_nmi(cpu, msr)) {
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for_each_possible_cpu (i) {
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if (i >= cpu)
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break;
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__release_evntsel_nmi(i, msr);
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}
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return 0;
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}
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}
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return 1;
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}
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void release_evntsel_nmi(unsigned int msr)
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{
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int cpu;
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for_each_possible_cpu (cpu) {
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__release_evntsel_nmi(cpu, msr);
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}
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}
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static __cpuinit inline int nmi_known_cpu(void)
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@ -263,7 +328,7 @@ static int __init check_nmi_watchdog(void)
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for_each_possible_cpu(cpu)
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prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
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local_irq_enable();
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mdelay((10*1000)/nmi_hz); // wait 10 ticks
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mdelay((20*1000)/nmi_hz); // wait 20 ticks
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for_each_possible_cpu(cpu) {
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#ifdef CONFIG_SMP
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@ -507,10 +572,10 @@ static int setup_k7_watchdog(void)
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perfctr_msr = MSR_K7_PERFCTR0;
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evntsel_msr = MSR_K7_EVNTSEL0;
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if (!reserve_perfctr_nmi(perfctr_msr))
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if (!__reserve_perfctr_nmi(-1, perfctr_msr))
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goto fail;
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if (!reserve_evntsel_nmi(evntsel_msr))
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if (!__reserve_evntsel_nmi(-1, evntsel_msr))
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goto fail1;
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wrmsrl(perfctr_msr, 0UL);
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@ -533,7 +598,7 @@ static int setup_k7_watchdog(void)
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wd->check_bit = 1ULL<<63;
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return 1;
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fail1:
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release_perfctr_nmi(perfctr_msr);
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__release_perfctr_nmi(-1, perfctr_msr);
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fail:
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return 0;
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}
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@ -544,8 +609,8 @@ static void stop_k7_watchdog(void)
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wrmsr(wd->evntsel_msr, 0, 0);
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release_evntsel_nmi(wd->evntsel_msr);
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release_perfctr_nmi(wd->perfctr_msr);
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__release_evntsel_nmi(-1, wd->evntsel_msr);
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__release_perfctr_nmi(-1, wd->perfctr_msr);
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}
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#define P6_EVNTSEL0_ENABLE (1 << 22)
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@ -563,10 +628,10 @@ static int setup_p6_watchdog(void)
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perfctr_msr = MSR_P6_PERFCTR0;
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evntsel_msr = MSR_P6_EVNTSEL0;
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if (!reserve_perfctr_nmi(perfctr_msr))
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if (!__reserve_perfctr_nmi(-1, perfctr_msr))
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goto fail;
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||||
|
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if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
if (!__reserve_evntsel_nmi(-1, evntsel_msr))
|
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goto fail1;
|
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|
||||
wrmsrl(perfctr_msr, 0UL);
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@ -590,7 +655,7 @@ static int setup_p6_watchdog(void)
|
||||
wd->check_bit = 1ULL<<39;
|
||||
return 1;
|
||||
fail1:
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
__release_perfctr_nmi(-1, perfctr_msr);
|
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fail:
|
||||
return 0;
|
||||
}
|
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@ -601,8 +666,8 @@ static void stop_p6_watchdog(void)
|
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|
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wrmsr(wd->evntsel_msr, 0, 0);
|
||||
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
__release_evntsel_nmi(-1, wd->evntsel_msr);
|
||||
__release_perfctr_nmi(-1, wd->perfctr_msr);
|
||||
}
|
||||
|
||||
/* Note that these events don't tick when the CPU idles. This means
|
||||
@ -668,10 +733,10 @@ static int setup_p4_watchdog(void)
|
||||
cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
|
||||
}
|
||||
|
||||
if (!reserve_perfctr_nmi(perfctr_msr))
|
||||
if (!__reserve_perfctr_nmi(-1, perfctr_msr))
|
||||
goto fail;
|
||||
|
||||
if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
if (!__reserve_evntsel_nmi(-1, evntsel_msr))
|
||||
goto fail1;
|
||||
|
||||
evntsel = P4_ESCR_EVENT_SELECT(0x3F)
|
||||
@ -695,7 +760,7 @@ static int setup_p4_watchdog(void)
|
||||
wd->check_bit = 1ULL<<39;
|
||||
return 1;
|
||||
fail1:
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
__release_perfctr_nmi(-1, perfctr_msr);
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
@ -707,8 +772,8 @@ static void stop_p4_watchdog(void)
|
||||
wrmsr(wd->cccr_msr, 0, 0);
|
||||
wrmsr(wd->evntsel_msr, 0, 0);
|
||||
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
__release_evntsel_nmi(-1, wd->evntsel_msr);
|
||||
__release_perfctr_nmi(-1, wd->perfctr_msr);
|
||||
}
|
||||
|
||||
#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
|
||||
@ -736,10 +801,10 @@ static int setup_intel_arch_watchdog(void)
|
||||
perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
|
||||
evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
|
||||
|
||||
if (!reserve_perfctr_nmi(perfctr_msr))
|
||||
if (!__reserve_perfctr_nmi(-1, perfctr_msr))
|
||||
goto fail;
|
||||
|
||||
if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
if (!__reserve_evntsel_nmi(-1, evntsel_msr))
|
||||
goto fail1;
|
||||
|
||||
wrmsrl(perfctr_msr, 0UL);
|
||||
@ -764,7 +829,7 @@ static int setup_intel_arch_watchdog(void)
|
||||
wd->check_bit = 1ULL << (eax.split.bit_width - 1);
|
||||
return 1;
|
||||
fail1:
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
__release_perfctr_nmi(-1, perfctr_msr);
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
@ -787,8 +852,8 @@ static void stop_intel_arch_watchdog(void)
|
||||
return;
|
||||
|
||||
wrmsr(wd->evntsel_msr, 0, 0);
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
__release_evntsel_nmi(-1, wd->evntsel_msr);
|
||||
__release_perfctr_nmi(-1, wd->perfctr_msr);
|
||||
}
|
||||
|
||||
void setup_apic_nmi_watchdog (void *unused)
|
||||
|
||||
@ -571,6 +571,16 @@ setr1: lodsw
|
||||
jmp _m_s
|
||||
|
||||
check_vesa:
|
||||
#ifdef CONFIG_FIRMWARE_EDID
|
||||
leaw modelist+1024, %di
|
||||
movw $0x4f00, %ax
|
||||
int $0x10
|
||||
cmpw $0x004f, %ax
|
||||
jnz setbad
|
||||
|
||||
movw 4(%di), %ax
|
||||
movw %ax, vbe_version
|
||||
#endif
|
||||
leaw modelist+1024, %di
|
||||
subb $VIDEO_FIRST_VESA>>8, %bh
|
||||
movw %bx, %cx # Get mode information structure
|
||||
@ -1945,6 +1955,9 @@ store_edid:
|
||||
rep
|
||||
stosl
|
||||
|
||||
cmpw $0x0200, vbe_version # only do EDID on >= VBE2.0
|
||||
jl no_edid
|
||||
|
||||
pushw %es # save ES
|
||||
xorw %di, %di # Report Capability
|
||||
pushw %di
|
||||
@ -1987,6 +2000,7 @@ do_restore: .byte 0 # Screen contents altered during mode change
|
||||
svga_prefix: .byte VIDEO_FIRST_BIOS>>8 # Default prefix for BIOS modes
|
||||
graphic_mode: .byte 0 # Graphic mode with a linear frame buffer
|
||||
dac_size: .byte 6 # DAC bit depth
|
||||
vbe_version: .word 0 # VBE bios version
|
||||
|
||||
# Status messages
|
||||
keymsg: .ascii "Press <RETURN> to see video modes available, "
|
||||
|
||||
@ -108,64 +108,128 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
|
||||
/* checks for a bit availability (hack for oprofile) */
|
||||
int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
|
||||
{
|
||||
int cpu;
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
|
||||
for_each_possible_cpu (cpu) {
|
||||
if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* checks the an msr for availability */
|
||||
int avail_to_resrv_perfctr_nmi(unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
int cpu;
|
||||
|
||||
counter = nmi_perfctr_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
|
||||
for_each_possible_cpu (cpu) {
|
||||
if (test_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int __reserve_perfctr_nmi(int cpu, unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
if (cpu < 0)
|
||||
cpu = smp_processor_id();
|
||||
|
||||
counter = nmi_perfctr_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
if (!test_and_set_bit(counter, &per_cpu(perfctr_nmi_owner, cpu)))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __release_perfctr_nmi(int cpu, unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
if (cpu < 0)
|
||||
cpu = smp_processor_id();
|
||||
|
||||
counter = nmi_perfctr_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
clear_bit(counter, &per_cpu(perfctr_nmi_owner, cpu));
|
||||
}
|
||||
|
||||
int reserve_perfctr_nmi(unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
|
||||
counter = nmi_perfctr_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
|
||||
return 1;
|
||||
return 0;
|
||||
int cpu, i;
|
||||
for_each_possible_cpu (cpu) {
|
||||
if (!__reserve_perfctr_nmi(cpu, msr)) {
|
||||
for_each_possible_cpu (i) {
|
||||
if (i >= cpu)
|
||||
break;
|
||||
__release_perfctr_nmi(i, msr);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
void release_perfctr_nmi(unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
|
||||
counter = nmi_perfctr_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
|
||||
int cpu;
|
||||
for_each_possible_cpu (cpu)
|
||||
__release_perfctr_nmi(cpu, msr);
|
||||
}
|
||||
|
||||
int reserve_evntsel_nmi(unsigned int msr)
|
||||
int __reserve_evntsel_nmi(int cpu, unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
if (cpu < 0)
|
||||
cpu = smp_processor_id();
|
||||
|
||||
counter = nmi_evntsel_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
|
||||
if (!test_and_set_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void release_evntsel_nmi(unsigned int msr)
|
||||
static void __release_evntsel_nmi(int cpu, unsigned int msr)
|
||||
{
|
||||
unsigned int counter;
|
||||
if (cpu < 0)
|
||||
cpu = smp_processor_id();
|
||||
|
||||
counter = nmi_evntsel_msr_to_bit(msr);
|
||||
BUG_ON(counter > NMI_MAX_COUNTER_BITS);
|
||||
|
||||
clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
|
||||
clear_bit(counter, &per_cpu(evntsel_nmi_owner, cpu)[0]);
|
||||
}
|
||||
|
||||
int reserve_evntsel_nmi(unsigned int msr)
|
||||
{
|
||||
int cpu, i;
|
||||
for_each_possible_cpu (cpu) {
|
||||
if (!__reserve_evntsel_nmi(cpu, msr)) {
|
||||
for_each_possible_cpu (i) {
|
||||
if (i >= cpu)
|
||||
break;
|
||||
__release_evntsel_nmi(i, msr);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
void release_evntsel_nmi(unsigned int msr)
|
||||
{
|
||||
int cpu;
|
||||
for_each_possible_cpu (cpu) {
|
||||
__release_evntsel_nmi(cpu, msr);
|
||||
}
|
||||
}
|
||||
|
||||
static __cpuinit inline int nmi_known_cpu(void)
|
||||
@ -253,7 +317,7 @@ int __init check_nmi_watchdog (void)
|
||||
for (cpu = 0; cpu < NR_CPUS; cpu++)
|
||||
counts[cpu] = cpu_pda(cpu)->__nmi_count;
|
||||
local_irq_enable();
|
||||
mdelay((10*1000)/nmi_hz); // wait 10 ticks
|
||||
mdelay((20*1000)/nmi_hz); // wait 20 ticks
|
||||
|
||||
for_each_online_cpu(cpu) {
|
||||
if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
|
||||
@ -472,10 +536,10 @@ static int setup_k7_watchdog(void)
|
||||
|
||||
perfctr_msr = MSR_K7_PERFCTR0;
|
||||
evntsel_msr = MSR_K7_EVNTSEL0;
|
||||
if (!reserve_perfctr_nmi(perfctr_msr))
|
||||
if (!__reserve_perfctr_nmi(-1, perfctr_msr))
|
||||
goto fail;
|
||||
|
||||
if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
if (!__reserve_evntsel_nmi(-1, evntsel_msr))
|
||||
goto fail1;
|
||||
|
||||
/* Simulator may not support it */
|
||||
@ -501,9 +565,9 @@ static int setup_k7_watchdog(void)
|
||||
wd->check_bit = 1ULL<<63;
|
||||
return 1;
|
||||
fail2:
|
||||
release_evntsel_nmi(evntsel_msr);
|
||||
__release_evntsel_nmi(-1, evntsel_msr);
|
||||
fail1:
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
__release_perfctr_nmi(-1, perfctr_msr);
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
@ -514,8 +578,8 @@ static void stop_k7_watchdog(void)
|
||||
|
||||
wrmsr(wd->evntsel_msr, 0, 0);
|
||||
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
__release_evntsel_nmi(-1, wd->evntsel_msr);
|
||||
__release_perfctr_nmi(-1, wd->perfctr_msr);
|
||||
}
|
||||
|
||||
/* Note that these events don't tick when the CPU idles. This means
|
||||
@ -581,10 +645,10 @@ static int setup_p4_watchdog(void)
|
||||
cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
|
||||
}
|
||||
|
||||
if (!reserve_perfctr_nmi(perfctr_msr))
|
||||
if (!__reserve_perfctr_nmi(-1, perfctr_msr))
|
||||
goto fail;
|
||||
|
||||
if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
if (!__reserve_evntsel_nmi(-1, evntsel_msr))
|
||||
goto fail1;
|
||||
|
||||
evntsel = P4_ESCR_EVENT_SELECT(0x3F)
|
||||
@ -609,7 +673,7 @@ static int setup_p4_watchdog(void)
|
||||
wd->check_bit = 1ULL<<39;
|
||||
return 1;
|
||||
fail1:
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
__release_perfctr_nmi(-1, perfctr_msr);
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
@ -621,8 +685,8 @@ static void stop_p4_watchdog(void)
|
||||
wrmsr(wd->cccr_msr, 0, 0);
|
||||
wrmsr(wd->evntsel_msr, 0, 0);
|
||||
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
__release_evntsel_nmi(-1, wd->evntsel_msr);
|
||||
__release_perfctr_nmi(-1, wd->perfctr_msr);
|
||||
}
|
||||
|
||||
#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
|
||||
@ -650,10 +714,10 @@ static int setup_intel_arch_watchdog(void)
|
||||
perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
|
||||
evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
|
||||
|
||||
if (!reserve_perfctr_nmi(perfctr_msr))
|
||||
if (!__reserve_perfctr_nmi(-1, perfctr_msr))
|
||||
goto fail;
|
||||
|
||||
if (!reserve_evntsel_nmi(evntsel_msr))
|
||||
if (!__reserve_evntsel_nmi(-1, evntsel_msr))
|
||||
goto fail1;
|
||||
|
||||
wrmsrl(perfctr_msr, 0UL);
|
||||
@ -680,7 +744,7 @@ static int setup_intel_arch_watchdog(void)
|
||||
wd->check_bit = 1ULL << (eax.split.bit_width - 1);
|
||||
return 1;
|
||||
fail1:
|
||||
release_perfctr_nmi(perfctr_msr);
|
||||
__release_perfctr_nmi(-1, perfctr_msr);
|
||||
fail:
|
||||
return 0;
|
||||
}
|
||||
@ -704,8 +768,8 @@ static void stop_intel_arch_watchdog(void)
|
||||
|
||||
wrmsr(wd->evntsel_msr, 0, 0);
|
||||
|
||||
release_evntsel_nmi(wd->evntsel_msr);
|
||||
release_perfctr_nmi(wd->perfctr_msr);
|
||||
__release_evntsel_nmi(-1, wd->evntsel_msr);
|
||||
__release_perfctr_nmi(-1, wd->perfctr_msr);
|
||||
}
|
||||
|
||||
void setup_apic_nmi_watchdog(void *unused)
|
||||
|
||||
@ -75,6 +75,7 @@
|
||||
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
|
||||
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
|
||||
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
|
||||
#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */
|
||||
|
||||
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
|
||||
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
|
||||
|
||||
@ -275,6 +275,8 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
|
||||
#define MSR_K7_FID_VID_CTL 0xC0010041
|
||||
#define MSR_K7_FID_VID_STATUS 0xC0010042
|
||||
|
||||
#define MSR_K8_ENABLE_C1E 0xC0010055
|
||||
|
||||
/* extended feature register */
|
||||
#define MSR_EFER 0xc0000080
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user