forked from luck/tmp_suning_uos_patched
x86: remove long dead cyrix mtrr code
cyrix_arr_init was #if 0 all the way back to at least v2.6.12. This was the only place where arr3_protected was set to anything but zero. Eliminate this variable. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Harvey Harrison
Ingo Molnar
parent
e1adbcf106
commit
9a6b344ea9
@ -7,8 +7,6 @@
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#include <asm/processor-flags.h>
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#include "mtrr.h"
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int arr3_protected;
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static void
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cyrix_get_arr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type * type)
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@ -99,8 +97,6 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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case 4:
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return replace_reg;
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case 3:
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if (arr3_protected)
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break;
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case 2:
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case 1:
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case 0:
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@ -115,8 +111,6 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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} else {
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for (i = 0; i < 7; i++) {
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cyrix_get_arr(i, &lbase, &lsize, <ype);
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if ((i == 3) && arr3_protected)
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continue;
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if (lsize == 0)
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return i;
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}
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@ -260,107 +254,6 @@ static void cyrix_set_all(void)
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post_set();
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}
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#if 0
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/*
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* On Cyrix 6x86(MX) and M II the ARR3 is special: it has connection
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* with the SMM (System Management Mode) mode. So we need the following:
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* Check whether SMI_LOCK (CCR3 bit 0) is set
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* if it is set, write a warning message: ARR3 cannot be changed!
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* (it cannot be changed until the next processor reset)
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* if it is reset, then we can change it, set all the needed bits:
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* - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset)
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* - disable access to SMM memory (CCR1 bit 2 reset)
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* - disable SMM mode (CCR1 bit 1 reset)
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* - disable write protection of ARR3 (CCR6 bit 1 reset)
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* - (maybe) disable ARR3
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* Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set)
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*/
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static void __init
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cyrix_arr_init(void)
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{
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struct set_mtrr_context ctxt;
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unsigned char ccr[7];
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int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 };
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#ifdef CONFIG_SMP
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int i;
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#endif
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/* flush cache and enable MAPEN */
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set_mtrr_prepare_save(&ctxt);
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set_mtrr_cache_disable(&ctxt);
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/* Save all CCRs locally */
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ccr[0] = getCx86(CX86_CCR0);
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ccr[1] = getCx86(CX86_CCR1);
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ccr[2] = getCx86(CX86_CCR2);
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ccr[3] = ctxt.ccr3;
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ccr[4] = getCx86(CX86_CCR4);
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ccr[5] = getCx86(CX86_CCR5);
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ccr[6] = getCx86(CX86_CCR6);
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if (ccr[3] & 1) {
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ccrc[3] = 1;
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arr3_protected = 1;
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} else {
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/* Disable SMM mode (bit 1), access to SMM memory (bit 2) and
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* access to SMM memory through ARR3 (bit 7).
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*/
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if (ccr[1] & 0x80) {
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ccr[1] &= 0x7f;
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ccrc[1] |= 0x80;
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}
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if (ccr[1] & 0x04) {
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ccr[1] &= 0xfb;
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ccrc[1] |= 0x04;
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}
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if (ccr[1] & 0x02) {
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ccr[1] &= 0xfd;
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ccrc[1] |= 0x02;
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}
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arr3_protected = 0;
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if (ccr[6] & 0x02) {
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ccr[6] &= 0xfd;
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ccrc[6] = 1; /* Disable write protection of ARR3 */
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setCx86(CX86_CCR6, ccr[6]);
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}
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/* Disable ARR3. This is safe now that we disabled SMM. */
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/* cyrix_set_arr_up (3, 0, 0, 0, FALSE); */
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}
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/* If we changed CCR1 in memory, change it in the processor, too. */
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if (ccrc[1])
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setCx86(CX86_CCR1, ccr[1]);
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/* Enable ARR usage by the processor */
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if (!(ccr[5] & 0x20)) {
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ccr[5] |= 0x20;
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ccrc[5] = 1;
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setCx86(CX86_CCR5, ccr[5]);
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}
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#ifdef CONFIG_SMP
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for (i = 0; i < 7; i++)
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ccr_state[i] = ccr[i];
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for (i = 0; i < 8; i++)
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cyrix_get_arr(i,
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&arr_state[i].base, &arr_state[i].size,
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&arr_state[i].type);
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#endif
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set_mtrr_done(&ctxt); /* flush cache and disable MAPEN */
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if (ccrc[5])
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printk(KERN_INFO "mtrr: ARR usage was not enabled, enabled manually\n");
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if (ccrc[3])
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printk(KERN_INFO "mtrr: ARR3 cannot be changed\n");
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/*
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if ( ccrc[1] & 0x80) printk ("mtrr: SMM memory access through ARR3 disabled\n");
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if ( ccrc[1] & 0x04) printk ("mtrr: SMM memory access disabled\n");
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if ( ccrc[1] & 0x02) printk ("mtrr: SMM mode disabled\n");
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*/
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if (ccrc[6])
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printk(KERN_INFO "mtrr: ARR3 was write protected, unprotected\n");
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}
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#endif
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static struct mtrr_ops cyrix_mtrr_ops = {
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.vendor = X86_VENDOR_CYRIX,
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// .init = cyrix_arr_init,
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@ -59,12 +59,6 @@ struct mtrr_ops * mtrr_if = NULL;
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static void set_mtrr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type);
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#ifndef CONFIG_X86_64
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extern int arr3_protected;
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#else
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#define arr3_protected 0
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#endif
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void set_mtrr_ops(struct mtrr_ops * ops)
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{
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if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
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@ -513,12 +507,6 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
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printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
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goto out;
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}
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if (is_cpu(CYRIX) && !use_intel()) {
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if ((reg == 3) && arr3_protected) {
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printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n");
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goto out;
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}
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}
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mtrr_if->get(reg, &lbase, &lsize, <ype);
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if (lsize < 1) {
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printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
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