forked from luck/tmp_suning_uos_patched
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (75 commits) omap3: Fix OMAP35XX_REV macros omap: serial: fix non-empty uart fifo read abort omap3: Zoom2/3: Update hsmmc board config params omap3 : Enable TWL4030 Keypad for Zoom2 and Zoom3 boards omap3: id code detection 3525 vs 3515 omap3: rx51: Use wl1251 in SPI mode 3 omap3: zoom2/3: make MMC slot work again omap1: htcherald: Update defconfig to include mux support omap1: LCD_DMA: Use some define rather than a hexadecimal omap: header: remove unused data-type omap: arch/arm/plat-omap/devices.c - sort alphabetically omap: Correcting GPMC_CONFIG1_DEVICETYPE_NAND OMAP3: serial - allow platforms specify which UARTs to initialize omap3: cm-t35: add mux initialization OMAP4: Sync up omap4430 defconfig OMAP4: Remove the secondary wait loop OMAP4: AuxCoreBoot registers only accessible in secure mode OMAP4: Fix SRAM base and size OMAP4: Fix cpu detection omap3: pandora: board file updates for .33 ...
This commit is contained in:
commit
9c3936cb69
|
@ -1787,6 +1787,11 @@ and is between 256 and 4096 characters. It is defined in the file
|
|||
waiting for the ACK, so if this is set too high
|
||||
interrupts *may* be lost!
|
||||
|
||||
omap_mux= [OMAP] Override bootloader pin multiplexing.
|
||||
Format: <mux_mode0.mode_name=value>...
|
||||
For example, to override I2C bus2:
|
||||
omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100
|
||||
|
||||
opl3= [HW,OSS]
|
||||
Format: <io>
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.32-rc6
|
||||
# Sat Nov 14 10:56:01 2009
|
||||
# Linux kernel version: 2.6.32-rc8
|
||||
# Sat Dec 5 12:16:24 2009
|
||||
#
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
|
@ -198,7 +198,9 @@ CONFIG_ARCH_OMAP1=y
|
|||
# OMAP Feature Selections
|
||||
#
|
||||
# CONFIG_OMAP_RESET_CLOCKS is not set
|
||||
# CONFIG_OMAP_MUX is not set
|
||||
CONFIG_OMAP_MUX=y
|
||||
# CONFIG_OMAP_MUX_DEBUG is not set
|
||||
CONFIG_OMAP_MUX_WARNINGS=y
|
||||
CONFIG_OMAP_MCBSP=y
|
||||
# CONFIG_OMAP_MBOX_FWK is not set
|
||||
CONFIG_OMAP_MPU_TIMER=y
|
||||
|
@ -207,6 +209,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y
|
|||
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
|
||||
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
|
||||
# CONFIG_OMAP_LL_DEBUG_NONE is not set
|
||||
CONFIG_OMAP_SERIAL_WAKE=y
|
||||
# CONFIG_OMAP_PM_NONE is not set
|
||||
CONFIG_OMAP_PM_NOOP=y
|
||||
|
||||
|
|
2431
arch/arm/configs/omap3_touchbook_defconfig
Normal file
2431
arch/arm/configs/omap3_touchbook_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -1,26 +1,29 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.30-rc7
|
||||
# Tue Jun 9 12:36:23 2009
|
||||
# Linux kernel version: 2.6.32
|
||||
# Sun Dec 6 23:37:45 2009
|
||||
#
|
||||
CONFIG_ARM=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_LOCKDEP_SUPPORT=y
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_GENERIC_IRQ_PROBE=y
|
||||
CONFIG_GENERIC_LOCKBREAK=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
CONFIG_ARCH_HAS_CPUFREQ=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
CONFIG_CONSTRUCTORS=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
|
@ -39,11 +42,12 @@ CONFIG_BSD_PROCESS_ACCT=y
|
|||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
CONFIG_TREE_RCU=y
|
||||
# CONFIG_TREE_PREEMPT_RCU is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
CONFIG_RCU_FANOUT=32
|
||||
# CONFIG_RCU_FANOUT_EXACT is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_GROUP_SCHED=y
|
||||
|
@ -52,8 +56,7 @@ CONFIG_FAIR_GROUP_SCHED=y
|
|||
CONFIG_USER_SCHED=y
|
||||
# CONFIG_CGROUP_SCHED is not set
|
||||
# CONFIG_CGROUPS is not set
|
||||
# CONFIG_SYSFS_DEPRECATED=y is not set
|
||||
# CONFIG_SYSFS_DEPRECATED_V2=y is not set
|
||||
# CONFIG_SYSFS_DEPRECATED_V2 is not set
|
||||
# CONFIG_RELAY is not set
|
||||
# CONFIG_NAMESPACES is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
|
@ -70,7 +73,6 @@ CONFIG_UID16=y
|
|||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_ALL is not set
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
CONFIG_HOTPLUG=y
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
|
@ -83,6 +85,10 @@ CONFIG_TIMERFD=y
|
|||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
|
||||
#
|
||||
# Kernel Performance Events And Counters
|
||||
#
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_COMPAT_BRK=y
|
||||
|
@ -90,13 +96,16 @@ CONFIG_COMPAT_BRK=y
|
|||
CONFIG_SLUB=y
|
||||
# CONFIG_SLOB is not set
|
||||
# CONFIG_PROFILING is not set
|
||||
# CONFIG_MARKERS is not set
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
# CONFIG_KPROBES is not set
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_USE_GENERIC_SMP_HELPERS=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
#
|
||||
# CONFIG_SLOW_WORK is not set
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_SLABINFO=y
|
||||
|
@ -110,7 +119,7 @@ CONFIG_MODVERSIONS=y
|
|||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
CONFIG_STOP_MACHINE=y
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
CONFIG_LBDAF=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
|
@ -131,6 +140,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
|
|||
#
|
||||
# System Type
|
||||
#
|
||||
CONFIG_MMU=y
|
||||
# CONFIG_ARCH_AAEC2000 is not set
|
||||
# CONFIG_ARCH_INTEGRATOR is not set
|
||||
# CONFIG_ARCH_REALVIEW is not set
|
||||
|
@ -142,8 +152,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
|
|||
# CONFIG_ARCH_EP93XX is not set
|
||||
# CONFIG_ARCH_FOOTBRIDGE is not set
|
||||
# CONFIG_ARCH_MXC is not set
|
||||
# CONFIG_ARCH_STMP3XXX is not set
|
||||
# CONFIG_ARCH_NETX is not set
|
||||
# CONFIG_ARCH_H720X is not set
|
||||
# CONFIG_ARCH_NOMADIK is not set
|
||||
# CONFIG_ARCH_IOP13XX is not set
|
||||
# CONFIG_ARCH_IOP32X is not set
|
||||
# CONFIG_ARCH_IOP33X is not set
|
||||
|
@ -166,10 +178,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
|
|||
# CONFIG_ARCH_SA1100 is not set
|
||||
# CONFIG_ARCH_S3C2410 is not set
|
||||
# CONFIG_ARCH_S3C64XX is not set
|
||||
# CONFIG_ARCH_S5PC1XX is not set
|
||||
# CONFIG_ARCH_SHARK is not set
|
||||
# CONFIG_ARCH_LH7A40X is not set
|
||||
# CONFIG_ARCH_U300 is not set
|
||||
# CONFIG_ARCH_DAVINCI is not set
|
||||
CONFIG_ARCH_OMAP=y
|
||||
# CONFIG_ARCH_BCMRING is not set
|
||||
|
||||
#
|
||||
# TI OMAP Implementations
|
||||
|
@ -190,9 +205,12 @@ CONFIG_ARCH_OMAP4=y
|
|||
CONFIG_OMAP_32K_TIMER=y
|
||||
CONFIG_OMAP_32K_TIMER_HZ=128
|
||||
CONFIG_OMAP_DM_TIMER=y
|
||||
CONFIG_OMAP_LL_DEBUG_UART1=y
|
||||
# CONFIG_OMAP_LL_DEBUG_UART1 is not set
|
||||
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
|
||||
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
|
||||
CONFIG_OMAP_LL_DEBUG_UART3=y
|
||||
# CONFIG_OMAP_LL_DEBUG_NONE is not set
|
||||
# CONFIG_OMAP_PM_NONE is not set
|
||||
CONFIG_OMAP_PM_NOOP=y
|
||||
|
||||
#
|
||||
# OMAP Board Type
|
||||
|
@ -207,7 +225,7 @@ CONFIG_CPU_32v6K=y
|
|||
CONFIG_CPU_V7=y
|
||||
CONFIG_CPU_32v7=y
|
||||
CONFIG_CPU_ABRT_EV7=y
|
||||
CONFIG_CPU_PABRT_IFAR=y
|
||||
CONFIG_CPU_PABRT_V7=y
|
||||
CONFIG_CPU_CACHE_V7=y
|
||||
CONFIG_CPU_CACHE_VIPT=y
|
||||
CONFIG_CPU_COPY_V6=y
|
||||
|
@ -222,9 +240,10 @@ CONFIG_CPU_CP15_MMU=y
|
|||
# CONFIG_ARM_THUMB is not set
|
||||
# CONFIG_ARM_THUMBEE is not set
|
||||
# CONFIG_CPU_ICACHE_DISABLE is not set
|
||||
CONFIG_CPU_DCACHE_DISABLE=y
|
||||
# CONFIG_CPU_DCACHE_DISABLE is not set
|
||||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_HAS_TLS_REG=y
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=5
|
||||
# CONFIG_ARM_ERRATA_430973 is not set
|
||||
# CONFIG_ARM_ERRATA_458693 is not set
|
||||
# CONFIG_ARM_ERRATA_460075 is not set
|
||||
|
@ -245,18 +264,20 @@ CONFIG_ARM_GIC=y
|
|||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_HAVE_ARM_SCU=y
|
||||
CONFIG_HAVE_ARM_TWD=y
|
||||
CONFIG_VMSPLIT_3G=y
|
||||
# CONFIG_VMSPLIT_2G is not set
|
||||
# CONFIG_VMSPLIT_1G is not set
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
CONFIG_NR_CPUS=2
|
||||
# CONFIG_HOTPLUG_CPU is not set
|
||||
CONFIG_LOCAL_TIMERS=y
|
||||
# CONFIG_PREEMPT is not set
|
||||
# CONFIG_LOCAL_TIMERS is not set
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_HZ=128
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_OABI_COMPAT=y
|
||||
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
|
||||
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
|
||||
# CONFIG_HIGHMEM is not set
|
||||
|
@ -271,10 +292,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
|
|||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
# CONFIG_UNEVICTABLE_LRU is not set
|
||||
CONFIG_HAVE_MLOCK=y
|
||||
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
|
||||
# CONFIG_KSM is not set
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
# CONFIG_LEDS is not set
|
||||
CONFIG_ALIGNMENT_TRAP=y
|
||||
# CONFIG_UACCESS_WITH_MEMCPY is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
|
@ -298,9 +322,11 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600
|
|||
#
|
||||
# At least one emulation must be selected
|
||||
#
|
||||
# CONFIG_FPE_NWFPE is not set
|
||||
# CONFIG_FPE_FASTFPE is not set
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
# CONFIG_NEON is not set
|
||||
CONFIG_NEON=y
|
||||
|
||||
#
|
||||
# Userspace binary formats
|
||||
|
@ -325,6 +351,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
|||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_DEVTMPFS is not set
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
|
@ -342,6 +369,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16
|
|||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
# CONFIG_BLK_DEV_XIP is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_MG_DISK is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
@ -355,6 +383,7 @@ CONFIG_HAVE_IDE=y
|
|||
# CONFIG_SCSI_NETLINK is not set
|
||||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
|
@ -427,6 +456,11 @@ CONFIG_HW_RANDOM=y
|
|||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_I2C is not set
|
||||
# CONFIG_SPI is not set
|
||||
|
||||
#
|
||||
# PPS support
|
||||
#
|
||||
# CONFIG_PPS is not set
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
|
@ -447,11 +481,14 @@ CONFIG_GPIOLIB=y
|
|||
#
|
||||
# SPI GPIO expanders:
|
||||
#
|
||||
|
||||
#
|
||||
# AC97 GPIO expanders:
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_POWER_SUPPLY is not set
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_THERMAL is not set
|
||||
# CONFIG_THERMAL_HWMON is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
|
||||
|
@ -472,21 +509,8 @@ CONFIG_SSB_POSSIBLE=y
|
|||
# CONFIG_MFD_T7L66XB is not set
|
||||
# CONFIG_MFD_TC6387XB is not set
|
||||
# CONFIG_MFD_TC6393XB is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia core support
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
# CONFIG_VIDEO_MEDIA is not set
|
||||
|
||||
#
|
||||
# Multimedia drivers
|
||||
#
|
||||
CONFIG_DAB=y
|
||||
# CONFIG_REGULATOR is not set
|
||||
# CONFIG_MEDIA_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
|
@ -511,14 +535,17 @@ CONFIG_DUMMY_CONSOLE=y
|
|||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
# CONFIG_DMADEVICES is not set
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
# CONFIG_UIO is not set
|
||||
|
||||
#
|
||||
# TI VLYNQ
|
||||
#
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
#
|
||||
|
@ -535,9 +562,12 @@ CONFIG_JBD=y
|
|||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_BTRFS_FS is not set
|
||||
# CONFIG_NILFS2_FS is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_FSNOTIFY=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
|
@ -601,7 +631,6 @@ CONFIG_MISC_FILESYSTEMS=y
|
|||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
# CONFIG_NILFS2_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
|
@ -673,23 +702,24 @@ CONFIG_NLS_ISO8859_1=y
|
|||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_FRAME_WARN=1024
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
# CONFIG_DEBUG_SHIRQ is not set
|
||||
CONFIG_DETECT_SOFTLOCKUP=y
|
||||
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
|
||||
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
|
||||
# CONFIG_DETECT_SOFTLOCKUP is not set
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
|
||||
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
|
||||
CONFIG_SCHED_DEBUG=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_SCHEDSTATS is not set
|
||||
# CONFIG_TIMER_STATS is not set
|
||||
# CONFIG_DEBUG_OBJECTS is not set
|
||||
# CONFIG_SLUB_DEBUG_ON is not set
|
||||
# CONFIG_SLUB_STATS is not set
|
||||
# CONFIG_DEBUG_KMEMLEAK is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_DEBUG_RT_MUTEXES is not set
|
||||
# CONFIG_RT_MUTEX_TESTER is not set
|
||||
# CONFIG_DEBUG_SPINLOCK is not set
|
||||
|
@ -708,31 +738,22 @@ CONFIG_DEBUG_INFO=y
|
|||
# CONFIG_DEBUG_LIST is not set
|
||||
# CONFIG_DEBUG_SG is not set
|
||||
# CONFIG_DEBUG_NOTIFIERS is not set
|
||||
# CONFIG_DEBUG_CREDENTIALS is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
# CONFIG_BOOT_PRINTK_DELAY is not set
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
# CONFIG_BACKTRACE_SELF_TEST is not set
|
||||
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
|
||||
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
|
||||
# CONFIG_FAULT_INJECTION is not set
|
||||
# CONFIG_PAGE_POISONING is not set
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_TRACING_SUPPORT=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_FUNCTION_TRACER is not set
|
||||
# CONFIG_IRQSOFF_TRACER is not set
|
||||
# CONFIG_SCHED_TRACER is not set
|
||||
# CONFIG_CONTEXT_SWITCH_TRACER is not set
|
||||
# CONFIG_EVENT_TRACER is not set
|
||||
# CONFIG_BOOT_TRACER is not set
|
||||
# CONFIG_TRACE_BRANCH_PROFILING is not set
|
||||
# CONFIG_STACK_TRACER is not set
|
||||
# CONFIG_KMEMTRACE is not set
|
||||
# CONFIG_WORKQUEUE_TRACER is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_BRANCH_PROFILE_NONE is not set
|
||||
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
|
||||
# CONFIG_PROFILE_ALL_BRANCHES is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
# CONFIG_KGDB is not set
|
||||
|
@ -754,7 +775,6 @@ CONFIG_CRYPTO=y
|
|||
#
|
||||
# Crypto core or helper
|
||||
#
|
||||
# CONFIG_CRYPTO_FIPS is not set
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_ALGAPI2=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
|
@ -796,11 +816,13 @@ CONFIG_CRYPTO_PCBC=m
|
|||
#
|
||||
# CONFIG_CRYPTO_HMAC is not set
|
||||
# CONFIG_CRYPTO_XCBC is not set
|
||||
# CONFIG_CRYPTO_VMAC is not set
|
||||
|
||||
#
|
||||
# Digest
|
||||
#
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
# CONFIG_CRYPTO_GHASH is not set
|
||||
# CONFIG_CRYPTO_MD4 is not set
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
# CONFIG_CRYPTO_MICHAEL_MIC is not set
|
||||
|
|
|
@ -610,7 +610,8 @@ CONFIG_INPUT_EVDEV=y
|
|||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_KEYBOARD_TWL4030=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
|
|
|
@ -629,7 +629,8 @@ CONFIG_INPUT_EVDEV=y
|
|||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_KEYBOARD_TWL4030=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
|
|
|
@ -3,7 +3,8 @@
|
|||
#
|
||||
|
||||
# Common support
|
||||
obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
|
||||
obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o
|
||||
obj-y += clock.o clock_data.o opp_data.o
|
||||
|
||||
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
|
||||
|
||||
|
@ -17,6 +18,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o
|
|||
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
|
||||
mailbox_mach-objs := mailbox.o
|
||||
|
||||
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
|
||||
obj-y += $(i2c-omap-m) $(i2c-omap-y)
|
||||
|
||||
led-y := leds.o
|
||||
|
||||
# Specific board support
|
||||
|
@ -48,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o
|
|||
led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o
|
||||
led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o
|
||||
obj-$(CONFIG_LEDS) += $(led-y)
|
||||
|
||||
ifneq ($(CONFIG_FB_OMAP),)
|
||||
obj-y += lcd_dma.o
|
||||
endif
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -30,7 +31,6 @@
|
|||
#include <mach/gpio.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/fpga.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/board.h>
|
||||
|
@ -100,6 +100,12 @@ static int fsample_keymap[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
|
||||
|
@ -167,8 +173,40 @@ static struct platform_device nor_device = {
|
|||
.resource = &nor_resource,
|
||||
};
|
||||
|
||||
static struct omap_nand_platform_data nand_data = {
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long mask;
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
|
||||
if (ctrl & NAND_ALE)
|
||||
mask |= 0x04;
|
||||
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
|
||||
}
|
||||
|
||||
#define FSAMPLE_NAND_RB_GPIO_PIN 62
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static const char *part_probes[] = { "cmdlinepart", NULL };
|
||||
|
||||
static struct platform_nand_data nand_data = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.chip_offset = 0,
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
.part_probe_types = part_probes,
|
||||
},
|
||||
.ctrl = {
|
||||
.cmd_ctrl = nand_cmd_ctl,
|
||||
.dev_ready = nand_dev_ready,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource nand_resource = {
|
||||
|
@ -178,7 +216,7 @@ static struct resource nand_resource = {
|
|||
};
|
||||
|
||||
static struct platform_device nand_device = {
|
||||
.name = "omapnand",
|
||||
.name = "gen_nand",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &nand_data,
|
||||
|
@ -190,6 +228,9 @@ static struct platform_device nand_device = {
|
|||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
@ -233,13 +274,6 @@ static struct platform_device *devices[] __initdata = {
|
|||
&lcd_device,
|
||||
};
|
||||
|
||||
#define P2_NAND_RB_GPIO_PIN 62
|
||||
|
||||
static int nand_dev_ready(struct omap_nand_platform_data *data)
|
||||
{
|
||||
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static struct omap_lcd_config fsample_lcd_config __initdata = {
|
||||
.ctrl_name = "internal",
|
||||
};
|
||||
|
@ -250,9 +284,9 @@ static struct omap_board_config_kernel fsample_config[] = {
|
|||
|
||||
static void __init omap_fsample_init(void)
|
||||
{
|
||||
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
|
||||
if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
|
||||
BUG();
|
||||
nand_data.dev_ready = nand_dev_ready;
|
||||
gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
|
||||
|
||||
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
|
||||
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c/tps65010.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/gpio.h>
|
||||
|
@ -40,7 +41,6 @@
|
|||
#include <plat/mux.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/tc.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/irda.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/keypad.h>
|
||||
|
@ -179,11 +179,43 @@ static struct mtd_partition h2_nand_partitions[] = {
|
|||
},
|
||||
};
|
||||
|
||||
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
|
||||
static struct omap_nand_platform_data h2_nand_data = {
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
.parts = h2_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(h2_nand_partitions),
|
||||
static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long mask;
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
|
||||
if (ctrl & NAND_ALE)
|
||||
mask |= 0x04;
|
||||
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
|
||||
}
|
||||
|
||||
#define H2_NAND_RB_GPIO_PIN 62
|
||||
|
||||
static int h2_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return gpio_get_value(H2_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static const char *h2_part_probes[] = { "cmdlinepart", NULL };
|
||||
|
||||
struct platform_nand_data h2_nand_platdata = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.chip_offset = 0,
|
||||
.nr_partitions = ARRAY_SIZE(h2_nand_partitions),
|
||||
.partitions = h2_nand_partitions,
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
.part_probe_types = h2_part_probes,
|
||||
},
|
||||
.ctrl = {
|
||||
.cmd_ctrl = h2_nand_cmd_ctl,
|
||||
.dev_ready = h2_nand_dev_ready,
|
||||
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource h2_nand_resource = {
|
||||
|
@ -191,15 +223,21 @@ static struct resource h2_nand_resource = {
|
|||
};
|
||||
|
||||
static struct platform_device h2_nand_device = {
|
||||
.name = "omapnand",
|
||||
.name = "gen_nand",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &h2_nand_data,
|
||||
.platform_data = &h2_nand_platdata,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &h2_nand_resource,
|
||||
};
|
||||
|
||||
static struct smc91x_platdata h2_smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource h2_smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = OMAP1610_ETHR_START, /* Physical */
|
||||
|
@ -216,6 +254,9 @@ static struct resource h2_smc91x_resources[] = {
|
|||
static struct platform_device h2_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &h2_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(h2_smc91x_resources),
|
||||
.resource = h2_smc91x_resources,
|
||||
};
|
||||
|
@ -368,8 +409,6 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
|
|||
{ OMAP_TAG_LCD, &h2_lcd_config },
|
||||
};
|
||||
|
||||
#define H2_NAND_RB_GPIO_PIN 62
|
||||
|
||||
static void __init h2_init(void)
|
||||
{
|
||||
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/input.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/i2c/tps65010.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/page.h>
|
||||
|
@ -42,7 +43,6 @@
|
|||
#include <mach/irqs.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/tc.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/dma.h>
|
||||
|
@ -181,11 +181,43 @@ static struct mtd_partition nand_partitions[] = {
|
|||
},
|
||||
};
|
||||
|
||||
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
|
||||
static struct omap_nand_platform_data nand_data = {
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
.parts = nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(nand_partitions),
|
||||
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long mask;
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
|
||||
if (ctrl & NAND_ALE)
|
||||
mask |= 0x04;
|
||||
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
|
||||
}
|
||||
|
||||
#define H3_NAND_RB_GPIO_PIN 10
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return gpio_get_value(H3_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static const char *part_probes[] = { "cmdlinepart", NULL };
|
||||
|
||||
struct platform_nand_data nand_platdata = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.chip_offset = 0,
|
||||
.nr_partitions = ARRAY_SIZE(nand_partitions),
|
||||
.partitions = nand_partitions,
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
.part_probe_types = part_probes,
|
||||
},
|
||||
.ctrl = {
|
||||
.cmd_ctrl = nand_cmd_ctl,
|
||||
.dev_ready = nand_dev_ready,
|
||||
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource nand_resource = {
|
||||
|
@ -193,15 +225,21 @@ static struct resource nand_resource = {
|
|||
};
|
||||
|
||||
static struct platform_device nand_device = {
|
||||
.name = "omapnand",
|
||||
.name = "gen_nand",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &nand_data,
|
||||
.platform_data = &nand_platdata,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &nand_resource,
|
||||
};
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = OMAP1710_ETHR_START, /* Physical */
|
||||
|
@ -218,6 +256,9 @@ static struct resource smc91x_resources[] = {
|
|||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
@ -332,13 +373,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
|
|||
},
|
||||
};
|
||||
|
||||
#define H3_NAND_RB_GPIO_PIN 10
|
||||
|
||||
static int nand_dev_ready(struct omap_nand_platform_data *data)
|
||||
{
|
||||
return gpio_get_value(H3_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static void __init h3_init(void)
|
||||
{
|
||||
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
|
||||
|
@ -356,7 +390,7 @@ static void __init h3_init(void)
|
|||
nand_resource.end += SZ_4K - 1;
|
||||
if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
|
||||
BUG();
|
||||
nand_data.dev_ready = nand_dev_ready;
|
||||
gpio_direction_input(H3_NAND_RB_GPIO_PIN);
|
||||
|
||||
/* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
|
||||
/* GPIO10 pullup/down register, Enable pullup on GPIO10 */
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <plat/common.h>
|
||||
#include <plat/board.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
|
@ -140,6 +141,15 @@ static struct platform_device kp_device = {
|
|||
.resource = kp_resources,
|
||||
};
|
||||
|
||||
/* USB Device */
|
||||
static struct omap_usb_config htcherald_usb_config __initdata = {
|
||||
.otg = 0,
|
||||
.register_host = 0,
|
||||
.register_dev = 1,
|
||||
.hmc_mode = 4,
|
||||
.pins[0] = 2,
|
||||
};
|
||||
|
||||
/* LCD Device resources */
|
||||
static struct platform_device lcd_device = {
|
||||
.name = "lcd_htcherald",
|
||||
|
@ -214,6 +224,57 @@ static void __init htcherald_disable_watchdog(void)
|
|||
}
|
||||
}
|
||||
|
||||
#define HTCHERALD_GPIO_USB_EN1 33
|
||||
#define HTCHERALD_GPIO_USB_EN2 73
|
||||
#define HTCHERALD_GPIO_USB_DM 35
|
||||
#define HTCHERALD_GPIO_USB_DP 36
|
||||
|
||||
static void __init htcherald_usb_enable(void)
|
||||
{
|
||||
unsigned int tries = 20;
|
||||
unsigned int value = 0;
|
||||
|
||||
/* Request the GPIOs we need to control here */
|
||||
if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0)
|
||||
goto err1;
|
||||
|
||||
if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0)
|
||||
goto err2;
|
||||
|
||||
if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0)
|
||||
goto err3;
|
||||
|
||||
if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0)
|
||||
goto err4;
|
||||
|
||||
/* force USB_EN GPIO to 0 */
|
||||
do {
|
||||
/* output low */
|
||||
gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0);
|
||||
} while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 &&
|
||||
--tries);
|
||||
|
||||
if (value == 1)
|
||||
printk(KERN_WARNING "Unable to reset USB, trying to continue\n");
|
||||
|
||||
gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */
|
||||
gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */
|
||||
gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */
|
||||
|
||||
goto done;
|
||||
|
||||
err4:
|
||||
gpio_free(HTCHERALD_GPIO_USB_DM);
|
||||
err3:
|
||||
gpio_free(HTCHERALD_GPIO_USB_EN2);
|
||||
err2:
|
||||
gpio_free(HTCHERALD_GPIO_USB_EN1);
|
||||
err1:
|
||||
printk(KERN_ERR "Unabled to request GPIO for USB\n");
|
||||
done:
|
||||
printk(KERN_INFO "USB setup complete.\n");
|
||||
}
|
||||
|
||||
static void __init htcherald_init(void)
|
||||
{
|
||||
printk(KERN_INFO "HTC Herald init.\n");
|
||||
|
@ -225,6 +286,9 @@ static void __init htcherald_init(void)
|
|||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
||||
htcherald_disable_watchdog();
|
||||
|
||||
htcherald_usb_enable();
|
||||
omap_usb_init(&htcherald_usb_config);
|
||||
}
|
||||
|
||||
static void __init htcherald_init_irq(void)
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -142,6 +143,11 @@ static struct platform_device innovator_kp_device = {
|
|||
.resource = innovator_kp_resources,
|
||||
};
|
||||
|
||||
static struct smc91x_platdata innovator_smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP15XX
|
||||
|
||||
|
@ -175,6 +181,9 @@ static struct resource innovator1510_smc91x_resources[] = {
|
|||
static struct platform_device innovator1510_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &innovator_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(innovator1510_smc91x_resources),
|
||||
.resource = innovator1510_smc91x_resources,
|
||||
};
|
||||
|
@ -241,6 +250,9 @@ static struct resource innovator1610_smc91x_resources[] = {
|
|||
static struct platform_device innovator1610_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &innovator_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(innovator1610_smc91x_resources),
|
||||
.resource = innovator1610_smc91x_resources,
|
||||
};
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
@ -115,6 +116,12 @@ static struct platform_device osk5912_flash_device = {
|
|||
.resource = &osk_flash_resource,
|
||||
};
|
||||
|
||||
static struct smc91x_platdata osk5912_smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource osk5912_smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = OMAP_OSK_ETHR_START, /* Physical */
|
||||
|
@ -131,6 +138,9 @@ static struct resource osk5912_smc91x_resources[] = {
|
|||
static struct platform_device osk5912_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &osk5912_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(osk5912_smc91x_resources),
|
||||
.resource = osk5912_smc91x_resources,
|
||||
};
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -30,7 +31,6 @@
|
|||
#include <mach/gpio.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/fpga.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/board.h>
|
||||
|
@ -67,6 +67,12 @@ static int p2_keymap[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
|
||||
|
@ -134,8 +140,40 @@ static struct platform_device nor_device = {
|
|||
.resource = &nor_resource,
|
||||
};
|
||||
|
||||
static struct omap_nand_platform_data nand_data = {
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long mask;
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
|
||||
if (ctrl & NAND_ALE)
|
||||
mask |= 0x04;
|
||||
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
|
||||
}
|
||||
|
||||
#define P2_NAND_RB_GPIO_PIN 62
|
||||
|
||||
static int nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static const char *part_probes[] = { "cmdlinepart", NULL };
|
||||
|
||||
static struct platform_nand_data nand_data = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.chip_offset = 0,
|
||||
.options = NAND_SAMSUNG_LP_OPTIONS,
|
||||
.part_probe_types = part_probes,
|
||||
},
|
||||
.ctrl = {
|
||||
.cmd_ctrl = nand_cmd_ctl,
|
||||
.dev_ready = nand_dev_ready,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource nand_resource = {
|
||||
|
@ -145,7 +183,7 @@ static struct resource nand_resource = {
|
|||
};
|
||||
|
||||
static struct platform_device nand_device = {
|
||||
.name = "omapnand",
|
||||
.name = "gen_nand",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &nand_data,
|
||||
|
@ -157,6 +195,9 @@ static struct platform_device nand_device = {
|
|||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
@ -201,13 +242,6 @@ static struct platform_device *devices[] __initdata = {
|
|||
&lcd_device,
|
||||
};
|
||||
|
||||
#define P2_NAND_RB_GPIO_PIN 62
|
||||
|
||||
static int nand_dev_ready(struct omap_nand_platform_data *data)
|
||||
{
|
||||
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
|
||||
}
|
||||
|
||||
static struct omap_lcd_config perseus2_lcd_config __initdata = {
|
||||
.ctrl_name = "internal",
|
||||
};
|
||||
|
@ -220,7 +254,7 @@ static void __init omap_perseus2_init(void)
|
|||
{
|
||||
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
|
||||
BUG();
|
||||
nand_data.dev_ready = nand_dev_ready;
|
||||
gpio_direction_input(P2_NAND_RB_GPIO_PIN);
|
||||
|
||||
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
|
||||
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/reboot.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -106,6 +107,12 @@ static struct platform_device voiceblue_flash_device = {
|
|||
.resource = &voiceblue_flash_resource,
|
||||
};
|
||||
|
||||
static struct smc91x_platdata voiceblue_smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource voiceblue_smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = OMAP_CS2_PHYS + 0x300,
|
||||
|
@ -122,6 +129,9 @@ static struct resource voiceblue_smc91x_resources[] = {
|
|||
static struct platform_device voiceblue_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &voiceblue_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(voiceblue_smc91x_resources),
|
||||
.resource = voiceblue_smc91x_resources,
|
||||
};
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/clock.c
|
||||
*
|
||||
* Copyright (C) 2004 - 2005 Nokia corporation
|
||||
* Copyright (C) 2004 - 2005, 2009 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
*
|
||||
* Modified to use omap shared clock framework by
|
||||
|
@ -26,12 +26,17 @@
|
|||
#include <plat/usb.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/sram.h>
|
||||
|
||||
static const struct clkops clkops_generic;
|
||||
static const struct clkops clkops_uart;
|
||||
static const struct clkops clkops_dspck;
|
||||
#include <plat/clkdev_omap.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "opp.h"
|
||||
|
||||
__u32 arm_idlect1_mask;
|
||||
struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap1 specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
static int clk_omap1_dummy_enable(struct clk *clk)
|
||||
{
|
||||
|
@ -42,134 +47,24 @@ static void clk_omap1_dummy_disable(struct clk *clk)
|
|||
{
|
||||
}
|
||||
|
||||
static const struct clkops clkops_dummy = {
|
||||
.enable = clk_omap1_dummy_enable,
|
||||
.disable = clk_omap1_dummy_disable,
|
||||
const struct clkops clkops_dummy = {
|
||||
.enable = clk_omap1_dummy_enable,
|
||||
.disable = clk_omap1_dummy_disable,
|
||||
};
|
||||
|
||||
static struct clk dummy_ck = {
|
||||
.name = "dummy",
|
||||
.ops = &clkops_dummy,
|
||||
.flags = RATE_FIXED,
|
||||
};
|
||||
|
||||
struct omap_clk {
|
||||
u32 cpu;
|
||||
struct clk_lookup lk;
|
||||
};
|
||||
|
||||
#define CLK(dev, con, ck, cp) \
|
||||
{ \
|
||||
.cpu = cp, \
|
||||
.lk = { \
|
||||
.dev_id = dev, \
|
||||
.con_id = con, \
|
||||
.clk = ck, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define CK_310 (1 << 0)
|
||||
#define CK_7XX (1 << 1)
|
||||
#define CK_1510 (1 << 2)
|
||||
#define CK_16XX (1 << 3)
|
||||
|
||||
static struct omap_clk omap_clks[] = {
|
||||
/* non-ULPD clocks */
|
||||
CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
|
||||
/* CK_GEN1 clocks */
|
||||
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
|
||||
CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
|
||||
CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
|
||||
/* CK_GEN2 clocks */
|
||||
CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
|
||||
/* CK_GEN3 clocks */
|
||||
CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
|
||||
CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
|
||||
CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
|
||||
CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
|
||||
CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
|
||||
CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
|
||||
/* ULPD clocks */
|
||||
CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
|
||||
CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
|
||||
CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
|
||||
CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
|
||||
CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
|
||||
CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
|
||||
CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
|
||||
CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
|
||||
/* Virtual clocks */
|
||||
CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
|
||||
CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
|
||||
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
|
||||
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
};
|
||||
|
||||
static int omap1_clk_enable_generic(struct clk * clk);
|
||||
static int omap1_clk_enable(struct clk *clk);
|
||||
static void omap1_clk_disable_generic(struct clk * clk);
|
||||
static void omap1_clk_disable(struct clk *clk);
|
||||
|
||||
__u32 arm_idlect1_mask;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap1 specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
static unsigned long omap1_watchdog_recalc(struct clk *clk)
|
||||
/* XXX can be replaced with a fixed_divisor_recalc */
|
||||
unsigned long omap1_watchdog_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 14;
|
||||
}
|
||||
|
||||
static unsigned long omap1_uart_recalc(struct clk *clk)
|
||||
unsigned long omap1_uart_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned int val = __raw_readl(clk->enable_reg);
|
||||
return val & clk->enable_bit ? 48000000 : 12000000;
|
||||
}
|
||||
|
||||
static unsigned long omap1_sossi_recalc(struct clk *clk)
|
||||
unsigned long omap1_sossi_recalc(struct clk *clk)
|
||||
{
|
||||
u32 div = omap_readl(MOD_CONF_CTRL_1);
|
||||
|
||||
|
@ -179,64 +74,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk)
|
|||
return clk->parent->rate / div;
|
||||
}
|
||||
|
||||
static int omap1_clk_enable_dsp_domain(struct clk *clk)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = omap1_clk_enable(&api_ck.clk);
|
||||
if (!retval) {
|
||||
retval = omap1_clk_enable_generic(clk);
|
||||
omap1_clk_disable(&api_ck.clk);
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void omap1_clk_disable_dsp_domain(struct clk *clk)
|
||||
{
|
||||
if (omap1_clk_enable(&api_ck.clk) == 0) {
|
||||
omap1_clk_disable_generic(clk);
|
||||
omap1_clk_disable(&api_ck.clk);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct clkops clkops_dspck = {
|
||||
.enable = &omap1_clk_enable_dsp_domain,
|
||||
.disable = &omap1_clk_disable_dsp_domain,
|
||||
};
|
||||
|
||||
static int omap1_clk_enable_uart_functional(struct clk *clk)
|
||||
{
|
||||
int ret;
|
||||
struct uart_clk *uclk;
|
||||
|
||||
ret = omap1_clk_enable_generic(clk);
|
||||
if (ret == 0) {
|
||||
/* Set smart idle acknowledgement mode */
|
||||
uclk = (struct uart_clk *)clk;
|
||||
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
|
||||
uclk->sysc_addr);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void omap1_clk_disable_uart_functional(struct clk *clk)
|
||||
{
|
||||
struct uart_clk *uclk;
|
||||
|
||||
/* Set force idle acknowledgement mode */
|
||||
uclk = (struct uart_clk *)clk;
|
||||
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
|
||||
|
||||
omap1_clk_disable_generic(clk);
|
||||
}
|
||||
|
||||
static const struct clkops clkops_uart = {
|
||||
.enable = &omap1_clk_enable_uart_functional,
|
||||
.disable = &omap1_clk_disable_uart_functional,
|
||||
};
|
||||
|
||||
static void omap1_clk_allow_idle(struct clk *clk)
|
||||
{
|
||||
struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
|
||||
|
@ -344,7 +181,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
|
|||
return dsor_exp;
|
||||
}
|
||||
|
||||
static unsigned long omap1_ckctl_recalc(struct clk *clk)
|
||||
unsigned long omap1_ckctl_recalc(struct clk *clk)
|
||||
{
|
||||
/* Calculate divisor encoded as 2-bit exponent */
|
||||
int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
|
||||
|
@ -352,7 +189,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk)
|
|||
return clk->parent->rate / dsor;
|
||||
}
|
||||
|
||||
static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
|
||||
unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
|
||||
{
|
||||
int dsor;
|
||||
|
||||
|
@ -363,28 +200,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
|
|||
* Note that DSP_CKCTL virt addr = phys addr, so
|
||||
* we must use __raw_readw() instead of omap_readw().
|
||||
*/
|
||||
omap1_clk_enable(&api_ck.clk);
|
||||
omap1_clk_enable(api_ck_p);
|
||||
dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
|
||||
omap1_clk_disable(&api_ck.clk);
|
||||
omap1_clk_disable(api_ck_p);
|
||||
|
||||
return clk->parent->rate / dsor;
|
||||
}
|
||||
|
||||
/* MPU virtual clock functions */
|
||||
static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
|
||||
int omap1_select_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
/* Find the highest supported frequency <= rate and switch to it */
|
||||
struct mpu_rate * ptr;
|
||||
unsigned long dpll1_rate, ref_rate;
|
||||
|
||||
if (clk != &virtual_ck_mpu)
|
||||
return -EINVAL;
|
||||
dpll1_rate = clk_get_rate(ck_dpll1_p);
|
||||
ref_rate = clk_get_rate(ck_ref_p);
|
||||
|
||||
for (ptr = rate_table; ptr->rate; ptr++) {
|
||||
if (ptr->xtal != ck_ref.rate)
|
||||
for (ptr = omap1_rate_table; ptr->rate; ptr++) {
|
||||
if (ptr->xtal != ref_rate)
|
||||
continue;
|
||||
|
||||
/* DPLL1 cannot be reprogrammed without risking system crash */
|
||||
if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
|
||||
if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
|
||||
continue;
|
||||
|
||||
/* Can check only after xtal frequency check */
|
||||
|
@ -405,11 +243,13 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
|
|||
else
|
||||
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
|
||||
|
||||
ck_dpll1.rate = ptr->pll_rate;
|
||||
/* XXX Do we need to recalculate the tree below DPLL1 at this point? */
|
||||
ck_dpll1_p->rate = ptr->pll_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
|
||||
int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int dsor_exp;
|
||||
u16 regval;
|
||||
|
@ -429,7 +269,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
|
||||
long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int dsor_exp = calc_dsor_exp(clk, rate);
|
||||
if (dsor_exp < 0)
|
||||
|
@ -439,7 +279,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
|
|||
return clk->parent->rate / (1 << dsor_exp);
|
||||
}
|
||||
|
||||
static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
|
||||
int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int dsor_exp;
|
||||
u16 regval;
|
||||
|
@ -459,19 +299,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
|
||||
long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
/* Find the highest supported frequency <= rate */
|
||||
struct mpu_rate * ptr;
|
||||
long highest_rate;
|
||||
long highest_rate;
|
||||
unsigned long ref_rate;
|
||||
|
||||
if (clk != &virtual_ck_mpu)
|
||||
return -EINVAL;
|
||||
ref_rate = clk_get_rate(ck_ref_p);
|
||||
|
||||
highest_rate = -EINVAL;
|
||||
|
||||
for (ptr = rate_table; ptr->rate; ptr++) {
|
||||
if (ptr->xtal != ck_ref.rate)
|
||||
for (ptr = omap1_rate_table; ptr->rate; ptr++) {
|
||||
if (ptr->xtal != ref_rate)
|
||||
continue;
|
||||
|
||||
highest_rate = ptr->rate;
|
||||
|
@ -506,8 +346,8 @@ static unsigned calc_ext_dsor(unsigned long rate)
|
|||
return dsor;
|
||||
}
|
||||
|
||||
/* Only needed on 1510 */
|
||||
static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
|
||||
/* XXX Only needed on 1510 */
|
||||
int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
|
@ -525,7 +365,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
|
|||
}
|
||||
|
||||
/* External clock (MCLK & BCLK) functions */
|
||||
static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
|
||||
int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned dsor;
|
||||
__u16 ratio_bits;
|
||||
|
@ -543,7 +383,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
|
||||
int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 l;
|
||||
int div;
|
||||
|
@ -566,12 +406,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
|
||||
long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
return 96000000 / calc_ext_dsor(rate);
|
||||
}
|
||||
|
||||
static void omap1_init_ext_clk(struct clk * clk)
|
||||
void omap1_init_ext_clk(struct clk *clk)
|
||||
{
|
||||
unsigned dsor;
|
||||
__u16 ratio_bits;
|
||||
|
@ -589,7 +429,7 @@ static void omap1_init_ext_clk(struct clk * clk)
|
|||
clk-> rate = 96000000 / dsor;
|
||||
}
|
||||
|
||||
static int omap1_clk_enable(struct clk *clk)
|
||||
int omap1_clk_enable(struct clk *clk)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
|
@ -617,7 +457,7 @@ static int omap1_clk_enable(struct clk *clk)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void omap1_clk_disable(struct clk *clk)
|
||||
void omap1_clk_disable(struct clk *clk)
|
||||
{
|
||||
if (clk->usecount > 0 && !(--clk->usecount)) {
|
||||
clk->ops->disable(clk);
|
||||
|
@ -672,12 +512,70 @@ static void omap1_clk_disable_generic(struct clk *clk)
|
|||
}
|
||||
}
|
||||
|
||||
static const struct clkops clkops_generic = {
|
||||
.enable = &omap1_clk_enable_generic,
|
||||
.disable = &omap1_clk_disable_generic,
|
||||
const struct clkops clkops_generic = {
|
||||
.enable = omap1_clk_enable_generic,
|
||||
.disable = omap1_clk_disable_generic,
|
||||
};
|
||||
|
||||
static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
static int omap1_clk_enable_dsp_domain(struct clk *clk)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = omap1_clk_enable(api_ck_p);
|
||||
if (!retval) {
|
||||
retval = omap1_clk_enable_generic(clk);
|
||||
omap1_clk_disable(api_ck_p);
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void omap1_clk_disable_dsp_domain(struct clk *clk)
|
||||
{
|
||||
if (omap1_clk_enable(api_ck_p) == 0) {
|
||||
omap1_clk_disable_generic(clk);
|
||||
omap1_clk_disable(api_ck_p);
|
||||
}
|
||||
}
|
||||
|
||||
const struct clkops clkops_dspck = {
|
||||
.enable = omap1_clk_enable_dsp_domain,
|
||||
.disable = omap1_clk_disable_dsp_domain,
|
||||
};
|
||||
|
||||
static int omap1_clk_enable_uart_functional(struct clk *clk)
|
||||
{
|
||||
int ret;
|
||||
struct uart_clk *uclk;
|
||||
|
||||
ret = omap1_clk_enable_generic(clk);
|
||||
if (ret == 0) {
|
||||
/* Set smart idle acknowledgement mode */
|
||||
uclk = (struct uart_clk *)clk;
|
||||
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
|
||||
uclk->sysc_addr);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void omap1_clk_disable_uart_functional(struct clk *clk)
|
||||
{
|
||||
struct uart_clk *uclk;
|
||||
|
||||
/* Set force idle acknowledgement mode */
|
||||
uclk = (struct uart_clk *)clk;
|
||||
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
|
||||
|
||||
omap1_clk_disable_generic(clk);
|
||||
}
|
||||
|
||||
const struct clkops clkops_uart = {
|
||||
.enable = omap1_clk_enable_uart_functional,
|
||||
.disable = omap1_clk_disable_uart_functional,
|
||||
};
|
||||
|
||||
long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (clk->flags & RATE_FIXED)
|
||||
return clk->rate;
|
||||
|
@ -688,7 +586,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
|
|||
return clk->rate;
|
||||
}
|
||||
|
||||
static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
|
@ -703,7 +601,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
|
|||
|
||||
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
||||
|
||||
static void __init omap1_clk_disable_unused(struct clk *clk)
|
||||
void __init omap1_clk_disable_unused(struct clk *clk)
|
||||
{
|
||||
__u32 regval32;
|
||||
|
||||
|
@ -724,184 +622,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
|
|||
if ((regval32 & (1 << clk->enable_bit)) == 0)
|
||||
return;
|
||||
|
||||
/* FIXME: This clock seems to be necessary but no-one
|
||||
* has asked for its activation. */
|
||||
if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
|
||||
|| clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
|
||||
|| clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
|
||||
) {
|
||||
printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
|
||||
clk->name);
|
||||
return;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
|
||||
clk->ops->disable(clk);
|
||||
printk(" done\n");
|
||||
}
|
||||
|
||||
#else
|
||||
#define omap1_clk_disable_unused NULL
|
||||
#endif
|
||||
|
||||
static struct clk_functions omap1_clk_functions = {
|
||||
.clk_enable = omap1_clk_enable,
|
||||
.clk_disable = omap1_clk_disable,
|
||||
.clk_round_rate = omap1_clk_round_rate,
|
||||
.clk_set_rate = omap1_clk_set_rate,
|
||||
.clk_disable_unused = omap1_clk_disable_unused,
|
||||
};
|
||||
|
||||
int __init omap1_clk_init(void)
|
||||
{
|
||||
struct omap_clk *c;
|
||||
const struct omap_clock_config *info;
|
||||
int crystal_type = 0; /* Default 12 MHz */
|
||||
u32 reg, cpu_mask;
|
||||
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
/* Resets some clocks that may be left on from bootloader,
|
||||
* but leaves serial clocks on.
|
||||
*/
|
||||
omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
|
||||
#endif
|
||||
|
||||
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
|
||||
reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
|
||||
omap_writew(reg, SOFT_REQ_REG);
|
||||
if (!cpu_is_omap15xx())
|
||||
omap_writew(0, SOFT_REQ_REG2);
|
||||
|
||||
clk_init(&omap1_clk_functions);
|
||||
|
||||
/* By default all idlect1 clocks are allowed to idle */
|
||||
arm_idlect1_mask = ~0;
|
||||
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
|
||||
clk_preinit(c->lk.clk);
|
||||
|
||||
cpu_mask = 0;
|
||||
if (cpu_is_omap16xx())
|
||||
cpu_mask |= CK_16XX;
|
||||
if (cpu_is_omap1510())
|
||||
cpu_mask |= CK_1510;
|
||||
if (cpu_is_omap7xx())
|
||||
cpu_mask |= CK_7XX;
|
||||
if (cpu_is_omap310())
|
||||
cpu_mask |= CK_310;
|
||||
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
|
||||
if (c->cpu & cpu_mask) {
|
||||
clkdev_add(&c->lk);
|
||||
clk_register(c->lk.clk);
|
||||
}
|
||||
|
||||
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
|
||||
if (info != NULL) {
|
||||
if (!cpu_is_omap15xx())
|
||||
crystal_type = info->system_clock_type;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
||||
ck_ref.rate = 13000000;
|
||||
#elif defined(CONFIG_ARCH_OMAP16XX)
|
||||
if (crystal_type == 2)
|
||||
ck_ref.rate = 19200000;
|
||||
#endif
|
||||
|
||||
printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
|
||||
omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
|
||||
omap_readw(ARM_CKCTL));
|
||||
|
||||
/* We want to be in syncronous scalable mode */
|
||||
omap_writew(0x1000, ARM_SYSST);
|
||||
|
||||
#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
|
||||
/* Use values set by bootloader. Determine PLL rate and recalculate
|
||||
* dependent clocks as if kernel had changed PLL or divisors.
|
||||
*/
|
||||
{
|
||||
unsigned pll_ctl_val = omap_readw(DPLL_CTL);
|
||||
|
||||
ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
|
||||
if (pll_ctl_val & 0x10) {
|
||||
/* PLL enabled, apply multiplier and divisor */
|
||||
if (pll_ctl_val & 0xf80)
|
||||
ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
|
||||
ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
|
||||
} else {
|
||||
/* PLL disabled, apply bypass divisor */
|
||||
switch (pll_ctl_val & 0xc) {
|
||||
case 0:
|
||||
break;
|
||||
case 0x4:
|
||||
ck_dpll1.rate /= 2;
|
||||
break;
|
||||
default:
|
||||
ck_dpll1.rate /= 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
/* Find the highest supported frequency and enable it */
|
||||
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
|
||||
printk(KERN_ERR "System frequencies not set. Check your config.\n");
|
||||
/* Guess sane values (60MHz) */
|
||||
omap_writew(0x2290, DPLL_CTL);
|
||||
omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
|
||||
ck_dpll1.rate = 60000000;
|
||||
}
|
||||
#endif
|
||||
propagate_rate(&ck_dpll1);
|
||||
/* Cache rates for clocks connected to ck_ref (not dpll1) */
|
||||
propagate_rate(&ck_ref);
|
||||
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
|
||||
"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
|
||||
ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
|
||||
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
|
||||
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
|
||||
|
||||
#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
|
||||
/* Select slicer output as OMAP input clock */
|
||||
omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
|
||||
#endif
|
||||
|
||||
/* Amstrad Delta wants BCLK high when inactive */
|
||||
if (machine_is_ams_delta())
|
||||
omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
|
||||
(1 << SDW_MCLK_INV_BIT),
|
||||
ULPD_CLOCK_CTRL);
|
||||
|
||||
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
|
||||
/* (on 730, bit 13 must not be cleared) */
|
||||
if (cpu_is_omap7xx())
|
||||
omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
|
||||
else
|
||||
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
|
||||
|
||||
/* Put DSP/MPUI into reset until needed */
|
||||
omap_writew(0, ARM_RSTCT1);
|
||||
omap_writew(1, ARM_RSTCT2);
|
||||
omap_writew(0x400, ARM_IDLECT1);
|
||||
|
||||
/*
|
||||
* According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
|
||||
* of the ARM_IDLECT2 register must be set to zero. The power-on
|
||||
* default value of this bit is one.
|
||||
*/
|
||||
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
|
||||
|
||||
/*
|
||||
* Only enable those clocks we will need, let the drivers
|
||||
* enable other clocks as necessary
|
||||
*/
|
||||
clk_enable(&armper_ck.clk);
|
||||
clk_enable(&armxor_ck.clk);
|
||||
clk_enable(&armtim_ck.clk); /* This should be done by timer code */
|
||||
|
||||
if (cpu_is_omap15xx())
|
||||
clk_enable(&arm_gpio_ck);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/clock.h
|
||||
*
|
||||
* Copyright (C) 2004 - 2005 Nokia corporation
|
||||
* Copyright (C) 2004 - 2005, 2009 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
|
||||
*
|
||||
|
@ -13,30 +13,36 @@
|
|||
#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
|
||||
#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
|
||||
|
||||
static unsigned long omap1_ckctl_recalc(struct clk *clk);
|
||||
static unsigned long omap1_watchdog_recalc(struct clk *clk);
|
||||
static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
|
||||
static unsigned long omap1_sossi_recalc(struct clk *clk);
|
||||
static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
|
||||
static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
|
||||
static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
|
||||
static unsigned long omap1_uart_recalc(struct clk *clk);
|
||||
static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
|
||||
static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
|
||||
static void omap1_init_ext_clk(struct clk * clk);
|
||||
static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
|
||||
static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
|
||||
#include <linux/clk.h>
|
||||
|
||||
static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
|
||||
static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
|
||||
#include <plat/clock.h>
|
||||
|
||||
struct mpu_rate {
|
||||
unsigned long rate;
|
||||
unsigned long xtal;
|
||||
unsigned long pll_rate;
|
||||
__u16 ckctl_val;
|
||||
__u16 dpllctl_val;
|
||||
};
|
||||
extern int __init omap1_clk_init(void);
|
||||
extern int omap1_clk_enable(struct clk *clk);
|
||||
extern void omap1_clk_disable(struct clk *clk);
|
||||
extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
|
||||
extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
|
||||
extern unsigned long omap1_ckctl_recalc(struct clk *clk);
|
||||
extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
|
||||
extern unsigned long omap1_sossi_recalc(struct clk *clk);
|
||||
extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
|
||||
extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
|
||||
extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
|
||||
extern unsigned long omap1_uart_recalc(struct clk *clk);
|
||||
extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
|
||||
extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
|
||||
extern void omap1_init_ext_clk(struct clk *clk);
|
||||
extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
|
||||
extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
|
||||
extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
|
||||
extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
|
||||
extern unsigned long omap1_watchdog_recalc(struct clk *clk);
|
||||
|
||||
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
||||
extern void __init omap1_clk_disable_unused(struct clk *clk);
|
||||
#else
|
||||
#define omap1_clk_disable_unused NULL
|
||||
#endif
|
||||
|
||||
struct uart_clk {
|
||||
struct clk clk;
|
||||
|
@ -96,596 +102,12 @@ struct arm_idlect1_clk {
|
|||
#define SOFT_REQ_REG 0xfffe0834
|
||||
#define SOFT_REQ_REG2 0xfffe0880
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap1 MPU rate table
|
||||
*-------------------------------------------------------------------------*/
|
||||
static struct mpu_rate rate_table[] = {
|
||||
/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
|
||||
* NOTE: Comment order here is different from bits in CKCTL value:
|
||||
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
|
||||
*/
|
||||
#if defined(CONFIG_OMAP_ARM_216MHZ)
|
||||
{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_195MHZ)
|
||||
{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_192MHZ)
|
||||
{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
|
||||
{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
|
||||
{ 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
|
||||
{ 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
|
||||
{ 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_182MHZ)
|
||||
{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_168MHZ)
|
||||
{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_150MHZ)
|
||||
{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_120MHZ)
|
||||
{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_96MHZ)
|
||||
{ 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_60MHZ)
|
||||
{ 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_30MHZ)
|
||||
{ 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
|
||||
#endif
|
||||
{ 0, 0, 0, 0, 0 },
|
||||
};
|
||||
extern __u32 arm_idlect1_mask;
|
||||
extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap1 clocks
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
static struct clk ck_ref = {
|
||||
.name = "ck_ref",
|
||||
.ops = &clkops_null,
|
||||
.rate = 12000000,
|
||||
};
|
||||
|
||||
static struct clk ck_dpll1 = {
|
||||
.name = "ck_dpll1",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_ref,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk ck_dpll1out = {
|
||||
.clk = {
|
||||
.name = "ck_dpll1out",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_CKOUT_ARM,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 12,
|
||||
};
|
||||
|
||||
static struct clk sossi_ck = {
|
||||
.name = "ck_sossi",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1out.clk,
|
||||
.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
|
||||
.enable_bit = 16,
|
||||
.recalc = &omap1_sossi_recalc,
|
||||
.set_rate = &omap1_set_sossi_rate,
|
||||
};
|
||||
|
||||
static struct clk arm_ck = {
|
||||
.name = "arm_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.rate_offset = CKCTL_ARMDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armper_ck = {
|
||||
.clk = {
|
||||
.name = "armper_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_PERCK,
|
||||
.rate_offset = CKCTL_PERDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
},
|
||||
.idlect_shift = 2,
|
||||
};
|
||||
|
||||
static struct clk arm_gpio_ck = {
|
||||
.name = "arm_gpio_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_GPIOCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armxor_ck = {
|
||||
.clk = {
|
||||
.name = "armxor_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_XORPCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 1,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armtim_ck = {
|
||||
.clk = {
|
||||
.name = "armtim_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_TIMCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 9,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armwdt_ck = {
|
||||
.clk = {
|
||||
.name = "armwdt_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_WDTCK,
|
||||
.recalc = &omap1_watchdog_recalc,
|
||||
},
|
||||
.idlect_shift = 0,
|
||||
};
|
||||
|
||||
static struct clk arminth_ck16xx = {
|
||||
.name = "arminth_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &arm_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
/* Note: On 16xx the frequency can be divided by 2 by programming
|
||||
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
|
||||
*
|
||||
* 1510 version is in TC clocks.
|
||||
*/
|
||||
};
|
||||
|
||||
static struct clk dsp_ck = {
|
||||
.name = "dsp_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
|
||||
.enable_bit = EN_DSPCK,
|
||||
.rate_offset = CKCTL_DSPDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct clk dspmmu_ck = {
|
||||
.name = "dspmmu_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct clk dspper_ck = {
|
||||
.name = "dspper_ck",
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_PERCK,
|
||||
.rate_offset = CKCTL_PERDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc_dsp_domain,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = &omap1_clk_set_rate_dsp_domain,
|
||||
};
|
||||
|
||||
static struct clk dspxor_ck = {
|
||||
.name = "dspxor_ck",
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_ref,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_XORPCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dsptim_ck = {
|
||||
.name = "dsptim_ck",
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_ref,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_DSPTIMCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
|
||||
static struct arm_idlect1_clk tc_ck = {
|
||||
.clk = {
|
||||
.name = "tc_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.rate_offset = CKCTL_TCDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
},
|
||||
.idlect_shift = 6,
|
||||
};
|
||||
|
||||
static struct clk arminth_ck1510 = {
|
||||
.name = "arminth_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
/* Note: On 1510 the frequency follows TC_CK
|
||||
*
|
||||
* 16xx version is in MPU clocks.
|
||||
*/
|
||||
};
|
||||
|
||||
static struct clk tipb_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "tipb_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk l3_ocpi_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "l3_ocpi_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_OCPI_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk tc1_ck = {
|
||||
.name = "tc1_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_TC1_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk tc2_ck = {
|
||||
.name = "tc2_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_TC2_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dma_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "dma_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dma_lcdfree_ck = {
|
||||
.name = "dma_lcdfree_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk api_ck = {
|
||||
.clk = {
|
||||
.name = "api_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_APICK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 8,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk lb_ck = {
|
||||
.clk = {
|
||||
.name = "lb_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LBCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 4,
|
||||
};
|
||||
|
||||
static struct clk rhea1_ck = {
|
||||
.name = "rhea1_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk rhea2_ck = {
|
||||
.name = "rhea2_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk lcd_ck_16xx = {
|
||||
.name = "lcd_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LCDCK,
|
||||
.rate_offset = CKCTL_LCDDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk lcd_ck_1510 = {
|
||||
.clk = {
|
||||
.name = "lcd_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LCDCK,
|
||||
.rate_offset = CKCTL_LCDDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
},
|
||||
.idlect_shift = 3,
|
||||
};
|
||||
|
||||
static struct clk uart1_1510 = {
|
||||
.name = "uart1_ck",
|
||||
.ops = &clkops_null,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
static struct uart_clk uart1_16xx = {
|
||||
.clk = {
|
||||
.name = "uart1_ck",
|
||||
.ops = &clkops_uart,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT |
|
||||
CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 29,
|
||||
},
|
||||
.sysc_addr = 0xfffb0054,
|
||||
};
|
||||
|
||||
static struct clk uart2_ck = {
|
||||
.name = "uart2_ck",
|
||||
.ops = &clkops_null,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
static struct clk uart3_1510 = {
|
||||
.name = "uart3_ck",
|
||||
.ops = &clkops_null,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
static struct uart_clk uart3_16xx = {
|
||||
.clk = {
|
||||
.name = "uart3_ck",
|
||||
.ops = &clkops_uart,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT |
|
||||
CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 31,
|
||||
},
|
||||
.sysc_addr = 0xfffb9854,
|
||||
};
|
||||
|
||||
static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
|
||||
.name = "usb_clko",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 6000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
|
||||
.enable_bit = USB_MCLK_EN_BIT,
|
||||
};
|
||||
|
||||
static struct clk usb_hhc_ck1510 = {
|
||||
.name = "usb_hhc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = USB_HOST_HHC_UHOST_EN,
|
||||
};
|
||||
|
||||
static struct clk usb_hhc_ck16xx = {
|
||||
.name = "usb_hhc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
|
||||
.enable_bit = 8 /* UHOST_EN */,
|
||||
};
|
||||
|
||||
static struct clk usb_dc_ck = {
|
||||
.name = "usb_dc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 4,
|
||||
};
|
||||
|
||||
static struct clk usb_dc_ck7xx = {
|
||||
.name = "usb_dc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 8,
|
||||
};
|
||||
|
||||
static struct clk mclk_1510 = {
|
||||
.name = "mclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.rate = 12000000,
|
||||
.flags = RATE_FIXED,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 6,
|
||||
};
|
||||
|
||||
static struct clk mclk_16xx = {
|
||||
.name = "mclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
|
||||
.enable_bit = COM_ULPD_PLL_CLK_REQ,
|
||||
.set_rate = &omap1_set_ext_clk_rate,
|
||||
.round_rate = &omap1_round_ext_clk_rate,
|
||||
.init = &omap1_init_ext_clk,
|
||||
};
|
||||
|
||||
static struct clk bclk_1510 = {
|
||||
.name = "bclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.rate = 12000000,
|
||||
.flags = RATE_FIXED,
|
||||
};
|
||||
|
||||
static struct clk bclk_16xx = {
|
||||
.name = "bclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
|
||||
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
|
||||
.set_rate = &omap1_set_ext_clk_rate,
|
||||
.round_rate = &omap1_round_ext_clk_rate,
|
||||
.init = &omap1_init_ext_clk,
|
||||
};
|
||||
|
||||
static struct clk mmc1_ck = {
|
||||
.name = "mmc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 23,
|
||||
};
|
||||
|
||||
static struct clk mmc2_ck = {
|
||||
.name = "mmc_ck",
|
||||
.id = 1,
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 20,
|
||||
};
|
||||
|
||||
static struct clk mmc3_ck = {
|
||||
.name = "mmc_ck",
|
||||
.id = 2,
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 12,
|
||||
};
|
||||
|
||||
static struct clk virtual_ck_mpu = {
|
||||
.name = "mpu",
|
||||
.ops = &clkops_null,
|
||||
.parent = &arm_ck, /* Is smarter alias for */
|
||||
.recalc = &followparent_recalc,
|
||||
.set_rate = &omap1_select_table_rate,
|
||||
.round_rate = &omap1_round_to_table_rate,
|
||||
};
|
||||
|
||||
/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
|
||||
remains active during MPU idle whenever this is enabled */
|
||||
static struct clk i2c_fck = {
|
||||
.name = "i2c_fck",
|
||||
.id = 1,
|
||||
.ops = &clkops_null,
|
||||
.flags = CLOCK_NO_IDLE_PARENT,
|
||||
.parent = &armxor_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk i2c_ick = {
|
||||
.name = "i2c_ick",
|
||||
.id = 1,
|
||||
.ops = &clkops_null,
|
||||
.flags = CLOCK_NO_IDLE_PARENT,
|
||||
.parent = &armper_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
extern const struct clkops clkops_dspck;
|
||||
extern const struct clkops clkops_dummy;
|
||||
extern const struct clkops clkops_uart;
|
||||
extern const struct clkops clkops_generic;
|
||||
|
||||
#endif
|
||||
|
|
843
arch/arm/mach-omap1/clock_data.c
Normal file
843
arch/arm/mach-omap1/clock_data.c
Normal file
|
@ -0,0 +1,843 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/clock_data.c
|
||||
*
|
||||
* Copyright (C) 2004 - 2005, 2009 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/mach-types.h> /* for machine_is_* */
|
||||
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clkdev_omap.h>
|
||||
#include <plat/usb.h> /* for OTG_BASE */
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* Omap1 clocks
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* XXX is this necessary? */
|
||||
static struct clk dummy_ck = {
|
||||
.name = "dummy",
|
||||
.ops = &clkops_dummy,
|
||||
.flags = RATE_FIXED,
|
||||
};
|
||||
|
||||
static struct clk ck_ref = {
|
||||
.name = "ck_ref",
|
||||
.ops = &clkops_null,
|
||||
.rate = 12000000,
|
||||
};
|
||||
|
||||
static struct clk ck_dpll1 = {
|
||||
.name = "ck_dpll1",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_ref,
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME: This clock seems to be necessary but no-one has asked for its
|
||||
* activation. [ FIX: SoSSI, SSR ]
|
||||
*/
|
||||
static struct arm_idlect1_clk ck_dpll1out = {
|
||||
.clk = {
|
||||
.name = "ck_dpll1out",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
|
||||
ENABLE_ON_INIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_CKOUT_ARM,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 12,
|
||||
};
|
||||
|
||||
static struct clk sossi_ck = {
|
||||
.name = "ck_sossi",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1out.clk,
|
||||
.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
|
||||
.enable_bit = 16,
|
||||
.recalc = &omap1_sossi_recalc,
|
||||
.set_rate = &omap1_set_sossi_rate,
|
||||
};
|
||||
|
||||
static struct clk arm_ck = {
|
||||
.name = "arm_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.rate_offset = CKCTL_ARMDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armper_ck = {
|
||||
.clk = {
|
||||
.name = "armper_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_PERCK,
|
||||
.rate_offset = CKCTL_PERDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
},
|
||||
.idlect_shift = 2,
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME: This clock seems to be necessary but no-one has asked for its
|
||||
* activation. [ GPIO code for 1510 ]
|
||||
*/
|
||||
static struct clk arm_gpio_ck = {
|
||||
.name = "arm_gpio_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = ENABLE_ON_INIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_GPIOCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armxor_ck = {
|
||||
.clk = {
|
||||
.name = "armxor_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_XORPCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 1,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armtim_ck = {
|
||||
.clk = {
|
||||
.name = "armtim_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_TIMCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 9,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk armwdt_ck = {
|
||||
.clk = {
|
||||
.name = "armwdt_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_ref,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_WDTCK,
|
||||
.recalc = &omap1_watchdog_recalc,
|
||||
},
|
||||
.idlect_shift = 0,
|
||||
};
|
||||
|
||||
static struct clk arminth_ck16xx = {
|
||||
.name = "arminth_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &arm_ck,
|
||||
.recalc = &followparent_recalc,
|
||||
/* Note: On 16xx the frequency can be divided by 2 by programming
|
||||
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
|
||||
*
|
||||
* 1510 version is in TC clocks.
|
||||
*/
|
||||
};
|
||||
|
||||
static struct clk dsp_ck = {
|
||||
.name = "dsp_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
|
||||
.enable_bit = EN_DSPCK,
|
||||
.rate_offset = CKCTL_DSPDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct clk dspmmu_ck = {
|
||||
.name = "dspmmu_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct clk dspper_ck = {
|
||||
.name = "dspper_ck",
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_PERCK,
|
||||
.rate_offset = CKCTL_PERDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc_dsp_domain,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = &omap1_clk_set_rate_dsp_domain,
|
||||
};
|
||||
|
||||
static struct clk dspxor_ck = {
|
||||
.name = "dspxor_ck",
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_ref,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_XORPCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dsptim_ck = {
|
||||
.name = "dsptim_ck",
|
||||
.ops = &clkops_dspck,
|
||||
.parent = &ck_ref,
|
||||
.enable_reg = DSP_IDLECT2,
|
||||
.enable_bit = EN_DSPTIMCK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
|
||||
static struct arm_idlect1_clk tc_ck = {
|
||||
.clk = {
|
||||
.name = "tc_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.rate_offset = CKCTL_TCDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
},
|
||||
.idlect_shift = 6,
|
||||
};
|
||||
|
||||
static struct clk arminth_ck1510 = {
|
||||
.name = "arminth_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
/* Note: On 1510 the frequency follows TC_CK
|
||||
*
|
||||
* 16xx version is in MPU clocks.
|
||||
*/
|
||||
};
|
||||
|
||||
static struct clk tipb_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "tipb_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk l3_ocpi_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "l3_ocpi_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_OCPI_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk tc1_ck = {
|
||||
.name = "tc1_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_TC1_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
* FIXME: This clock seems to be necessary but no-one has asked for its
|
||||
* activation. [ pm.c (SRAM), CCP, Camera ]
|
||||
*/
|
||||
static struct clk tc2_ck = {
|
||||
.name = "tc2_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = ENABLE_ON_INIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
|
||||
.enable_bit = EN_TC2_CK,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dma_ck = {
|
||||
/* No-idle controlled by "tc_ck" */
|
||||
.name = "dma_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk dma_lcdfree_ck = {
|
||||
.name = "dma_lcdfree_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk api_ck = {
|
||||
.clk = {
|
||||
.name = "api_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_APICK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 8,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk lb_ck = {
|
||||
.clk = {
|
||||
.name = "lb_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &tc_ck.clk,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LBCK,
|
||||
.recalc = &followparent_recalc,
|
||||
},
|
||||
.idlect_shift = 4,
|
||||
};
|
||||
|
||||
static struct clk rhea1_ck = {
|
||||
.name = "rhea1_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk rhea2_ck = {
|
||||
.name = "rhea2_ck",
|
||||
.ops = &clkops_null,
|
||||
.parent = &tc_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk lcd_ck_16xx = {
|
||||
.name = "lcd_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LCDCK,
|
||||
.rate_offset = CKCTL_LCDDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
};
|
||||
|
||||
static struct arm_idlect1_clk lcd_ck_1510 = {
|
||||
.clk = {
|
||||
.name = "lcd_ck",
|
||||
.ops = &clkops_generic,
|
||||
.parent = &ck_dpll1,
|
||||
.flags = CLOCK_IDLE_CONTROL,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
|
||||
.enable_bit = EN_LCDCK,
|
||||
.rate_offset = CKCTL_LCDDIV_OFFSET,
|
||||
.recalc = &omap1_ckctl_recalc,
|
||||
.round_rate = omap1_clk_round_rate_ckctl_arm,
|
||||
.set_rate = omap1_clk_set_rate_ckctl_arm,
|
||||
},
|
||||
.idlect_shift = 3,
|
||||
};
|
||||
|
||||
static struct clk uart1_1510 = {
|
||||
.name = "uart1_ck",
|
||||
.ops = &clkops_null,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
static struct uart_clk uart1_16xx = {
|
||||
.clk = {
|
||||
.name = "uart1_ck",
|
||||
.ops = &clkops_uart,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT |
|
||||
CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 29,
|
||||
},
|
||||
.sysc_addr = 0xfffb0054,
|
||||
};
|
||||
|
||||
static struct clk uart2_ck = {
|
||||
.name = "uart2_ck",
|
||||
.ops = &clkops_null,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
static struct clk uart3_1510 = {
|
||||
.name = "uart3_ck",
|
||||
.ops = &clkops_null,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 12000000,
|
||||
.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
|
||||
.set_rate = &omap1_set_uart_rate,
|
||||
.recalc = &omap1_uart_recalc,
|
||||
};
|
||||
|
||||
static struct uart_clk uart3_16xx = {
|
||||
.clk = {
|
||||
.name = "uart3_ck",
|
||||
.ops = &clkops_uart,
|
||||
/* Direct from ULPD, no real parent */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT |
|
||||
CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 31,
|
||||
},
|
||||
.sysc_addr = 0xfffb9854,
|
||||
};
|
||||
|
||||
static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
|
||||
.name = "usb_clko",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 6000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
|
||||
.enable_bit = USB_MCLK_EN_BIT,
|
||||
};
|
||||
|
||||
static struct clk usb_hhc_ck1510 = {
|
||||
.name = "usb_hhc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = USB_HOST_HHC_UHOST_EN,
|
||||
};
|
||||
|
||||
static struct clk usb_hhc_ck16xx = {
|
||||
.name = "usb_hhc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
|
||||
.enable_bit = 8 /* UHOST_EN */,
|
||||
};
|
||||
|
||||
static struct clk usb_dc_ck = {
|
||||
.name = "usb_dc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 4,
|
||||
};
|
||||
|
||||
static struct clk usb_dc_ck7xx = {
|
||||
.name = "usb_dc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 8,
|
||||
};
|
||||
|
||||
static struct clk mclk_1510 = {
|
||||
.name = "mclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.rate = 12000000,
|
||||
.flags = RATE_FIXED,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 6,
|
||||
};
|
||||
|
||||
static struct clk mclk_16xx = {
|
||||
.name = "mclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
|
||||
.enable_bit = COM_ULPD_PLL_CLK_REQ,
|
||||
.set_rate = &omap1_set_ext_clk_rate,
|
||||
.round_rate = &omap1_round_ext_clk_rate,
|
||||
.init = &omap1_init_ext_clk,
|
||||
};
|
||||
|
||||
static struct clk bclk_1510 = {
|
||||
.name = "bclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.rate = 12000000,
|
||||
.flags = RATE_FIXED,
|
||||
};
|
||||
|
||||
static struct clk bclk_16xx = {
|
||||
.name = "bclk",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
|
||||
.enable_bit = SWD_ULPD_PLL_CLK_REQ,
|
||||
.set_rate = &omap1_set_ext_clk_rate,
|
||||
.round_rate = &omap1_round_ext_clk_rate,
|
||||
.init = &omap1_init_ext_clk,
|
||||
};
|
||||
|
||||
static struct clk mmc1_ck = {
|
||||
.name = "mmc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 23,
|
||||
};
|
||||
|
||||
static struct clk mmc2_ck = {
|
||||
.name = "mmc_ck",
|
||||
.id = 1,
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
|
||||
.enable_bit = 20,
|
||||
};
|
||||
|
||||
static struct clk mmc3_ck = {
|
||||
.name = "mmc_ck",
|
||||
.id = 2,
|
||||
.ops = &clkops_generic,
|
||||
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
||||
.parent = &armper_ck.clk,
|
||||
.rate = 48000000,
|
||||
.flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = 12,
|
||||
};
|
||||
|
||||
static struct clk virtual_ck_mpu = {
|
||||
.name = "mpu",
|
||||
.ops = &clkops_null,
|
||||
.parent = &arm_ck, /* Is smarter alias for */
|
||||
.recalc = &followparent_recalc,
|
||||
.set_rate = &omap1_select_table_rate,
|
||||
.round_rate = &omap1_round_to_table_rate,
|
||||
};
|
||||
|
||||
/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
|
||||
remains active during MPU idle whenever this is enabled */
|
||||
static struct clk i2c_fck = {
|
||||
.name = "i2c_fck",
|
||||
.id = 1,
|
||||
.ops = &clkops_null,
|
||||
.flags = CLOCK_NO_IDLE_PARENT,
|
||||
.parent = &armxor_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
static struct clk i2c_ick = {
|
||||
.name = "i2c_ick",
|
||||
.id = 1,
|
||||
.ops = &clkops_null,
|
||||
.flags = CLOCK_NO_IDLE_PARENT,
|
||||
.parent = &armper_ck.clk,
|
||||
.recalc = &followparent_recalc,
|
||||
};
|
||||
|
||||
/*
|
||||
* clkdev integration
|
||||
*/
|
||||
|
||||
static struct omap_clk omap_clks[] = {
|
||||
/* non-ULPD clocks */
|
||||
CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
|
||||
/* CK_GEN1 clocks */
|
||||
CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
|
||||
CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
|
||||
CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
|
||||
/* CK_GEN2 clocks */
|
||||
CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
|
||||
/* CK_GEN3 clocks */
|
||||
CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
|
||||
CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
|
||||
CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
|
||||
CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
|
||||
CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
|
||||
CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
|
||||
CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
|
||||
/* ULPD clocks */
|
||||
CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
|
||||
CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
|
||||
CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
|
||||
CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
|
||||
CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
|
||||
CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
|
||||
CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
|
||||
CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
|
||||
/* Virtual clocks */
|
||||
CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
|
||||
CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
|
||||
CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
|
||||
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
|
||||
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
|
||||
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
|
||||
CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
|
||||
};
|
||||
|
||||
/*
|
||||
* init
|
||||
*/
|
||||
|
||||
static struct clk_functions omap1_clk_functions __initdata = {
|
||||
.clk_enable = omap1_clk_enable,
|
||||
.clk_disable = omap1_clk_disable,
|
||||
.clk_round_rate = omap1_clk_round_rate,
|
||||
.clk_set_rate = omap1_clk_set_rate,
|
||||
.clk_disable_unused = omap1_clk_disable_unused,
|
||||
};
|
||||
|
||||
int __init omap1_clk_init(void)
|
||||
{
|
||||
struct omap_clk *c;
|
||||
const struct omap_clock_config *info;
|
||||
int crystal_type = 0; /* Default 12 MHz */
|
||||
u32 reg, cpu_mask;
|
||||
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
/*
|
||||
* Resets some clocks that may be left on from bootloader,
|
||||
* but leaves serial clocks on.
|
||||
*/
|
||||
omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
|
||||
#endif
|
||||
|
||||
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
|
||||
reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
|
||||
omap_writew(reg, SOFT_REQ_REG);
|
||||
if (!cpu_is_omap15xx())
|
||||
omap_writew(0, SOFT_REQ_REG2);
|
||||
|
||||
clk_init(&omap1_clk_functions);
|
||||
|
||||
/* By default all idlect1 clocks are allowed to idle */
|
||||
arm_idlect1_mask = ~0;
|
||||
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
|
||||
clk_preinit(c->lk.clk);
|
||||
|
||||
cpu_mask = 0;
|
||||
if (cpu_is_omap16xx())
|
||||
cpu_mask |= CK_16XX;
|
||||
if (cpu_is_omap1510())
|
||||
cpu_mask |= CK_1510;
|
||||
if (cpu_is_omap7xx())
|
||||
cpu_mask |= CK_7XX;
|
||||
if (cpu_is_omap310())
|
||||
cpu_mask |= CK_310;
|
||||
|
||||
for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
|
||||
if (c->cpu & cpu_mask) {
|
||||
clkdev_add(&c->lk);
|
||||
clk_register(c->lk.clk);
|
||||
}
|
||||
|
||||
/* Pointers to these clocks are needed by code in clock.c */
|
||||
api_ck_p = clk_get(NULL, "api_ck");
|
||||
ck_dpll1_p = clk_get(NULL, "ck_dpll1");
|
||||
ck_ref_p = clk_get(NULL, "ck_ref");
|
||||
|
||||
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
|
||||
if (info != NULL) {
|
||||
if (!cpu_is_omap15xx())
|
||||
crystal_type = info->system_clock_type;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
||||
ck_ref.rate = 13000000;
|
||||
#elif defined(CONFIG_ARCH_OMAP16XX)
|
||||
if (crystal_type == 2)
|
||||
ck_ref.rate = 19200000;
|
||||
#endif
|
||||
|
||||
pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
|
||||
"0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
|
||||
omap_readw(ARM_CKCTL));
|
||||
|
||||
/* We want to be in syncronous scalable mode */
|
||||
omap_writew(0x1000, ARM_SYSST);
|
||||
|
||||
#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
|
||||
/* Use values set by bootloader. Determine PLL rate and recalculate
|
||||
* dependent clocks as if kernel had changed PLL or divisors.
|
||||
*/
|
||||
{
|
||||
unsigned pll_ctl_val = omap_readw(DPLL_CTL);
|
||||
|
||||
ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
|
||||
if (pll_ctl_val & 0x10) {
|
||||
/* PLL enabled, apply multiplier and divisor */
|
||||
if (pll_ctl_val & 0xf80)
|
||||
ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
|
||||
ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
|
||||
} else {
|
||||
/* PLL disabled, apply bypass divisor */
|
||||
switch (pll_ctl_val & 0xc) {
|
||||
case 0:
|
||||
break;
|
||||
case 0x4:
|
||||
ck_dpll1.rate /= 2;
|
||||
break;
|
||||
default:
|
||||
ck_dpll1.rate /= 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
/* Find the highest supported frequency and enable it */
|
||||
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
|
||||
printk(KERN_ERR "System frequencies not set. Check your config.\n");
|
||||
/* Guess sane values (60MHz) */
|
||||
omap_writew(0x2290, DPLL_CTL);
|
||||
omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
|
||||
ck_dpll1.rate = 60000000;
|
||||
}
|
||||
#endif
|
||||
propagate_rate(&ck_dpll1);
|
||||
/* Cache rates for clocks connected to ck_ref (not dpll1) */
|
||||
propagate_rate(&ck_ref);
|
||||
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
|
||||
"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
|
||||
ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
|
||||
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
|
||||
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
|
||||
|
||||
#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
|
||||
/* Select slicer output as OMAP input clock */
|
||||
omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
|
||||
#endif
|
||||
|
||||
/* Amstrad Delta wants BCLK high when inactive */
|
||||
if (machine_is_ams_delta())
|
||||
omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
|
||||
(1 << SDW_MCLK_INV_BIT),
|
||||
ULPD_CLOCK_CTRL);
|
||||
|
||||
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
|
||||
/* (on 730, bit 13 must not be cleared) */
|
||||
if (cpu_is_omap7xx())
|
||||
omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
|
||||
else
|
||||
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
|
||||
|
||||
/* Put DSP/MPUI into reset until needed */
|
||||
omap_writew(0, ARM_RSTCT1);
|
||||
omap_writew(1, ARM_RSTCT2);
|
||||
omap_writew(0x400, ARM_IDLECT1);
|
||||
|
||||
/*
|
||||
* According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
|
||||
* of the ARM_IDLECT2 register must be set to zero. The power-on
|
||||
* default value of this bit is one.
|
||||
*/
|
||||
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
|
||||
|
||||
/*
|
||||
* Only enable those clocks we will need, let the drivers
|
||||
* enable other clocks as necessary
|
||||
*/
|
||||
clk_enable(&armper_ck.clk);
|
||||
clk_enable(&armxor_ck.clk);
|
||||
clk_enable(&armtim_ck.clk); /* This should be done by timer code */
|
||||
|
||||
if (cpu_is_omap15xx())
|
||||
clk_enable(&arm_gpio_ck);
|
||||
|
||||
return 0;
|
||||
}
|
39
arch/arm/mach-omap1/i2c.c
Normal file
39
arch/arm/mach-omap1/i2c.c
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Helper module for board specific I2C bus registration
|
||||
*
|
||||
* Copyright (C) 2009 Nokia Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
struct i2c_board_info const *info,
|
||||
unsigned len)
|
||||
{
|
||||
if (cpu_is_omap7xx()) {
|
||||
omap_cfg_reg(I2C_7XX_SDA);
|
||||
omap_cfg_reg(I2C_7XX_SCL);
|
||||
} else {
|
||||
omap_cfg_reg(I2C_SDA);
|
||||
omap_cfg_reg(I2C_SCL);
|
||||
}
|
||||
|
||||
return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
|
||||
}
|
78
arch/arm/mach-omap1/include/mach/lcd_dma.h
Normal file
78
arch/arm/mach-omap1/include/mach/lcd_dma.h
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* arch/arm/mach-omap1/include/mach/lcd_dma.h
|
||||
*
|
||||
* Extracted from arch/arm/plat-omap/include/plat/dma.h
|
||||
* Copyright (C) 2003 Nokia Corporation
|
||||
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __MACH_OMAP1_LCD_DMA_H__
|
||||
#define __MACH_OMAP1_LCD_DMA_H__
|
||||
|
||||
/* Hardware registers for LCD DMA */
|
||||
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
|
||||
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
|
||||
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
|
||||
#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
|
||||
#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
|
||||
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
|
||||
|
||||
#define OMAP1610_DMA_LCD_BASE (0xfffee300)
|
||||
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
|
||||
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
|
||||
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
|
||||
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
|
||||
#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
|
||||
#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
|
||||
#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
|
||||
#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
|
||||
#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
|
||||
#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
|
||||
#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
|
||||
#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
|
||||
#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
|
||||
#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
|
||||
#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
|
||||
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
|
||||
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
|
||||
|
||||
/* LCD DMA block numbers */
|
||||
enum {
|
||||
OMAP_LCD_DMA_B1_TOP,
|
||||
OMAP_LCD_DMA_B1_BOTTOM,
|
||||
OMAP_LCD_DMA_B2_TOP,
|
||||
OMAP_LCD_DMA_B2_BOTTOM
|
||||
};
|
||||
|
||||
/* LCD DMA functions */
|
||||
extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
|
||||
void *data);
|
||||
extern void omap_free_lcd_dma(void);
|
||||
extern void omap_setup_lcd_dma(void);
|
||||
extern void omap_enable_lcd_dma(void);
|
||||
extern void omap_stop_lcd_dma(void);
|
||||
extern void omap_set_lcd_dma_ext_controller(int external);
|
||||
extern void omap_set_lcd_dma_single_transfer(int single);
|
||||
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
|
||||
int data_type);
|
||||
extern void omap_set_lcd_dma_b1_rotation(int rotate);
|
||||
extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
|
||||
extern void omap_set_lcd_dma_b1_mirror(int mirror);
|
||||
extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
|
||||
|
||||
extern int omap_lcd_dma_running(void);
|
||||
|
||||
#endif /* __MACH_OMAP1_LCD_DMA_H__ */
|
57
arch/arm/mach-omap1/include/mach/lcdc.h
Normal file
57
arch/arm/mach-omap1/include/mach/lcdc.h
Normal file
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* arch/arm/mach-omap1/include/mach/lcdc.h
|
||||
*
|
||||
* Extracted from drivers/video/omap/lcdc.c
|
||||
* Copyright (C) 2004 Nokia Corporation
|
||||
* Author: Imre Deak <imre.deak@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
#ifndef __MACH_LCDC_H__
|
||||
#define __MACH_LCDC_H__
|
||||
|
||||
#define OMAP_LCDC_BASE 0xfffec000
|
||||
#define OMAP_LCDC_SIZE 256
|
||||
#define OMAP_LCDC_IRQ INT_LCD_CTRL
|
||||
|
||||
#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
|
||||
#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
|
||||
#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
|
||||
#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
|
||||
#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
|
||||
#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
|
||||
#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
|
||||
#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
|
||||
|
||||
#define OMAP_LCDC_STAT_DONE (1 << 0)
|
||||
#define OMAP_LCDC_STAT_VSYNC (1 << 1)
|
||||
#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
|
||||
#define OMAP_LCDC_STAT_ABC (1 << 3)
|
||||
#define OMAP_LCDC_STAT_LINE_INT (1 << 4)
|
||||
#define OMAP_LCDC_STAT_FUF (1 << 5)
|
||||
#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
|
||||
|
||||
#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
|
||||
#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
|
||||
#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
|
||||
|
||||
#define OMAP_LCDC_IRQ_VSYNC (1 << 2)
|
||||
#define OMAP_LCDC_IRQ_DONE (1 << 3)
|
||||
#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
|
||||
#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
|
||||
#define OMAP_LCDC_IRQ_LINE (1 << 6)
|
||||
#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
|
||||
|
||||
#endif /* __MACH_LCDC_H__ */
|
|
@ -18,7 +18,8 @@
|
|||
#include <plat/mux.h>
|
||||
#include <plat/tc.h>
|
||||
|
||||
extern int omap1_clk_init(void);
|
||||
#include "clock.h"
|
||||
|
||||
extern void omap_check_revision(void);
|
||||
extern void omap_sram_init(void);
|
||||
extern void omapfb_reserve_sdram(void);
|
||||
|
|
448
arch/arm/mach-omap1/lcd_dma.c
Normal file
448
arch/arm/mach-omap1/lcd_dma.c
Normal file
|
@ -0,0 +1,448 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/lcd_dma.c
|
||||
*
|
||||
* Extracted from arch/arm/plat-omap/dma.c
|
||||
* Copyright (C) 2003 - 2008 Nokia Corporation
|
||||
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
|
||||
* Graphics DMA and LCD DMA graphics tranformations
|
||||
* by Imre Deak <imre.deak@nokia.com>
|
||||
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
|
||||
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
|
||||
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments
|
||||
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
*
|
||||
* Support functions for the OMAP internal DMA channels.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/lcdc.h>
|
||||
#include <plat/dma.h>
|
||||
|
||||
int omap_lcd_dma_running(void)
|
||||
{
|
||||
/*
|
||||
* On OMAP1510, internal LCD controller will start the transfer
|
||||
* when it gets enabled, so assume DMA running if LCD enabled.
|
||||
*/
|
||||
if (cpu_is_omap1510())
|
||||
if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
|
||||
return 1;
|
||||
|
||||
/* Check if LCD DMA is running */
|
||||
if (cpu_is_omap16xx())
|
||||
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct lcd_dma_info {
|
||||
spinlock_t lock;
|
||||
int reserved;
|
||||
void (*callback)(u16 status, void *data);
|
||||
void *cb_data;
|
||||
|
||||
int active;
|
||||
unsigned long addr, size;
|
||||
int rotate, data_type, xres, yres;
|
||||
int vxres;
|
||||
int mirror;
|
||||
int xscale, yscale;
|
||||
int ext_ctrl;
|
||||
int src_port;
|
||||
int single_transfer;
|
||||
} lcd_dma;
|
||||
|
||||
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
|
||||
int data_type)
|
||||
{
|
||||
lcd_dma.addr = addr;
|
||||
lcd_dma.data_type = data_type;
|
||||
lcd_dma.xres = fb_xres;
|
||||
lcd_dma.yres = fb_yres;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
|
||||
|
||||
void omap_set_lcd_dma_src_port(int port)
|
||||
{
|
||||
lcd_dma.src_port = port;
|
||||
}
|
||||
|
||||
void omap_set_lcd_dma_ext_controller(int external)
|
||||
{
|
||||
lcd_dma.ext_ctrl = external;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
|
||||
|
||||
void omap_set_lcd_dma_single_transfer(int single)
|
||||
{
|
||||
lcd_dma.single_transfer = single;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
|
||||
|
||||
void omap_set_lcd_dma_b1_rotation(int rotate)
|
||||
{
|
||||
if (cpu_is_omap1510()) {
|
||||
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
lcd_dma.rotate = rotate;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
|
||||
|
||||
void omap_set_lcd_dma_b1_mirror(int mirror)
|
||||
{
|
||||
if (cpu_is_omap1510()) {
|
||||
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
|
||||
BUG();
|
||||
}
|
||||
lcd_dma.mirror = mirror;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
|
||||
|
||||
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
|
||||
{
|
||||
if (cpu_is_omap1510()) {
|
||||
printk(KERN_ERR "DMA virtual resulotion is not supported "
|
||||
"in 1510 mode\n");
|
||||
BUG();
|
||||
}
|
||||
lcd_dma.vxres = vxres;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
|
||||
|
||||
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
|
||||
{
|
||||
if (cpu_is_omap1510()) {
|
||||
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
|
||||
BUG();
|
||||
}
|
||||
lcd_dma.xscale = xscale;
|
||||
lcd_dma.yscale = yscale;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
|
||||
|
||||
static void set_b1_regs(void)
|
||||
{
|
||||
unsigned long top, bottom;
|
||||
int es;
|
||||
u16 w;
|
||||
unsigned long en, fn;
|
||||
long ei, fi;
|
||||
unsigned long vxres;
|
||||
unsigned int xscale, yscale;
|
||||
|
||||
switch (lcd_dma.data_type) {
|
||||
case OMAP_DMA_DATA_TYPE_S8:
|
||||
es = 1;
|
||||
break;
|
||||
case OMAP_DMA_DATA_TYPE_S16:
|
||||
es = 2;
|
||||
break;
|
||||
case OMAP_DMA_DATA_TYPE_S32:
|
||||
es = 4;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
|
||||
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
|
||||
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
|
||||
BUG_ON(vxres < lcd_dma.xres);
|
||||
|
||||
#define PIXADDR(x, y) (lcd_dma.addr + \
|
||||
((y) * vxres * yscale + (x) * xscale) * es)
|
||||
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
|
||||
|
||||
switch (lcd_dma.rotate) {
|
||||
case 0:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(0, 0);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
/* 1510 DMA requires the bottom address to be 2 more
|
||||
* than the actual last memory access location. */
|
||||
if (cpu_is_omap1510() &&
|
||||
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
|
||||
bottom += 2;
|
||||
ei = PIXSTEP(0, 0, 1, 0);
|
||||
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
|
||||
} else {
|
||||
top = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
bottom = PIXADDR(0, lcd_dma.yres - 1);
|
||||
ei = PIXSTEP(1, 0, 0, 0);
|
||||
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
|
||||
}
|
||||
en = lcd_dma.xres;
|
||||
fn = lcd_dma.yres;
|
||||
break;
|
||||
case 90:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(0, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
ei = PIXSTEP(0, 1, 0, 0);
|
||||
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
|
||||
} else {
|
||||
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(0, 0);
|
||||
ei = PIXSTEP(0, 1, 0, 0);
|
||||
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
|
||||
}
|
||||
en = lcd_dma.yres;
|
||||
fn = lcd_dma.xres;
|
||||
break;
|
||||
case 180:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(0, 0);
|
||||
ei = PIXSTEP(1, 0, 0, 0);
|
||||
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
|
||||
} else {
|
||||
top = PIXADDR(0, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
ei = PIXSTEP(0, 0, 1, 0);
|
||||
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
|
||||
}
|
||||
en = lcd_dma.xres;
|
||||
fn = lcd_dma.yres;
|
||||
break;
|
||||
case 270:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
bottom = PIXADDR(0, lcd_dma.yres - 1);
|
||||
ei = PIXSTEP(0, 0, 0, 1);
|
||||
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
|
||||
} else {
|
||||
top = PIXADDR(0, 0);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
ei = PIXSTEP(0, 0, 0, 1);
|
||||
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
|
||||
}
|
||||
en = lcd_dma.yres;
|
||||
fn = lcd_dma.xres;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return; /* Suppress warning about uninitialized vars */
|
||||
}
|
||||
|
||||
if (cpu_is_omap1510()) {
|
||||
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
|
||||
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
|
||||
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
|
||||
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* 1610 regs */
|
||||
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
|
||||
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
|
||||
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
|
||||
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
|
||||
|
||||
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
|
||||
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
|
||||
w &= ~0x03;
|
||||
w |= lcd_dma.data_type;
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
/* Always set the source port as SDRAM for now*/
|
||||
w &= ~(0x03 << 6);
|
||||
if (lcd_dma.callback != NULL)
|
||||
w |= 1 << 1; /* Block interrupt enable */
|
||||
else
|
||||
w &= ~(1 << 1);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
|
||||
if (!(lcd_dma.rotate || lcd_dma.mirror ||
|
||||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
|
||||
return;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
/* Set the double-indexed addressing mode */
|
||||
w |= (0x03 << 12);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
|
||||
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
|
||||
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
|
||||
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
|
||||
}
|
||||
|
||||
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
u16 w;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
if (unlikely(!(w & (1 << 3)))) {
|
||||
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
|
||||
return IRQ_NONE;
|
||||
}
|
||||
/* Ack the IRQ */
|
||||
w |= (1 << 3);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
lcd_dma.active = 0;
|
||||
if (lcd_dma.callback != NULL)
|
||||
lcd_dma.callback(w, lcd_dma.cb_data);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
|
||||
void *data)
|
||||
{
|
||||
spin_lock_irq(&lcd_dma.lock);
|
||||
if (lcd_dma.reserved) {
|
||||
spin_unlock_irq(&lcd_dma.lock);
|
||||
printk(KERN_ERR "LCD DMA channel already reserved\n");
|
||||
BUG();
|
||||
return -EBUSY;
|
||||
}
|
||||
lcd_dma.reserved = 1;
|
||||
spin_unlock_irq(&lcd_dma.lock);
|
||||
lcd_dma.callback = callback;
|
||||
lcd_dma.cb_data = data;
|
||||
lcd_dma.active = 0;
|
||||
lcd_dma.single_transfer = 0;
|
||||
lcd_dma.rotate = 0;
|
||||
lcd_dma.vxres = 0;
|
||||
lcd_dma.mirror = 0;
|
||||
lcd_dma.xscale = 0;
|
||||
lcd_dma.yscale = 0;
|
||||
lcd_dma.ext_ctrl = 0;
|
||||
lcd_dma.src_port = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_request_lcd_dma);
|
||||
|
||||
void omap_free_lcd_dma(void)
|
||||
{
|
||||
spin_lock(&lcd_dma.lock);
|
||||
if (!lcd_dma.reserved) {
|
||||
spin_unlock(&lcd_dma.lock);
|
||||
printk(KERN_ERR "LCD DMA is not reserved\n");
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
if (!cpu_is_omap1510())
|
||||
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
|
||||
OMAP1610_DMA_LCD_CCR);
|
||||
lcd_dma.reserved = 0;
|
||||
spin_unlock(&lcd_dma.lock);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_free_lcd_dma);
|
||||
|
||||
void omap_enable_lcd_dma(void)
|
||||
{
|
||||
u16 w;
|
||||
|
||||
/*
|
||||
* Set the Enable bit only if an external controller is
|
||||
* connected. Otherwise the OMAP internal controller will
|
||||
* start the transfer when it gets enabled.
|
||||
*/
|
||||
if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
|
||||
return;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
w |= 1 << 8;
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
|
||||
lcd_dma.active = 1;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
w |= 1 << 7;
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_enable_lcd_dma);
|
||||
|
||||
void omap_setup_lcd_dma(void)
|
||||
{
|
||||
BUG_ON(lcd_dma.active);
|
||||
if (!cpu_is_omap1510()) {
|
||||
/* Set some reasonable defaults */
|
||||
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
|
||||
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
|
||||
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
|
||||
}
|
||||
set_b1_regs();
|
||||
if (!cpu_is_omap1510()) {
|
||||
u16 w;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
/*
|
||||
* If DMA was already active set the end_prog bit to have
|
||||
* the programmed register set loaded into the active
|
||||
* register set.
|
||||
*/
|
||||
w |= 1 << 11; /* End_prog */
|
||||
if (!lcd_dma.single_transfer)
|
||||
w |= (3 << 8); /* Auto_init, repeat */
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(omap_setup_lcd_dma);
|
||||
|
||||
void omap_stop_lcd_dma(void)
|
||||
{
|
||||
u16 w;
|
||||
|
||||
lcd_dma.active = 0;
|
||||
if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
|
||||
return;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
w &= ~(1 << 7);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
w &= ~(1 << 8);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_stop_lcd_dma);
|
||||
|
||||
static int __init omap_init_lcd_dma(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (cpu_is_omap16xx()) {
|
||||
u16 w;
|
||||
|
||||
/* this would prevent OMAP sleep */
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
w &= ~(1 << 8);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
}
|
||||
|
||||
spin_lock_init(&lcd_dma.lock);
|
||||
|
||||
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
|
||||
"LCD DMA", NULL);
|
||||
if (r != 0)
|
||||
printk(KERN_ERR "unable to request IRQ for LCD DMA "
|
||||
"(error %d)\n", r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
arch_initcall(omap_init_lcd_dma);
|
||||
|
|
@ -50,12 +50,18 @@ MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
|
|||
|
||||
MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
|
||||
MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
|
||||
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0)
|
||||
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
|
||||
MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
|
||||
MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
|
||||
|
||||
/* MMC Pins */
|
||||
MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
|
||||
MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
|
||||
MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
|
||||
|
||||
/* I2C interface */
|
||||
MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
|
||||
MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
|
||||
};
|
||||
#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
|
||||
#else
|
||||
|
|
28
arch/arm/mach-omap1/opp.h
Normal file
28
arch/arm/mach-omap1/opp.h
Normal file
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/opp.h
|
||||
*
|
||||
* Copyright (C) 2004 - 2005 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H
|
||||
#define __ARCH_ARM_MACH_OMAP1_OPP_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct mpu_rate {
|
||||
unsigned long rate;
|
||||
unsigned long xtal;
|
||||
unsigned long pll_rate;
|
||||
__u16 ckctl_val;
|
||||
__u16 dpllctl_val;
|
||||
};
|
||||
|
||||
extern struct mpu_rate omap1_rate_table[];
|
||||
|
||||
#endif
|
59
arch/arm/mach-omap1/opp_data.c
Normal file
59
arch/arm/mach-omap1/opp_data.c
Normal file
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap1/opp_data.c
|
||||
*
|
||||
* Copyright (C) 2004 - 2005 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "opp.h"
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap1 MPU rate table
|
||||
*-------------------------------------------------------------------------*/
|
||||
struct mpu_rate omap1_rate_table[] = {
|
||||
/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
|
||||
* NOTE: Comment order here is different from bits in CKCTL value:
|
||||
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
|
||||
*/
|
||||
#if defined(CONFIG_OMAP_ARM_216MHZ)
|
||||
{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_195MHZ)
|
||||
{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_192MHZ)
|
||||
{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
|
||||
{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
|
||||
{ 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
|
||||
{ 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
|
||||
{ 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_182MHZ)
|
||||
{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_168MHZ)
|
||||
{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_150MHZ)
|
||||
{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_120MHZ)
|
||||
{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_96MHZ)
|
||||
{ 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_60MHZ)
|
||||
{ 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
|
||||
#endif
|
||||
#if defined(CONFIG_OMAP_ARM_30MHZ)
|
||||
{ 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
|
||||
#endif
|
||||
{ 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
|
@ -24,6 +24,18 @@ config ARCH_OMAP3430
|
|||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select ARCH_OMAP_OTG
|
||||
|
||||
config OMAP_PACKAGE_CBC
|
||||
bool
|
||||
|
||||
config OMAP_PACKAGE_CBB
|
||||
bool
|
||||
|
||||
config OMAP_PACKAGE_CUS
|
||||
bool
|
||||
|
||||
config OMAP_PACKAGE_CBP
|
||||
bool
|
||||
|
||||
comment "OMAP Board Type"
|
||||
depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
|
||||
|
||||
|
@ -52,14 +64,17 @@ config MACH_OMAP_2430SDP
|
|||
config MACH_OMAP3_BEAGLE
|
||||
bool "OMAP3 BEAGLE board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP_LDP
|
||||
bool "OMAP3 LDP board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OVERO
|
||||
bool "Gumstix Overo board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP3EVM
|
||||
bool "OMAP 3530 EVM board"
|
||||
|
@ -68,14 +83,22 @@ config MACH_OMAP3EVM
|
|||
config MACH_OMAP3517EVM
|
||||
bool "OMAP3517/ AM3517 EVM board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP3_PANDORA
|
||||
bool "OMAP3 Pandora"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP3_TOUCHBOOK
|
||||
bool "OMAP3 Touch Book"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select BACKLIGHT_CLASS_DEVICE
|
||||
|
||||
config MACH_OMAP_3430SDP
|
||||
bool "OMAP 3430 SDP board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_NOKIA_N800
|
||||
bool
|
||||
|
@ -96,26 +119,33 @@ config MACH_NOKIA_N8X0
|
|||
config MACH_NOKIA_RX51
|
||||
bool "Nokia RX-51 board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP_ZOOM2
|
||||
bool "OMAP3 Zoom2 board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP_ZOOM3
|
||||
bool "OMAP3630 Zoom3 board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBP
|
||||
|
||||
config MACH_CM_T35
|
||||
bool "CompuLab CM-T35 module"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CUS
|
||||
select OMAP_MUX
|
||||
|
||||
config MACH_IGEP0020
|
||||
bool "IGEP0020"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP_3630SDP
|
||||
bool "OMAP3630 SDP board"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
select OMAP_PACKAGE_CBP
|
||||
|
||||
config MACH_OMAP_4430SDP
|
||||
bool "OMAP 4430 SDP board"
|
||||
|
@ -128,3 +158,15 @@ config OMAP3_EMU
|
|||
help
|
||||
Say Y here to enable debugging hardware of omap3
|
||||
|
||||
config OMAP3_SDRC_AC_TIMING
|
||||
bool "Enable SDRC AC timing register changes"
|
||||
depends on ARCH_OMAP3 && ARCH_OMAP34XX
|
||||
default n
|
||||
help
|
||||
If you know that none of your system initiators will attempt to
|
||||
access SDRAM during CORE DVFS, select Y here. This should boost
|
||||
SDRAM performance at lower CORE OPPs. There are relatively few
|
||||
users who will wish to say yes at this point - almost everyone will
|
||||
wish to say no. Selecting yes without understanding what is
|
||||
going on could result in system crashes;
|
||||
|
||||
|
|
|
@ -6,11 +6,14 @@
|
|||
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
|
||||
|
||||
omap-2-3-common = irq.o sdrc.o omap_hwmod.o
|
||||
omap-3-4-common = dpll.o
|
||||
prcm-common = prcm.o powerdomain.o
|
||||
clock-common = clock.o clockdomain.o
|
||||
clock-common = clock.o clock_common_data.o clockdomain.o
|
||||
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common)
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
|
||||
$(omap-3-4-common)
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
|
||||
|
||||
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
|
||||
|
||||
|
@ -23,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
|
|||
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
|
||||
|
||||
# Pin multiplexing
|
||||
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
|
||||
|
||||
# SMS/SDRC
|
||||
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
|
||||
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
|
||||
|
@ -41,8 +47,11 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
|
|||
obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
|
||||
|
||||
# Clock framework
|
||||
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
|
||||
obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o
|
||||
|
||||
# EMU peripherals
|
||||
obj-$(CONFIG_OMAP3_EMU) += emu.o
|
||||
|
@ -55,6 +64,9 @@ iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
|
|||
|
||||
obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y)
|
||||
|
||||
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
|
||||
obj-y += $(i2c-omap-m) $(i2c-omap-y)
|
||||
|
||||
# Specific board support
|
||||
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
|
||||
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
|
||||
|
@ -93,7 +105,8 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \
|
|||
mmc-twl4030.o
|
||||
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \
|
||||
mmc-twl4030.o
|
||||
|
||||
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
|
||||
mmc-twl4030.o
|
||||
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
|
||||
|
||||
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
#include <asm/mach/map.h>
|
||||
|
||||
#include <plat/mcspi.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/board.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/common.h>
|
||||
|
@ -42,6 +41,7 @@
|
|||
#include <plat/control.h>
|
||||
#include <plat/gpmc-smc91x.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-qimonda-hyb18m512160af-6.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
|
@ -625,7 +625,9 @@ static inline void board_smc91x_init(void)
|
|||
|
||||
static void enable_board_wakeup_source(void)
|
||||
{
|
||||
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
|
||||
/* T2 interrupt line (keypad) */
|
||||
omap_mux_init_signal("sys_nirq",
|
||||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
||||
|
@ -640,8 +642,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap_3430sdp_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap3430_i2c_init();
|
||||
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
|
||||
if (omap_rev() > OMAP3430_REV_ES1_0)
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include <mach/board-zoom.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-hynix-h8mbx00u0mer-0em.h"
|
||||
|
||||
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||
|
@ -48,7 +49,9 @@ static inline void board_smc91x_init(void)
|
|||
|
||||
static void enable_board_wakeup_source(void)
|
||||
{
|
||||
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
|
||||
/* T2 interrupt line (keypad) */
|
||||
omap_mux_init_signal("sys_nirq",
|
||||
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
||||
|
@ -82,8 +85,17 @@ static void __init omap_sdp_init_irq(void)
|
|||
omap_gpio_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap_sdp_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
|
||||
zoom_peripherals_init();
|
||||
board_smc91x_init();
|
||||
enable_board_wakeup_source();
|
||||
|
|
|
@ -30,6 +30,8 @@
|
|||
#include <plat/common.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "mux.h"
|
||||
|
||||
/*
|
||||
* Board initialization
|
||||
*/
|
||||
|
@ -60,8 +62,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init am3517_evm_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
platform_add_devices(am3517_evm_devices,
|
||||
ARRAY_SIZE(am3517_evm_devices));
|
||||
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/leds.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -120,6 +121,12 @@ static void __init apollon_flash_init(void)
|
|||
apollon_flash_resource[0].end = base + SZ_128K - 1;
|
||||
}
|
||||
|
||||
static struct smc91x_platdata appolon_smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource apollon_smc91x_resources[] = {
|
||||
[0] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
@ -134,6 +141,9 @@ static struct resource apollon_smc91x_resources[] = {
|
|||
static struct platform_device apollon_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &appolon_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(apollon_smc91x_resources),
|
||||
.resource = apollon_smc91x_resources,
|
||||
};
|
||||
|
|
|
@ -38,13 +38,13 @@
|
|||
|
||||
#include <plat/board.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
|
@ -482,8 +482,102 @@ static void __init cm_t35_map_io(void)
|
|||
omap2_map_common_io();
|
||||
}
|
||||
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
/* nCS and IRQ for CM-T35 ethernet */
|
||||
OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
|
||||
OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
|
||||
|
||||
/* nCS and IRQ for SB-T35 ethernet */
|
||||
OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
|
||||
OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
|
||||
|
||||
/* PENDOWN GPIO */
|
||||
OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
|
||||
|
||||
/* mUSB */
|
||||
OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
|
||||
/* MMC 2 */
|
||||
OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
|
||||
|
||||
/* McSPI 1 */
|
||||
OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
|
||||
|
||||
/* McSPI 4 */
|
||||
OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
|
||||
|
||||
/* McBSP 2 */
|
||||
OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
|
||||
/* serial ports */
|
||||
OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
|
||||
OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
|
||||
|
||||
/* DSS */
|
||||
OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
|
||||
|
||||
/* TPS IRQ */
|
||||
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
|
||||
OMAP_PIN_INPUT_PULLUP),
|
||||
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
|
||||
static void __init cm_t35_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
|
||||
omap_serial_init();
|
||||
cm_t35_init_i2c();
|
||||
cm_t35_init_nand();
|
||||
|
@ -492,8 +586,6 @@ static void __init cm_t35_init(void)
|
|||
cm_t35_init_led();
|
||||
|
||||
usb_musb_init();
|
||||
|
||||
omap_cfg_reg(AF26_34XX_SYS_NIRQ);
|
||||
}
|
||||
|
||||
MACHINE_START(CM_T35, "Compulab CM-T35")
|
||||
|
|
|
@ -27,9 +27,9 @@
|
|||
#include <plat/board.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
#define IGEP2_SMSC911X_CS 5
|
||||
|
@ -203,8 +203,17 @@ static int __init igep2_i2c_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init igep2_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
igep2_i2c_init();
|
||||
omap_serial_init();
|
||||
usb_musb_init();
|
||||
|
|
|
@ -43,6 +43,7 @@
|
|||
#include <plat/control.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
#define LDP_SMSC911X_CS 1
|
||||
|
@ -374,8 +375,17 @@ static struct platform_device *ldp_devices[] __initdata = {
|
|||
&ldp_gpio_keys_device,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap_ldp_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_i2c_init();
|
||||
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
|
||||
ts_gpio = 54;
|
||||
|
|
|
@ -41,10 +41,10 @@
|
|||
#include <plat/common.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/timer-gp.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
#define GPMC_CS0_BASE 0x60
|
||||
|
@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
|
|||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
|
||||
omap_cfg_reg(AG9_34XX_GPIO23);
|
||||
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
|
||||
mmc[0].gpio_wp = 23;
|
||||
} else {
|
||||
omap_cfg_reg(AH8_34XX_GPIO29);
|
||||
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
|
||||
}
|
||||
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
|
||||
mmc[0].gpio_cd = gpio + 0;
|
||||
|
@ -422,14 +422,23 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap3_beagle_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap3_beagle_i2c_init();
|
||||
platform_add_devices(omap3_beagle_devices,
|
||||
ARRAY_SIZE(omap3_beagle_devices));
|
||||
omap_serial_init();
|
||||
|
||||
omap_cfg_reg(J25_34XX_GPIO170);
|
||||
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
|
||||
gpio_request(170, "DVI_nPD");
|
||||
/* REVISIT leave DVI powered down until it's needed ... */
|
||||
gpio_direction_output(170, true);
|
||||
|
@ -439,8 +448,8 @@ static void __init omap3_beagle_init(void)
|
|||
omap3beagle_flash_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
|
||||
}
|
||||
|
||||
static void __init omap3_beagle_map_io(void)
|
||||
|
|
|
@ -38,11 +38,11 @@
|
|||
#include <asm/mach/map.h>
|
||||
|
||||
#include <plat/board.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/mcspi.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
|
@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
|
|||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
|
||||
omap_cfg_reg(L8_34XX_GPIO63);
|
||||
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
|
||||
mmc[0].gpio_cd = gpio + 0;
|
||||
twl4030_mmc_init(mmc);
|
||||
|
||||
|
@ -422,9 +422,18 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap3_evm_init(void)
|
||||
{
|
||||
omap3_evm_get_revision();
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
|
||||
omap3_evm_i2c_init();
|
||||
|
||||
|
@ -440,24 +449,24 @@ static void __init omap3_evm_init(void)
|
|||
#endif
|
||||
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
|
||||
/* enable EHCI VBUS using GPIO22 */
|
||||
omap_cfg_reg(AF9_34XX_GPIO22);
|
||||
omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
|
||||
gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
|
||||
gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
|
||||
gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
|
||||
|
||||
/* Select EHCI port on main board */
|
||||
omap_cfg_reg(U3_34XX_GPIO61);
|
||||
omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
|
||||
gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
|
||||
gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
|
||||
gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
|
||||
|
||||
/* setup EHCI phy reset config */
|
||||
omap_cfg_reg(AH14_34XX_GPIO21);
|
||||
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
|
||||
ehci_pdata.reset_gpio_port[1] = 21;
|
||||
|
||||
} else {
|
||||
/* setup EHCI phy reset on MDC */
|
||||
omap_cfg_reg(AF4_34XX_GPIO135_OUT);
|
||||
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
|
||||
ehci_pdata.reset_gpio_port[1] = 135;
|
||||
}
|
||||
usb_musb_init();
|
||||
|
|
|
@ -40,8 +40,8 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <plat/mcspi.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/mux.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
|
@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = {
|
|||
GPIO_BUTTON_LOW(103, KEY_DOWN, "down"),
|
||||
GPIO_BUTTON_LOW(96, KEY_LEFT, "left"),
|
||||
GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"),
|
||||
GPIO_BUTTON_LOW(111, BTN_A, "a"),
|
||||
GPIO_BUTTON_LOW(106, BTN_B, "b"),
|
||||
GPIO_BUTTON_LOW(109, BTN_X, "x"),
|
||||
GPIO_BUTTON_LOW(101, BTN_Y, "y"),
|
||||
GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"),
|
||||
GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"),
|
||||
GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"),
|
||||
GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"),
|
||||
GPIO_BUTTON_LOW(102, BTN_TL, "l"),
|
||||
GPIO_BUTTON_LOW(97, BTN_TL2, "l2"),
|
||||
GPIO_BUTTON_LOW(105, BTN_TR, "r"),
|
||||
|
@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void)
|
|||
omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
|
||||
ARRAY_SIZE(omap3pandora_i2c_boardinfo));
|
||||
/* i2c2 pins are not connected */
|
||||
omap_register_i2c_bus(3, 400, NULL, 0);
|
||||
omap_register_i2c_bus(3, 100, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -368,23 +368,8 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct platform_device omap3pandora_lcd_device = {
|
||||
.name = "pandora_lcd",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
|
||||
.ctrl_name = "internal",
|
||||
};
|
||||
|
||||
static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
|
||||
{ OMAP_TAG_LCD, &omap3pandora_lcd_config },
|
||||
};
|
||||
|
||||
static void __init omap3pandora_init_irq(void)
|
||||
{
|
||||
omap_board_config = omap3pandora_config;
|
||||
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
omap_init_irq();
|
||||
|
@ -392,7 +377,6 @@ static void __init omap3pandora_init_irq(void)
|
|||
}
|
||||
|
||||
static struct platform_device *omap3pandora_devices[] __initdata = {
|
||||
&omap3pandora_lcd_device,
|
||||
&pandora_leds_gpio,
|
||||
&pandora_keys_gpio,
|
||||
};
|
||||
|
@ -409,8 +393,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap3pandora_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap3pandora_i2c_init();
|
||||
platform_add_devices(omap3pandora_devices,
|
||||
ARRAY_SIZE(omap3pandora_devices));
|
||||
|
@ -423,8 +416,8 @@ static void __init omap3pandora_init(void)
|
|||
usb_musb_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
|
||||
}
|
||||
|
||||
static void __init omap3pandora_map_io(void)
|
||||
|
|
572
arch/arm/mach-omap2/board-omap3touchbook.c
Normal file
572
arch/arm/mach-omap2/board-omap3touchbook.c
Normal file
|
@ -0,0 +1,572 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/board-omap3touchbook.c
|
||||
*
|
||||
* Copyright (C) 2009 Always Innovating
|
||||
*
|
||||
* Modified from mach-omap2/board-omap3beagleboard.c
|
||||
*
|
||||
* Initial code: Grégoire Gentil, Tim Yamin
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
#include <plat/mcspi.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <linux/spi/ads7846.h>
|
||||
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/i2c/twl4030.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/flash.h>
|
||||
|
||||
#include <plat/board.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/timer-gp.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
#include <asm/setup.h>
|
||||
|
||||
#define GPMC_CS0_BASE 0x60
|
||||
#define GPMC_CS_SIZE 0x30
|
||||
|
||||
#define NAND_BLOCK_SIZE SZ_128K
|
||||
|
||||
#define OMAP3_AC_GPIO 136
|
||||
#define OMAP3_TS_GPIO 162
|
||||
#define TB_BL_PWM_TIMER 9
|
||||
#define TB_KILL_POWER_GPIO 168
|
||||
|
||||
unsigned long touchbook_revision;
|
||||
|
||||
static struct mtd_partition omap3touchbook_nand_partitions[] = {
|
||||
/* All the partition sizes are listed in terms of NAND block size */
|
||||
{
|
||||
.name = "X-Loader",
|
||||
.offset = 0,
|
||||
.size = 4 * NAND_BLOCK_SIZE,
|
||||
.mask_flags = MTD_WRITEABLE, /* force read-only */
|
||||
},
|
||||
{
|
||||
.name = "U-Boot",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
|
||||
.size = 15 * NAND_BLOCK_SIZE,
|
||||
.mask_flags = MTD_WRITEABLE, /* force read-only */
|
||||
},
|
||||
{
|
||||
.name = "U-Boot Env",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
|
||||
.size = 1 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "Kernel",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
|
||||
.size = 32 * NAND_BLOCK_SIZE,
|
||||
},
|
||||
{
|
||||
.name = "File System",
|
||||
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_nand_platform_data omap3touchbook_nand_data = {
|
||||
.options = NAND_BUSWIDTH_16,
|
||||
.parts = omap3touchbook_nand_partitions,
|
||||
.nr_parts = ARRAY_SIZE(omap3touchbook_nand_partitions),
|
||||
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
|
||||
.nand_setup = NULL,
|
||||
.dev_ready = NULL,
|
||||
};
|
||||
|
||||
static struct resource omap3touchbook_nand_resource = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct platform_device omap3touchbook_nand_device = {
|
||||
.name = "omap2-nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &omap3touchbook_nand_data,
|
||||
},
|
||||
.num_resources = 1,
|
||||
.resource = &omap3touchbook_nand_resource,
|
||||
};
|
||||
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
|
||||
static struct twl4030_hsmmc_info mmc[] = {
|
||||
{
|
||||
.mmc = 1,
|
||||
.wires = 8,
|
||||
.gpio_wp = 29,
|
||||
},
|
||||
{} /* Terminator */
|
||||
};
|
||||
|
||||
static struct platform_device omap3_touchbook_lcd_device = {
|
||||
.name = "omap3touchbook_lcd",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
|
||||
.ctrl_name = "internal",
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply touchbook_vmmc1_supply = {
|
||||
.supply = "vmmc",
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply touchbook_vsim_supply = {
|
||||
.supply = "vmmc_aux",
|
||||
};
|
||||
|
||||
static struct gpio_led gpio_leds[];
|
||||
|
||||
static int touchbook_twl_gpio_setup(struct device *dev,
|
||||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
|
||||
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
|
||||
mmc[0].gpio_wp = 23;
|
||||
} else {
|
||||
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
|
||||
}
|
||||
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
|
||||
mmc[0].gpio_cd = gpio + 0;
|
||||
twl4030_mmc_init(mmc);
|
||||
|
||||
/* link regulators to MMC adapters */
|
||||
touchbook_vmmc1_supply.dev = mmc[0].dev;
|
||||
touchbook_vsim_supply.dev = mmc[0].dev;
|
||||
|
||||
/* REVISIT: need ehci-omap hooks for external VBUS
|
||||
* power switch and overcurrent detect
|
||||
*/
|
||||
|
||||
gpio_request(gpio + 1, "EHCI_nOC");
|
||||
gpio_direction_input(gpio + 1);
|
||||
|
||||
/* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
|
||||
gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
|
||||
gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
|
||||
|
||||
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
|
||||
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct twl4030_gpio_platform_data touchbook_gpio_data = {
|
||||
.gpio_base = OMAP_MAX_GPIO_LINES,
|
||||
.irq_base = TWL4030_GPIO_IRQ_BASE,
|
||||
.irq_end = TWL4030_GPIO_IRQ_END,
|
||||
.use_leds = true,
|
||||
.pullups = BIT(1),
|
||||
.pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
|
||||
| BIT(15) | BIT(16) | BIT(17),
|
||||
.setup = touchbook_twl_gpio_setup,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply touchbook_vdac_supply = {
|
||||
.supply = "vdac",
|
||||
.dev = &omap3_touchbook_lcd_device.dev,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply touchbook_vdvi_supply = {
|
||||
.supply = "vdvi",
|
||||
.dev = &omap3_touchbook_lcd_device.dev,
|
||||
};
|
||||
|
||||
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
|
||||
static struct regulator_init_data touchbook_vmmc1 = {
|
||||
.constraints = {
|
||||
.min_uV = 1850000,
|
||||
.max_uV = 3150000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &touchbook_vmmc1_supply,
|
||||
};
|
||||
|
||||
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
|
||||
static struct regulator_init_data touchbook_vsim = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 3000000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
|
||||
| REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &touchbook_vsim_supply,
|
||||
};
|
||||
|
||||
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
|
||||
static struct regulator_init_data touchbook_vdac = {
|
||||
.constraints = {
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &touchbook_vdac_supply,
|
||||
};
|
||||
|
||||
/* VPLL2 for digital video outputs */
|
||||
static struct regulator_init_data touchbook_vpll2 = {
|
||||
.constraints = {
|
||||
.name = "VDVI",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL
|
||||
| REGULATOR_MODE_STANDBY,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_MODE
|
||||
| REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &touchbook_vdvi_supply,
|
||||
};
|
||||
|
||||
static struct twl4030_usb_data touchbook_usb_data = {
|
||||
.usb_mode = T2_USB_MODE_ULPI,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_audio_data touchbook_audio_data = {
|
||||
.audio_mclk = 26000000,
|
||||
};
|
||||
|
||||
static struct twl4030_codec_data touchbook_codec_data = {
|
||||
.audio_mclk = 26000000,
|
||||
.audio = &touchbook_audio_data,
|
||||
};
|
||||
|
||||
static struct twl4030_platform_data touchbook_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
|
||||
/* platform_data for children goes here */
|
||||
.usb = &touchbook_usb_data,
|
||||
.gpio = &touchbook_gpio_data,
|
||||
.codec = &touchbook_codec_data,
|
||||
.vmmc1 = &touchbook_vmmc1,
|
||||
.vsim = &touchbook_vsim,
|
||||
.vdac = &touchbook_vdac,
|
||||
.vpll2 = &touchbook_vpll2,
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("twl4030", 0x48),
|
||||
.flags = I2C_CLIENT_WAKE,
|
||||
.irq = INT_34XX_SYS_NIRQ,
|
||||
.platform_data = &touchbook_twldata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
|
||||
{
|
||||
I2C_BOARD_INFO("bq27200", 0x55),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init omap3_touchbook_i2c_init(void)
|
||||
{
|
||||
/* Standard TouchBook bus */
|
||||
omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
|
||||
ARRAY_SIZE(touchbook_i2c_boardinfo));
|
||||
|
||||
/* Additional TouchBook bus */
|
||||
omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
|
||||
ARRAY_SIZE(touchBook_i2c_boardinfo));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init omap3_ads7846_init(void)
|
||||
{
|
||||
if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
|
||||
printk(KERN_ERR "Failed to request GPIO %d for "
|
||||
"ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
|
||||
return;
|
||||
}
|
||||
|
||||
gpio_direction_input(OMAP3_TS_GPIO);
|
||||
omap_set_gpio_debounce(OMAP3_TS_GPIO, 1);
|
||||
omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa);
|
||||
}
|
||||
|
||||
static struct ads7846_platform_data ads7846_config = {
|
||||
.x_min = 100,
|
||||
.y_min = 265,
|
||||
.x_max = 3950,
|
||||
.y_max = 3750,
|
||||
.x_plate_ohms = 40,
|
||||
.pressure_max = 255,
|
||||
.debounce_max = 10,
|
||||
.debounce_tol = 5,
|
||||
.debounce_rep = 1,
|
||||
.gpio_pendown = OMAP3_TS_GPIO,
|
||||
.keep_vref_on = 1,
|
||||
};
|
||||
|
||||
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
|
||||
.turbo_mode = 0,
|
||||
.single_channel = 1, /* 0: slave, 1: master */
|
||||
};
|
||||
|
||||
static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
|
||||
{
|
||||
.modalias = "ads7846",
|
||||
.bus_num = 4,
|
||||
.chip_select = 0,
|
||||
.max_speed_hz = 1500000,
|
||||
.controller_data = &ads7846_mcspi_config,
|
||||
.irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
|
||||
.platform_data = &ads7846_config,
|
||||
}
|
||||
};
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
{
|
||||
.name = "touchbook::usr0",
|
||||
.default_trigger = "heartbeat",
|
||||
.gpio = 150,
|
||||
},
|
||||
{
|
||||
.name = "touchbook::usr1",
|
||||
.default_trigger = "mmc0",
|
||||
.gpio = 149,
|
||||
},
|
||||
{
|
||||
.name = "touchbook::pmu_stat",
|
||||
.gpio = -EINVAL, /* gets replaced */
|
||||
.active_low = true,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_led_info = {
|
||||
.leds = gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device leds_gpio = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_led_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
{
|
||||
.code = BTN_EXTRA,
|
||||
.gpio = 7,
|
||||
.desc = "user",
|
||||
.wakeup = 1,
|
||||
},
|
||||
{
|
||||
.code = KEY_POWER,
|
||||
.gpio = 183,
|
||||
.desc = "power",
|
||||
.wakeup = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gpio_key_info = {
|
||||
.buttons = gpio_buttons,
|
||||
.nbuttons = ARRAY_SIZE(gpio_buttons),
|
||||
};
|
||||
|
||||
static struct platform_device keys_gpio = {
|
||||
.name = "gpio-keys",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_key_info,
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
|
||||
{ OMAP_TAG_LCD, &omap3_touchbook_lcd_config },
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap3_touchbook_init_irq(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_board_config = omap3_touchbook_config;
|
||||
omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
|
||||
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
omap_init_irq();
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
omap2_gp_clockevent_set_gptimer(12);
|
||||
#endif
|
||||
omap_gpio_init();
|
||||
}
|
||||
|
||||
static struct platform_device *omap3_touchbook_devices[] __initdata = {
|
||||
&omap3_touchbook_lcd_device,
|
||||
&leds_gpio,
|
||||
&keys_gpio,
|
||||
};
|
||||
|
||||
static void __init omap3touchbook_flash_init(void)
|
||||
{
|
||||
u8 cs = 0;
|
||||
u8 nandcs = GPMC_CS_NUM + 1;
|
||||
|
||||
u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
|
||||
|
||||
/* find out the chip-select on which NAND exists */
|
||||
while (cs < GPMC_CS_NUM) {
|
||||
u32 ret = 0;
|
||||
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
|
||||
|
||||
if ((ret & 0xC00) == 0x800) {
|
||||
printk(KERN_INFO "Found NAND on CS%d\n", cs);
|
||||
if (nandcs > GPMC_CS_NUM)
|
||||
nandcs = cs;
|
||||
}
|
||||
cs++;
|
||||
}
|
||||
|
||||
if (nandcs > GPMC_CS_NUM) {
|
||||
printk(KERN_INFO "NAND: Unable to find configuration "
|
||||
"in GPMC\n ");
|
||||
return;
|
||||
}
|
||||
|
||||
if (nandcs < GPMC_CS_NUM) {
|
||||
omap3touchbook_nand_data.cs = nandcs;
|
||||
omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *)
|
||||
(gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
|
||||
omap3touchbook_nand_data.gpmc_baseaddr =
|
||||
(void *) (gpmc_base_add);
|
||||
|
||||
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
|
||||
if (platform_device_register(&omap3touchbook_nand_device) < 0)
|
||||
printk(KERN_ERR "Unable to register NAND device\n");
|
||||
}
|
||||
}
|
||||
|
||||
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
||||
|
||||
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
|
||||
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
|
||||
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
|
||||
|
||||
.phy_reset = true,
|
||||
.reset_gpio_port[0] = -EINVAL,
|
||||
.reset_gpio_port[1] = 147,
|
||||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
static void omap3_touchbook_poweroff(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
|
||||
if (r < 0) {
|
||||
printk(KERN_ERR "Unable to get kill power GPIO\n");
|
||||
return;
|
||||
}
|
||||
|
||||
gpio_direction_output(TB_KILL_POWER_GPIO, 0);
|
||||
}
|
||||
|
||||
static void __init early_touchbook_revision(char **p)
|
||||
{
|
||||
if (!*p)
|
||||
return;
|
||||
|
||||
strict_strtoul(*p, 10, &touchbook_revision);
|
||||
}
|
||||
__early_param("tbr=", early_touchbook_revision);
|
||||
|
||||
static void __init omap3_touchbook_init(void)
|
||||
{
|
||||
pm_power_off = omap3_touchbook_poweroff;
|
||||
|
||||
omap3_touchbook_i2c_init();
|
||||
platform_add_devices(omap3_touchbook_devices,
|
||||
ARRAY_SIZE(omap3_touchbook_devices));
|
||||
omap_serial_init();
|
||||
|
||||
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
|
||||
gpio_request(176, "DVI_nPD");
|
||||
/* REVISIT leave DVI powered down until it's needed ... */
|
||||
gpio_direction_output(176, true);
|
||||
|
||||
/* Touchscreen and accelerometer */
|
||||
spi_register_board_info(omap3_ads7846_spi_board_info,
|
||||
ARRAY_SIZE(omap3_ads7846_spi_board_info));
|
||||
omap3_ads7846_init();
|
||||
usb_musb_init();
|
||||
usb_ehci_init(&ehci_pdata);
|
||||
omap3touchbook_flash_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
|
||||
}
|
||||
|
||||
static void __init omap3_touchbook_map_io(void)
|
||||
{
|
||||
omap2_set_globals_343x();
|
||||
omap2_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
|
||||
/* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
|
||||
.phys_io = 0x48000000,
|
||||
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = omap3_touchbook_map_io,
|
||||
.init_irq = omap3_touchbook_init_irq,
|
||||
.init_machine = omap3_touchbook_init,
|
||||
.timer = &omap_timer,
|
||||
MACHINE_END
|
|
@ -44,9 +44,9 @@
|
|||
#include <plat/gpmc.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <plat/nand.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
|
@ -405,9 +405,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
|
|||
.reset_gpio_port[2] = -EINVAL
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init overo_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
overo_i2c_init();
|
||||
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
|
||||
omap_serial_init();
|
||||
|
@ -418,8 +426,8 @@ static void __init overo_init(void)
|
|||
overo_init_smsc911x();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
|
||||
|
||||
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
|
||||
"OVERO_GPIO_W2W_NRESET") == 0) &&
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include <plat/onenand.h>
|
||||
#include <plat/gpmc-smc91x.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "mmc-twl4030.h"
|
||||
|
||||
#define SYSTEM_REV_B_USES_VAUX3 0x1699
|
||||
|
@ -59,7 +60,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
|
|||
.bus_num = 4,
|
||||
.chip_select = 0,
|
||||
.max_speed_hz = 48000000,
|
||||
.mode = SPI_MODE_2,
|
||||
.mode = SPI_MODE_3,
|
||||
.controller_data = &wl1251_mcspi_config,
|
||||
.platform_data = &wl1251_pdata,
|
||||
},
|
||||
|
@ -630,9 +631,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = {
|
|||
|
||||
static void __init board_smc91x_init(void)
|
||||
{
|
||||
omap_cfg_reg(U8_34XX_GPIO54_DOWN);
|
||||
omap_cfg_reg(G25_34XX_GPIO86_OUT);
|
||||
omap_cfg_reg(H19_34XX_GPIO164_OUT);
|
||||
omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
|
||||
|
||||
gpmc_smc91x_init(&board_smc91x_data);
|
||||
}
|
||||
|
|
|
@ -23,13 +23,14 @@
|
|||
#include <asm/mach/map.h>
|
||||
|
||||
#include <plat/mcspi.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/board.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "mux.h"
|
||||
|
||||
struct omap_sdrc_params *rx51_get_sdram_timings(void);
|
||||
|
||||
static struct omap_lcd_config rx51_lcd_config = {
|
||||
|
@ -69,15 +70,24 @@ static void __init rx51_init_irq(void)
|
|||
|
||||
extern void __init rx51_peripherals_init(void);
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init rx51_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_serial_init();
|
||||
usb_musb_init();
|
||||
rx51_peripherals_init();
|
||||
|
||||
/* Ensure SDRC pins are mux'd for self-refresh */
|
||||
omap_cfg_reg(H16_34XX_SDRC_CKE0);
|
||||
omap_cfg_reg(H17_34XX_SDRC_CKE1);
|
||||
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
|
||||
}
|
||||
|
||||
static void __init rx51_map_io(void)
|
||||
|
|
|
@ -152,14 +152,20 @@ static struct regulator_init_data zoom_vsim = {
|
|||
|
||||
static struct twl4030_hsmmc_info mmc[] __initdata = {
|
||||
{
|
||||
.name = "external",
|
||||
.mmc = 1,
|
||||
.wires = 4,
|
||||
.gpio_wp = -EINVAL,
|
||||
.power_saving = true,
|
||||
},
|
||||
{
|
||||
.name = "internal",
|
||||
.mmc = 2,
|
||||
.wires = 4,
|
||||
.wires = 8,
|
||||
.gpio_cd = -EINVAL,
|
||||
.gpio_wp = -EINVAL,
|
||||
.nonremovable = true,
|
||||
.power_saving = true,
|
||||
},
|
||||
{} /* Terminator */
|
||||
};
|
||||
|
@ -167,11 +173,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
|
|||
static int zoom_twl_gpio_setup(struct device *dev,
|
||||
unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
/* gpio + 0 is "mmc0_cd" (input/IRQ),
|
||||
* gpio + 1 is "mmc1_cd" (input/IRQ)
|
||||
*/
|
||||
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
|
||||
mmc[0].gpio_cd = gpio + 0;
|
||||
mmc[1].gpio_cd = gpio + 1;
|
||||
twl4030_mmc_init(mmc);
|
||||
|
||||
/* link regulators to MMC adapters ... we "know" the
|
||||
|
@ -236,6 +239,7 @@ static struct twl4030_platform_data zoom_twldata = {
|
|||
.gpio = &zoom_gpio_data,
|
||||
.keypad = &zoom_kp_twl4030_data,
|
||||
.codec = &zoom_codec_data,
|
||||
.vmmc1 = &zoom_vmmc1,
|
||||
.vmmc2 = &zoom_vmmc2,
|
||||
.vsim = &zoom_vsim,
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include <mach/board-zoom.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-micron-mt46h32m32lf-6.h"
|
||||
|
||||
static void __init omap_zoom2_init_irq(void)
|
||||
|
@ -68,8 +69,17 @@ static struct twl4030_platform_data zoom2_twldata = {
|
|||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap_zoom2_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
zoom_peripherals_init();
|
||||
zoom_debugboard_init();
|
||||
}
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <plat/common.h>
|
||||
#include <plat/board.h>
|
||||
|
||||
#include "mux.h"
|
||||
#include "sdram-hynix-h8mbx00u0mer-0em.h"
|
||||
|
||||
static void __init omap_zoom_map_io(void)
|
||||
|
@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void)
|
|||
omap_gpio_init();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#else
|
||||
#define board_mux NULL
|
||||
#endif
|
||||
|
||||
static void __init omap_zoom_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
|
||||
zoom_peripherals_init();
|
||||
zoom_debugboard_init();
|
||||
}
|
||||
|
|
|
@ -70,9 +70,41 @@
|
|||
u8 cpu_mask;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* OMAP2/3 specific clock functions
|
||||
* OMAP2/3/4 specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
void omap2_init_dpll_parent(struct clk *clk)
|
||||
{
|
||||
u32 v;
|
||||
struct dpll_data *dd;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return;
|
||||
|
||||
/* Return bypass rate if DPLL is bypassed */
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v &= dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
|
||||
/* Reparent in case the dpll is in bypass */
|
||||
if (cpu_is_omap24xx()) {
|
||||
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
|
||||
clk_reparent(clk, dd->clk_bypass);
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||
clk_reparent(clk, dd->clk_bypass);
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||
clk_reparent(clk, dd->clk_bypass);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
|
||||
* @clk: struct clk *
|
||||
|
@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
|
|||
* clockdomain pointer, and save it into the struct clk. Intended to be
|
||||
* called during clk_register(). No return value.
|
||||
*/
|
||||
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
|
||||
void omap2_init_clk_clkdm(struct clk *clk)
|
||||
{
|
||||
struct clockdomain *clkdm;
|
||||
|
@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk)
|
|||
"clkdm %s\n", clk->name, clk->clkdm_name);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
|
||||
|
@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
|
|||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||
return dd->clk_bypass->rate;
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||
return dd->clk_bypass->rate;
|
||||
}
|
||||
|
||||
v = __raw_readl(dd->mult_div1_reg);
|
||||
|
@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk)
|
|||
_omap2_clk_disable(clk);
|
||||
if (clk->parent)
|
||||
omap2_clk_disable(clk->parent);
|
||||
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
|
||||
if (clk->clkdm)
|
||||
omap2_clkdm_clk_disable(clk->clkdm, clk);
|
||||
#endif
|
||||
|
||||
}
|
||||
}
|
||||
|
@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk)
|
|||
int ret = 0;
|
||||
|
||||
if (clk->usecount++ == 0) {
|
||||
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
|
||||
if (clk->clkdm)
|
||||
omap2_clkdm_clk_enable(clk->clkdm, clk);
|
||||
#endif
|
||||
|
||||
if (clk->parent) {
|
||||
ret = omap2_clk_enable(clk->parent);
|
||||
|
@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk)
|
|||
return ret;
|
||||
|
||||
err:
|
||||
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
|
||||
if (clk->clkdm)
|
||||
omap2_clkdm_clk_disable(clk->clkdm, clk);
|
||||
#endif
|
||||
clk->usecount--;
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -1,8 +1,8 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/clock.h
|
||||
*
|
||||
* Copyright (C) 2005-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2008 Nokia Corporation
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*
|
||||
* Contacts:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
|
@ -36,6 +36,17 @@
|
|||
#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
|
||||
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
|
||||
|
||||
/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
|
||||
#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
|
||||
#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
|
||||
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
|
||||
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
|
||||
|
||||
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
|
||||
#define DPLL_LOW_POWER_STOP 0x1
|
||||
#define DPLL_LOW_POWER_BYPASS 0x5
|
||||
#define DPLL_LOCKED 0x7
|
||||
|
||||
int omap2_clk_init(void);
|
||||
int omap2_clk_enable(struct clk *clk);
|
||||
void omap2_clk_disable(struct clk *clk);
|
||||
|
@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
|
|||
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
|
||||
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
|
||||
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
|
||||
unsigned long omap3_dpll_recalc(struct clk *clk);
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
|
||||
void omap3_dpll_allow_idle(struct clk *clk);
|
||||
void omap3_dpll_deny_idle(struct clk *clk);
|
||||
u32 omap3_dpll_autoidle_read(struct clk *clk);
|
||||
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
|
||||
int omap3_noncore_dpll_enable(struct clk *clk);
|
||||
void omap3_noncore_dpll_disable(struct clk *clk);
|
||||
|
||||
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
||||
void omap2_clk_disable_unused(struct clk *clk);
|
||||
|
@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
|
|||
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
|
||||
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
|
||||
u32 omap2_get_dpll_rate(struct clk *clk);
|
||||
void omap2_init_dpll_parent(struct clk *clk);
|
||||
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
|
||||
void omap2_clk_prepare_for_reboot(void);
|
||||
int omap2_dflt_clk_enable(struct clk *clk);
|
||||
|
@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
|
|||
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
|
||||
extern u8 cpu_mask;
|
||||
|
||||
extern const struct clkops clkops_omap2_dflt_wait;
|
||||
extern const struct clkops clkops_omap2_dflt;
|
||||
|
||||
extern u8 cpu_mask;
|
||||
extern struct clk_functions omap2_clk_functions;
|
||||
extern struct clk *vclk, *sclk;
|
||||
|
||||
/* clksel_rate data common to 24xx/343x */
|
||||
static const struct clksel_rate gpt_32k_rates[] = {
|
||||
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
|
||||
{ .div = 0 }
|
||||
};
|
||||
|
||||
static const struct clksel_rate gpt_sys_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
|
||||
{ .div = 0 }
|
||||
};
|
||||
|
||||
static const struct clksel_rate gfx_l3_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
|
||||
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
|
||||
{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
|
||||
{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
|
||||
{ .div = 0 }
|
||||
};
|
||||
extern const struct clksel_rate gpt_32k_rates[];
|
||||
extern const struct clksel_rate gpt_sys_rates[];
|
||||
extern const struct clksel_rate gfx_l3_rates[];
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
@ -1,805 +0,0 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/clock.c
|
||||
*
|
||||
* Copyright (C) 2005-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2008 Nokia Corporation
|
||||
*
|
||||
* Contacts:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Paul Walmsley
|
||||
*
|
||||
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
|
||||
* Gordon McNutt and RidgeRun, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <plat/clock.h>
|
||||
#include <plat/sram.h>
|
||||
#include <plat/prcm.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
#include <plat/sdrc.h>
|
||||
#include "clock.h"
|
||||
#include "prm.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
|
||||
static const struct clkops clkops_oscck;
|
||||
static const struct clkops clkops_fixed;
|
||||
|
||||
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit);
|
||||
|
||||
/* 2430 I2CHS has non-standard IDLEST register */
|
||||
static const struct clkops clkops_omap2430_i2chs_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_idlest = omap2430_clk_i2chs_find_idlest,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
};
|
||||
|
||||
#include "clock24xx.h"
|
||||
|
||||
struct omap_clk {
|
||||
u32 cpu;
|
||||
struct clk_lookup lk;
|
||||
};
|
||||
|
||||
#define CLK(dev, con, ck, cp) \
|
||||
{ \
|
||||
.cpu = cp, \
|
||||
.lk = { \
|
||||
.dev_id = dev, \
|
||||
.con_id = con, \
|
||||
.clk = ck, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define CK_243X RATE_IN_243X
|
||||
#define CK_242X RATE_IN_242X
|
||||
|
||||
static struct omap_clk omap24xx_clks[] = {
|
||||
/* external root sources */
|
||||
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
|
||||
/* internal analog sources */
|
||||
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
|
||||
/* internal prcm root sources */
|
||||
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
|
||||
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
|
||||
CLK(NULL, "emul_ck", &emul_ck, CK_242X),
|
||||
/* mpu domain clocks */
|
||||
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
|
||||
/* dsp domain clocks */
|
||||
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
|
||||
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
|
||||
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
|
||||
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
|
||||
/* GFX domain clocks */
|
||||
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
|
||||
/* Modem domain clocks */
|
||||
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
|
||||
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
|
||||
/* DSS domain clocks */
|
||||
CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
|
||||
CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
|
||||
CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
|
||||
CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
|
||||
/* L3 domain clocks */
|
||||
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
|
||||
/* L4 domain clocks */
|
||||
CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
|
||||
/* virtual meta-group clock */
|
||||
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
|
||||
/* general l4 interface ck, multi-parent functional clk */
|
||||
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
|
||||
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
|
||||
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
|
||||
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
|
||||
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
|
||||
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
|
||||
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
|
||||
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
|
||||
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
|
||||
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
|
||||
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
|
||||
CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
|
||||
CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
|
||||
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
|
||||
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
|
||||
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
|
||||
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
|
||||
CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
|
||||
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
|
||||
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
|
||||
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
|
||||
CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
|
||||
CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
|
||||
CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
|
||||
CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
|
||||
CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
|
||||
CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
|
||||
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
|
||||
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
|
||||
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
|
||||
CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
|
||||
CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
|
||||
CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
|
||||
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
|
||||
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
|
||||
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
|
||||
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
|
||||
CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
|
||||
};
|
||||
|
||||
/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
|
||||
#define EN_APLL_STOPPED 0
|
||||
#define EN_APLL_LOCKED 3
|
||||
|
||||
/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
|
||||
#define APLLS_CLKIN_19_2MHZ 0
|
||||
#define APLLS_CLKIN_13MHZ 2
|
||||
#define APLLS_CLKIN_12MHZ 3
|
||||
|
||||
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
|
||||
|
||||
static struct prcm_config *curr_prcm_set;
|
||||
static struct clk *vclk;
|
||||
static struct clk *sclk;
|
||||
|
||||
static void __iomem *prcm_clksrc_ctrl;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap24xx specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
|
||||
* @clk: struct clk * being enabled
|
||||
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
||||
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
||||
*
|
||||
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
|
||||
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
|
||||
* passes back the correct CM_IDLEST register address for I2CHS
|
||||
* modules. No return value.
|
||||
*/
|
||||
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
|
||||
*idlest_bit = clk->enable_bit;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
|
||||
* @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
|
||||
*
|
||||
* Returns the CORE_CLK rate. CORE_CLK can have one of three rate
|
||||
* sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
|
||||
* (the latter is unusual). This currently should be called with
|
||||
* struct clk *dpll_ck, which is a composite clock of dpll_ck and
|
||||
* core_ck.
|
||||
*/
|
||||
static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
|
||||
{
|
||||
long long core_clk;
|
||||
u32 v;
|
||||
|
||||
core_clk = omap2_get_dpll_rate(clk);
|
||||
|
||||
v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
v &= OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
|
||||
if (v == CORE_CLK_SRC_32K)
|
||||
core_clk = 32768;
|
||||
else
|
||||
core_clk *= v;
|
||||
|
||||
return core_clk;
|
||||
}
|
||||
|
||||
static int omap2_enable_osc_ck(struct clk *clk)
|
||||
{
|
||||
u32 pcc;
|
||||
|
||||
pcc = __raw_readl(prcm_clksrc_ctrl);
|
||||
|
||||
__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap2_disable_osc_ck(struct clk *clk)
|
||||
{
|
||||
u32 pcc;
|
||||
|
||||
pcc = __raw_readl(prcm_clksrc_ctrl);
|
||||
|
||||
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
|
||||
}
|
||||
|
||||
static const struct clkops clkops_oscck = {
|
||||
.enable = &omap2_enable_osc_ck,
|
||||
.disable = &omap2_disable_osc_ck,
|
||||
};
|
||||
|
||||
#ifdef OLD_CK
|
||||
/* Recalculate SYST_CLK */
|
||||
static void omap2_sys_clk_recalc(struct clk * clk)
|
||||
{
|
||||
u32 div = PRCM_CLKSRC_CTRL;
|
||||
div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
|
||||
div >>= clk->rate_offset;
|
||||
clk->rate = (clk->parent->rate / div);
|
||||
propagate_rate(clk);
|
||||
}
|
||||
#endif /* OLD_CK */
|
||||
|
||||
/* Enable an APLL if off */
|
||||
static int omap2_clk_fixed_enable(struct clk *clk)
|
||||
{
|
||||
u32 cval, apll_mask;
|
||||
|
||||
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
|
||||
|
||||
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
||||
|
||||
if ((cval & apll_mask) == apll_mask)
|
||||
return 0; /* apll already enabled */
|
||||
|
||||
cval &= ~apll_mask;
|
||||
cval |= apll_mask;
|
||||
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
|
||||
|
||||
if (clk == &apll96_ck)
|
||||
cval = OMAP24XX_ST_96M_APLL;
|
||||
else if (clk == &apll54_ck)
|
||||
cval = OMAP24XX_ST_54M_APLL;
|
||||
|
||||
omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
|
||||
clk->name);
|
||||
|
||||
/*
|
||||
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
|
||||
* fails?
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Stop APLL */
|
||||
static void omap2_clk_fixed_disable(struct clk *clk)
|
||||
{
|
||||
u32 cval;
|
||||
|
||||
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
||||
cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
|
||||
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
|
||||
}
|
||||
|
||||
static const struct clkops clkops_fixed = {
|
||||
.enable = &omap2_clk_fixed_enable,
|
||||
.disable = &omap2_clk_fixed_disable,
|
||||
};
|
||||
|
||||
/*
|
||||
* Uses the current prcm set to tell if a rate is valid.
|
||||
* You can go slower, but not faster within a given rate set.
|
||||
*/
|
||||
static long omap2_dpllcore_round_rate(unsigned long target_rate)
|
||||
{
|
||||
u32 high, low, core_clk_src;
|
||||
|
||||
core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
|
||||
if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
|
||||
high = curr_prcm_set->dpll_speed * 2;
|
||||
low = curr_prcm_set->dpll_speed;
|
||||
} else { /* DPLL clockout x 2 */
|
||||
high = curr_prcm_set->dpll_speed;
|
||||
low = curr_prcm_set->dpll_speed / 2;
|
||||
}
|
||||
|
||||
#ifdef DOWN_VARIABLE_DPLL
|
||||
if (target_rate > high)
|
||||
return high;
|
||||
else
|
||||
return target_rate;
|
||||
#else
|
||||
if (target_rate > low)
|
||||
return high;
|
||||
else
|
||||
return low;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static unsigned long omap2_dpllcore_recalc(struct clk *clk)
|
||||
{
|
||||
return omap2xxx_clk_get_core_rate(clk);
|
||||
}
|
||||
|
||||
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 cur_rate, low, mult, div, valid_rate, done_rate;
|
||||
u32 bypass = 0;
|
||||
struct prcm_config tmpset;
|
||||
const struct dpll_data *dd;
|
||||
|
||||
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
|
||||
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
|
||||
if ((rate == (cur_rate / 2)) && (mult == 2)) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
|
||||
} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
} else if (rate != cur_rate) {
|
||||
valid_rate = omap2_dpllcore_round_rate(rate);
|
||||
if (valid_rate != rate)
|
||||
return -EINVAL;
|
||||
|
||||
if (mult == 1)
|
||||
low = curr_prcm_set->dpll_speed;
|
||||
else
|
||||
low = curr_prcm_set->dpll_speed / 2;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
|
||||
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
|
||||
dd->div1_mask);
|
||||
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
|
||||
tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
if (rate > low) {
|
||||
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
|
||||
mult = ((rate / 2) / 1000000);
|
||||
done_rate = CORE_CLK_SRC_DPLL_X2;
|
||||
} else {
|
||||
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
|
||||
mult = (rate / 1000000);
|
||||
done_rate = CORE_CLK_SRC_DPLL;
|
||||
}
|
||||
tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
|
||||
tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
|
||||
|
||||
/* Worst case */
|
||||
tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
|
||||
|
||||
if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
|
||||
bypass = 1;
|
||||
|
||||
/* For omap2xxx_sdrc_init_params() */
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
|
||||
/* Force dll lock mode */
|
||||
omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
|
||||
bypass);
|
||||
|
||||
/* Errata: ret dll entry state */
|
||||
omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
|
||||
omap2xxx_sdrc_reprogram(done_rate, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_table_mpu_recalc - just return the MPU speed
|
||||
* @clk: virt_prcm_set struct clk
|
||||
*
|
||||
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
|
||||
*/
|
||||
static unsigned long omap2_table_mpu_recalc(struct clk *clk)
|
||||
{
|
||||
return curr_prcm_set->mpu_speed;
|
||||
}
|
||||
|
||||
/*
|
||||
* Look for a rate equal or less than the target rate given a configuration set.
|
||||
*
|
||||
* What's not entirely clear is "which" field represents the key field.
|
||||
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
|
||||
* just uses the ARM rates.
|
||||
*/
|
||||
static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct prcm_config *ptr;
|
||||
long highest_rate;
|
||||
|
||||
if (clk != &virt_prcm_set)
|
||||
return -EINVAL;
|
||||
|
||||
highest_rate = -EINVAL;
|
||||
|
||||
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
|
||||
if (!(ptr->flags & cpu_mask))
|
||||
continue;
|
||||
if (ptr->xtal_speed != sys_ck.rate)
|
||||
continue;
|
||||
|
||||
highest_rate = ptr->mpu_speed;
|
||||
|
||||
/* Can check only after xtal frequency check */
|
||||
if (ptr->mpu_speed <= rate)
|
||||
break;
|
||||
}
|
||||
return highest_rate;
|
||||
}
|
||||
|
||||
/* Sets basic clocks based on the specified rate */
|
||||
static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 cur_rate, done_rate, bypass = 0, tmp;
|
||||
struct prcm_config *prcm;
|
||||
unsigned long found_speed = 0;
|
||||
unsigned long flags;
|
||||
|
||||
if (clk != &virt_prcm_set)
|
||||
return -EINVAL;
|
||||
|
||||
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
||||
if (!(prcm->flags & cpu_mask))
|
||||
continue;
|
||||
|
||||
if (prcm->xtal_speed != sys_ck.rate)
|
||||
continue;
|
||||
|
||||
if (prcm->mpu_speed <= rate) {
|
||||
found_speed = prcm->mpu_speed;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!found_speed) {
|
||||
printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
|
||||
rate / 1000000);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
curr_prcm_set = prcm;
|
||||
cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
|
||||
|
||||
if (prcm->dpll_speed == cur_rate / 2) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
|
||||
} else if (prcm->dpll_speed == cur_rate * 2) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
} else if (prcm->dpll_speed != cur_rate) {
|
||||
local_irq_save(flags);
|
||||
|
||||
if (prcm->dpll_speed == prcm->xtal_speed)
|
||||
bypass = 1;
|
||||
|
||||
if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
|
||||
CORE_CLK_SRC_DPLL_X2)
|
||||
done_rate = CORE_CLK_SRC_DPLL_X2;
|
||||
else
|
||||
done_rate = CORE_CLK_SRC_DPLL;
|
||||
|
||||
/* MPU divider */
|
||||
cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
|
||||
|
||||
/* dsp + iva1 div(2420), iva2.1(2430) */
|
||||
cm_write_mod_reg(prcm->cm_clksel_dsp,
|
||||
OMAP24XX_DSP_MOD, CM_CLKSEL);
|
||||
|
||||
cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
|
||||
|
||||
/* Major subsystem dividers */
|
||||
tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
|
||||
cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
|
||||
CM_CLKSEL1);
|
||||
|
||||
if (cpu_is_omap2430())
|
||||
cm_write_mod_reg(prcm->cm_clksel_mdm,
|
||||
OMAP2430_MDM_MOD, CM_CLKSEL);
|
||||
|
||||
/* x2 to enter omap2xxx_sdrc_init_params() */
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
|
||||
omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
|
||||
bypass);
|
||||
|
||||
omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
|
||||
omap2xxx_sdrc_reprogram(done_rate, 0);
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
/*
|
||||
* Walk PRCM rate table and fillout cpufreq freq_table
|
||||
*/
|
||||
static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
|
||||
|
||||
void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
|
||||
{
|
||||
struct prcm_config *prcm;
|
||||
int i = 0;
|
||||
|
||||
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
||||
if (!(prcm->flags & cpu_mask))
|
||||
continue;
|
||||
if (prcm->xtal_speed != sys_ck.rate)
|
||||
continue;
|
||||
|
||||
/* don't put bypass rates in table */
|
||||
if (prcm->dpll_speed == prcm->xtal_speed)
|
||||
continue;
|
||||
|
||||
freq_table[i].index = i;
|
||||
freq_table[i].frequency = prcm->mpu_speed / 1000;
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
printk(KERN_WARNING "%s: failed to initialize frequency "
|
||||
"table\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
freq_table[i].index = i;
|
||||
freq_table[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
*table = &freq_table[0];
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct clk_functions omap2_clk_functions = {
|
||||
.clk_enable = omap2_clk_enable,
|
||||
.clk_disable = omap2_clk_disable,
|
||||
.clk_round_rate = omap2_clk_round_rate,
|
||||
.clk_set_rate = omap2_clk_set_rate,
|
||||
.clk_set_parent = omap2_clk_set_parent,
|
||||
.clk_disable_unused = omap2_clk_disable_unused,
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
.clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
|
||||
#endif
|
||||
};
|
||||
|
||||
static u32 omap2_get_apll_clkin(void)
|
||||
{
|
||||
u32 aplls, srate = 0;
|
||||
|
||||
aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
|
||||
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
|
||||
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
|
||||
|
||||
if (aplls == APLLS_CLKIN_19_2MHZ)
|
||||
srate = 19200000;
|
||||
else if (aplls == APLLS_CLKIN_13MHZ)
|
||||
srate = 13000000;
|
||||
else if (aplls == APLLS_CLKIN_12MHZ)
|
||||
srate = 12000000;
|
||||
|
||||
return srate;
|
||||
}
|
||||
|
||||
static u32 omap2_get_sysclkdiv(void)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
div = __raw_readl(prcm_clksrc_ctrl);
|
||||
div &= OMAP_SYSCLKDIV_MASK;
|
||||
div >>= OMAP_SYSCLKDIV_SHIFT;
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
static unsigned long omap2_osc_clk_recalc(struct clk *clk)
|
||||
{
|
||||
return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
|
||||
}
|
||||
|
||||
static unsigned long omap2_sys_clk_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / omap2_get_sysclkdiv();
|
||||
}
|
||||
|
||||
/*
|
||||
* Set clocks for bypass mode for reboot to work.
|
||||
*/
|
||||
void omap2_clk_prepare_for_reboot(void)
|
||||
{
|
||||
u32 rate;
|
||||
|
||||
if (vclk == NULL || sclk == NULL)
|
||||
return;
|
||||
|
||||
rate = clk_get_rate(sclk);
|
||||
clk_set_rate(vclk, rate);
|
||||
}
|
||||
|
||||
/*
|
||||
* Switch the MPU rate if specified on cmdline.
|
||||
* We cannot do this early until cmdline is parsed.
|
||||
*/
|
||||
static int __init omap2_clk_arch_init(void)
|
||||
{
|
||||
if (!mpurate)
|
||||
return -EINVAL;
|
||||
|
||||
if (clk_set_rate(&virt_prcm_set, mpurate))
|
||||
printk(KERN_ERR "Could not find matching MPU rate\n");
|
||||
|
||||
recalculate_root_clocks();
|
||||
|
||||
printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
|
||||
"%ld.%01ld/%ld/%ld MHz\n",
|
||||
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
||||
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap2_clk_arch_init);
|
||||
|
||||
int __init omap2_clk_init(void)
|
||||
{
|
||||
struct prcm_config *prcm;
|
||||
struct omap_clk *c;
|
||||
u32 clkrate;
|
||||
|
||||
if (cpu_is_omap242x()) {
|
||||
prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
|
||||
cpu_mask = RATE_IN_242X;
|
||||
} else if (cpu_is_omap2430()) {
|
||||
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
|
||||
cpu_mask = RATE_IN_243X;
|
||||
}
|
||||
|
||||
clk_init(&omap2_clk_functions);
|
||||
|
||||
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
||||
clk_preinit(c->lk.clk);
|
||||
|
||||
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
|
||||
propagate_rate(&osc_ck);
|
||||
sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
|
||||
propagate_rate(&sys_ck);
|
||||
|
||||
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
||||
if (c->cpu & cpu_mask) {
|
||||
clkdev_add(&c->lk);
|
||||
clk_register(c->lk.clk);
|
||||
omap2_init_clk_clkdm(c->lk.clk);
|
||||
}
|
||||
|
||||
/* Check the MPU rate set by bootloader */
|
||||
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
|
||||
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
||||
if (!(prcm->flags & cpu_mask))
|
||||
continue;
|
||||
if (prcm->xtal_speed != sys_ck.rate)
|
||||
continue;
|
||||
if (prcm->dpll_speed <= clkrate)
|
||||
break;
|
||||
}
|
||||
curr_prcm_set = prcm;
|
||||
|
||||
recalculate_root_clocks();
|
||||
|
||||
printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
|
||||
"%ld.%01ld/%ld/%ld MHz\n",
|
||||
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
||||
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
||||
|
||||
/*
|
||||
* Only enable those clocks we will need, let the drivers
|
||||
* enable other clocks as necessary
|
||||
*/
|
||||
clk_enable_init_clocks();
|
||||
|
||||
/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
|
||||
vclk = clk_get(NULL, "virt_prcm_set");
|
||||
sclk = clk_get(NULL, "sys_ck");
|
||||
|
||||
return 0;
|
||||
}
|
587
arch/arm/mach-omap2/clock2xxx.c
Normal file
587
arch/arm/mach-omap2/clock2xxx.c
Normal file
|
@ -0,0 +1,587 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/clock.c
|
||||
*
|
||||
* Copyright (C) 2005-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2008 Nokia Corporation
|
||||
*
|
||||
* Contacts:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Paul Walmsley
|
||||
*
|
||||
* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
|
||||
* Gordon McNutt and RidgeRun, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <plat/clock.h>
|
||||
#include <plat/sram.h>
|
||||
#include <plat/prcm.h>
|
||||
#include <plat/clkdev_omap.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
#include <plat/sdrc.h>
|
||||
#include "clock.h"
|
||||
#include "clock2xxx.h"
|
||||
#include "opp2xxx.h"
|
||||
#include "prm.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
|
||||
|
||||
/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
|
||||
#define EN_APLL_STOPPED 0
|
||||
#define EN_APLL_LOCKED 3
|
||||
|
||||
/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
|
||||
#define APLLS_CLKIN_19_2MHZ 0
|
||||
#define APLLS_CLKIN_13MHZ 2
|
||||
#define APLLS_CLKIN_12MHZ 3
|
||||
|
||||
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
|
||||
|
||||
const struct prcm_config *curr_prcm_set;
|
||||
const struct prcm_config *rate_table;
|
||||
|
||||
struct clk *vclk, *sclk, *dclk;
|
||||
|
||||
void __iomem *prcm_clksrc_ctrl;
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Omap24xx specific clock functions
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
|
||||
* @clk: struct clk * being enabled
|
||||
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
|
||||
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
|
||||
*
|
||||
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
|
||||
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
|
||||
* passes back the correct CM_IDLEST register address for I2CHS
|
||||
* modules. No return value.
|
||||
*/
|
||||
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit)
|
||||
{
|
||||
*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
|
||||
*idlest_bit = clk->enable_bit;
|
||||
}
|
||||
|
||||
/* 2430 I2CHS has non-standard IDLEST register */
|
||||
const struct clkops clkops_omap2430_i2chs_wait = {
|
||||
.enable = omap2_dflt_clk_enable,
|
||||
.disable = omap2_dflt_clk_disable,
|
||||
.find_idlest = omap2430_clk_i2chs_find_idlest,
|
||||
.find_companion = omap2_clk_dflt_find_companion,
|
||||
};
|
||||
|
||||
/**
|
||||
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
|
||||
* @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
|
||||
*
|
||||
* Returns the CORE_CLK rate. CORE_CLK can have one of three rate
|
||||
* sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
|
||||
* (the latter is unusual). This currently should be called with
|
||||
* struct clk *dpll_ck, which is a composite clock of dpll_ck and
|
||||
* core_ck.
|
||||
*/
|
||||
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
|
||||
{
|
||||
long long core_clk;
|
||||
u32 v;
|
||||
|
||||
core_clk = omap2_get_dpll_rate(clk);
|
||||
|
||||
v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
v &= OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
|
||||
if (v == CORE_CLK_SRC_32K)
|
||||
core_clk = 32768;
|
||||
else
|
||||
core_clk *= v;
|
||||
|
||||
return core_clk;
|
||||
}
|
||||
|
||||
static int omap2_enable_osc_ck(struct clk *clk)
|
||||
{
|
||||
u32 pcc;
|
||||
|
||||
pcc = __raw_readl(prcm_clksrc_ctrl);
|
||||
|
||||
__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap2_disable_osc_ck(struct clk *clk)
|
||||
{
|
||||
u32 pcc;
|
||||
|
||||
pcc = __raw_readl(prcm_clksrc_ctrl);
|
||||
|
||||
__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
|
||||
}
|
||||
|
||||
const struct clkops clkops_oscck = {
|
||||
.enable = omap2_enable_osc_ck,
|
||||
.disable = omap2_disable_osc_ck,
|
||||
};
|
||||
|
||||
#ifdef OLD_CK
|
||||
/* Recalculate SYST_CLK */
|
||||
static void omap2_sys_clk_recalc(struct clk *clk)
|
||||
{
|
||||
u32 div = PRCM_CLKSRC_CTRL;
|
||||
div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
|
||||
div >>= clk->rate_offset;
|
||||
clk->rate = (clk->parent->rate / div);
|
||||
propagate_rate(clk);
|
||||
}
|
||||
#endif /* OLD_CK */
|
||||
|
||||
/* Enable an APLL if off */
|
||||
static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
|
||||
{
|
||||
u32 cval, apll_mask;
|
||||
|
||||
apll_mask = EN_APLL_LOCKED << clk->enable_bit;
|
||||
|
||||
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
||||
|
||||
if ((cval & apll_mask) == apll_mask)
|
||||
return 0; /* apll already enabled */
|
||||
|
||||
cval &= ~apll_mask;
|
||||
cval |= apll_mask;
|
||||
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
|
||||
|
||||
omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
|
||||
clk->name);
|
||||
|
||||
/*
|
||||
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
|
||||
* fails?
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap2_clk_apll96_enable(struct clk *clk)
|
||||
{
|
||||
return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
|
||||
}
|
||||
|
||||
static int omap2_clk_apll54_enable(struct clk *clk)
|
||||
{
|
||||
return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
|
||||
}
|
||||
|
||||
/* Stop APLL */
|
||||
static void omap2_clk_apll_disable(struct clk *clk)
|
||||
{
|
||||
u32 cval;
|
||||
|
||||
cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
|
||||
cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
|
||||
cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
|
||||
}
|
||||
|
||||
const struct clkops clkops_apll96 = {
|
||||
.enable = omap2_clk_apll96_enable,
|
||||
.disable = omap2_clk_apll_disable,
|
||||
};
|
||||
|
||||
const struct clkops clkops_apll54 = {
|
||||
.enable = omap2_clk_apll54_enable,
|
||||
.disable = omap2_clk_apll_disable,
|
||||
};
|
||||
|
||||
/*
|
||||
* Uses the current prcm set to tell if a rate is valid.
|
||||
* You can go slower, but not faster within a given rate set.
|
||||
*/
|
||||
long omap2_dpllcore_round_rate(unsigned long target_rate)
|
||||
{
|
||||
u32 high, low, core_clk_src;
|
||||
|
||||
core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
|
||||
if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */
|
||||
high = curr_prcm_set->dpll_speed * 2;
|
||||
low = curr_prcm_set->dpll_speed;
|
||||
} else { /* DPLL clockout x 2 */
|
||||
high = curr_prcm_set->dpll_speed;
|
||||
low = curr_prcm_set->dpll_speed / 2;
|
||||
}
|
||||
|
||||
#ifdef DOWN_VARIABLE_DPLL
|
||||
if (target_rate > high)
|
||||
return high;
|
||||
else
|
||||
return target_rate;
|
||||
#else
|
||||
if (target_rate > low)
|
||||
return high;
|
||||
else
|
||||
return low;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
unsigned long omap2_dpllcore_recalc(struct clk *clk)
|
||||
{
|
||||
return omap2xxx_clk_get_core_rate(clk);
|
||||
}
|
||||
|
||||
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 cur_rate, low, mult, div, valid_rate, done_rate;
|
||||
u32 bypass = 0;
|
||||
struct prcm_config tmpset;
|
||||
const struct dpll_data *dd;
|
||||
|
||||
cur_rate = omap2xxx_clk_get_core_rate(dclk);
|
||||
mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
mult &= OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
|
||||
if ((rate == (cur_rate / 2)) && (mult == 2)) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
|
||||
} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
} else if (rate != cur_rate) {
|
||||
valid_rate = omap2_dpllcore_round_rate(rate);
|
||||
if (valid_rate != rate)
|
||||
return -EINVAL;
|
||||
|
||||
if (mult == 1)
|
||||
low = curr_prcm_set->dpll_speed;
|
||||
else
|
||||
low = curr_prcm_set->dpll_speed / 2;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
|
||||
tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
|
||||
dd->div1_mask);
|
||||
div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
|
||||
tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
|
||||
tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
|
||||
if (rate > low) {
|
||||
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
|
||||
mult = ((rate / 2) / 1000000);
|
||||
done_rate = CORE_CLK_SRC_DPLL_X2;
|
||||
} else {
|
||||
tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
|
||||
mult = (rate / 1000000);
|
||||
done_rate = CORE_CLK_SRC_DPLL;
|
||||
}
|
||||
tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
|
||||
tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
|
||||
|
||||
/* Worst case */
|
||||
tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
|
||||
|
||||
if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
|
||||
bypass = 1;
|
||||
|
||||
/* For omap2xxx_sdrc_init_params() */
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
|
||||
/* Force dll lock mode */
|
||||
omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
|
||||
bypass);
|
||||
|
||||
/* Errata: ret dll entry state */
|
||||
omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
|
||||
omap2xxx_sdrc_reprogram(done_rate, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_table_mpu_recalc - just return the MPU speed
|
||||
* @clk: virt_prcm_set struct clk
|
||||
*
|
||||
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
|
||||
*/
|
||||
unsigned long omap2_table_mpu_recalc(struct clk *clk)
|
||||
{
|
||||
return curr_prcm_set->mpu_speed;
|
||||
}
|
||||
|
||||
/*
|
||||
* Look for a rate equal or less than the target rate given a configuration set.
|
||||
*
|
||||
* What's not entirely clear is "which" field represents the key field.
|
||||
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
|
||||
* just uses the ARM rates.
|
||||
*/
|
||||
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
const struct prcm_config *ptr;
|
||||
long highest_rate;
|
||||
long sys_ck_rate;
|
||||
|
||||
sys_ck_rate = clk_get_rate(sclk);
|
||||
|
||||
highest_rate = -EINVAL;
|
||||
|
||||
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
|
||||
if (!(ptr->flags & cpu_mask))
|
||||
continue;
|
||||
if (ptr->xtal_speed != sys_ck_rate)
|
||||
continue;
|
||||
|
||||
highest_rate = ptr->mpu_speed;
|
||||
|
||||
/* Can check only after xtal frequency check */
|
||||
if (ptr->mpu_speed <= rate)
|
||||
break;
|
||||
}
|
||||
return highest_rate;
|
||||
}
|
||||
|
||||
/* Sets basic clocks based on the specified rate */
|
||||
int omap2_select_table_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
u32 cur_rate, done_rate, bypass = 0, tmp;
|
||||
const struct prcm_config *prcm;
|
||||
unsigned long found_speed = 0;
|
||||
unsigned long flags;
|
||||
long sys_ck_rate;
|
||||
|
||||
sys_ck_rate = clk_get_rate(sclk);
|
||||
|
||||
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
||||
if (!(prcm->flags & cpu_mask))
|
||||
continue;
|
||||
|
||||
if (prcm->xtal_speed != sys_ck_rate)
|
||||
continue;
|
||||
|
||||
if (prcm->mpu_speed <= rate) {
|
||||
found_speed = prcm->mpu_speed;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!found_speed) {
|
||||
printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
|
||||
rate / 1000000);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
curr_prcm_set = prcm;
|
||||
cur_rate = omap2xxx_clk_get_core_rate(dclk);
|
||||
|
||||
if (prcm->dpll_speed == cur_rate / 2) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
|
||||
} else if (prcm->dpll_speed == cur_rate * 2) {
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
} else if (prcm->dpll_speed != cur_rate) {
|
||||
local_irq_save(flags);
|
||||
|
||||
if (prcm->dpll_speed == prcm->xtal_speed)
|
||||
bypass = 1;
|
||||
|
||||
if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
|
||||
CORE_CLK_SRC_DPLL_X2)
|
||||
done_rate = CORE_CLK_SRC_DPLL_X2;
|
||||
else
|
||||
done_rate = CORE_CLK_SRC_DPLL;
|
||||
|
||||
/* MPU divider */
|
||||
cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
|
||||
|
||||
/* dsp + iva1 div(2420), iva2.1(2430) */
|
||||
cm_write_mod_reg(prcm->cm_clksel_dsp,
|
||||
OMAP24XX_DSP_MOD, CM_CLKSEL);
|
||||
|
||||
cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
|
||||
|
||||
/* Major subsystem dividers */
|
||||
tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
|
||||
cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
|
||||
CM_CLKSEL1);
|
||||
|
||||
if (cpu_is_omap2430())
|
||||
cm_write_mod_reg(prcm->cm_clksel_mdm,
|
||||
OMAP2430_MDM_MOD, CM_CLKSEL);
|
||||
|
||||
/* x2 to enter omap2xxx_sdrc_init_params() */
|
||||
omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
|
||||
|
||||
omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
|
||||
bypass);
|
||||
|
||||
omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
|
||||
omap2xxx_sdrc_reprogram(done_rate, 0);
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
/*
|
||||
* Walk PRCM rate table and fillout cpufreq freq_table
|
||||
*/
|
||||
static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
|
||||
|
||||
void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
|
||||
{
|
||||
struct prcm_config *prcm;
|
||||
int i = 0;
|
||||
|
||||
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
||||
if (!(prcm->flags & cpu_mask))
|
||||
continue;
|
||||
if (prcm->xtal_speed != sys_ck.rate)
|
||||
continue;
|
||||
|
||||
/* don't put bypass rates in table */
|
||||
if (prcm->dpll_speed == prcm->xtal_speed)
|
||||
continue;
|
||||
|
||||
freq_table[i].index = i;
|
||||
freq_table[i].frequency = prcm->mpu_speed / 1000;
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
printk(KERN_WARNING "%s: failed to initialize frequency "
|
||||
"table\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
freq_table[i].index = i;
|
||||
freq_table[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
*table = &freq_table[0];
|
||||
}
|
||||
#endif
|
||||
|
||||
struct clk_functions omap2_clk_functions = {
|
||||
.clk_enable = omap2_clk_enable,
|
||||
.clk_disable = omap2_clk_disable,
|
||||
.clk_round_rate = omap2_clk_round_rate,
|
||||
.clk_set_rate = omap2_clk_set_rate,
|
||||
.clk_set_parent = omap2_clk_set_parent,
|
||||
.clk_disable_unused = omap2_clk_disable_unused,
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
.clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
|
||||
#endif
|
||||
};
|
||||
|
||||
static u32 omap2_get_apll_clkin(void)
|
||||
{
|
||||
u32 aplls, srate = 0;
|
||||
|
||||
aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
|
||||
aplls &= OMAP24XX_APLLS_CLKIN_MASK;
|
||||
aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
|
||||
|
||||
if (aplls == APLLS_CLKIN_19_2MHZ)
|
||||
srate = 19200000;
|
||||
else if (aplls == APLLS_CLKIN_13MHZ)
|
||||
srate = 13000000;
|
||||
else if (aplls == APLLS_CLKIN_12MHZ)
|
||||
srate = 12000000;
|
||||
|
||||
return srate;
|
||||
}
|
||||
|
||||
static u32 omap2_get_sysclkdiv(void)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
div = __raw_readl(prcm_clksrc_ctrl);
|
||||
div &= OMAP_SYSCLKDIV_MASK;
|
||||
div >>= OMAP_SYSCLKDIV_SHIFT;
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
unsigned long omap2_osc_clk_recalc(struct clk *clk)
|
||||
{
|
||||
return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
|
||||
}
|
||||
|
||||
unsigned long omap2_sys_clk_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / omap2_get_sysclkdiv();
|
||||
}
|
||||
|
||||
/*
|
||||
* Set clocks for bypass mode for reboot to work.
|
||||
*/
|
||||
void omap2_clk_prepare_for_reboot(void)
|
||||
{
|
||||
u32 rate;
|
||||
|
||||
if (vclk == NULL || sclk == NULL)
|
||||
return;
|
||||
|
||||
rate = clk_get_rate(sclk);
|
||||
clk_set_rate(vclk, rate);
|
||||
}
|
||||
|
||||
/*
|
||||
* Switch the MPU rate if specified on cmdline.
|
||||
* We cannot do this early until cmdline is parsed.
|
||||
*/
|
||||
static int __init omap2_clk_arch_init(void)
|
||||
{
|
||||
struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
|
||||
unsigned long sys_ck_rate;
|
||||
|
||||
if (!mpurate)
|
||||
return -EINVAL;
|
||||
|
||||
virt_prcm_set = clk_get(NULL, "virt_prcm_set");
|
||||
sys_ck = clk_get(NULL, "sys_ck");
|
||||
dpll_ck = clk_get(NULL, "dpll_ck");
|
||||
mpu_ck = clk_get(NULL, "mpu_ck");
|
||||
|
||||
if (clk_set_rate(virt_prcm_set, mpurate))
|
||||
printk(KERN_ERR "Could not find matching MPU rate\n");
|
||||
|
||||
recalculate_root_clocks();
|
||||
|
||||
sys_ck_rate = clk_get_rate(sys_ck);
|
||||
|
||||
pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
|
||||
"%ld.%01ld/%ld/%ld MHz\n",
|
||||
(sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
|
||||
(clk_get_rate(dpll_ck) / 1000000),
|
||||
(clk_get_rate(mpu_ck) / 1000000));
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap2_clk_arch_init);
|
||||
|
||||
|
41
arch/arm/mach-omap2/clock2xxx.h
Normal file
41
arch/arm/mach-omap2/clock2xxx.h
Normal file
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* OMAP2 clock function prototypes and macros
|
||||
*
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
|
||||
|
||||
unsigned long omap2_table_mpu_recalc(struct clk *clk);
|
||||
int omap2_select_table_rate(struct clk *clk, unsigned long rate);
|
||||
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
|
||||
unsigned long omap2_sys_clk_recalc(struct clk *clk);
|
||||
unsigned long omap2_osc_clk_recalc(struct clk *clk);
|
||||
unsigned long omap2_sys_clk_recalc(struct clk *clk);
|
||||
unsigned long omap2_dpllcore_recalc(struct clk *clk);
|
||||
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
|
||||
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
|
||||
|
||||
/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
|
||||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
|
||||
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
|
||||
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
|
||||
#else
|
||||
#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
|
||||
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
|
||||
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
|
||||
#endif
|
||||
|
||||
extern void __iomem *prcm_clksrc_ctrl;
|
||||
|
||||
extern struct clk *dclk;
|
||||
|
||||
extern const struct clkops clkops_omap2430_i2chs_wait;
|
||||
extern const struct clkops clkops_oscck;
|
||||
extern const struct clkops clkops_apll96;
|
||||
extern const struct clkops clkops_apll54;
|
||||
|
||||
#endif
|
|
@ -1,8 +1,8 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/clock24xx.h
|
||||
* linux/arch/arm/mach-omap2/clock2xxx_data.c
|
||||
*
|
||||
* Copyright (C) 2005-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2008 Nokia Corporation
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*
|
||||
* Contacts:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
|
@ -13,600 +13,21 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <plat/clkdev_omap.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#include "clock2xxx.h"
|
||||
#include "opp2xxx.h"
|
||||
#include "prm.h"
|
||||
#include "cm.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
#include "sdrc.h"
|
||||
|
||||
/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
|
||||
#ifdef CONFIG_ARCH_OMAP2420
|
||||
#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
|
||||
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
|
||||
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
|
||||
#else
|
||||
#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
|
||||
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
|
||||
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
|
||||
#endif
|
||||
|
||||
static unsigned long omap2_table_mpu_recalc(struct clk *clk);
|
||||
static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
|
||||
static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
|
||||
static unsigned long omap2_sys_clk_recalc(struct clk *clk);
|
||||
static unsigned long omap2_osc_clk_recalc(struct clk *clk);
|
||||
static unsigned long omap2_sys_clk_recalc(struct clk *clk);
|
||||
static unsigned long omap2_dpllcore_recalc(struct clk *clk);
|
||||
static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
|
||||
|
||||
/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
|
||||
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
|
||||
* CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
|
||||
*/
|
||||
struct prcm_config {
|
||||
unsigned long xtal_speed; /* crystal rate */
|
||||
unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
|
||||
unsigned long mpu_speed; /* speed of MPU */
|
||||
unsigned long cm_clksel_mpu; /* mpu divider */
|
||||
unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
|
||||
unsigned long cm_clksel_gfx; /* gfx dividers */
|
||||
unsigned long cm_clksel1_core; /* major subsystem dividers */
|
||||
unsigned long cm_clksel1_pll; /* m,n */
|
||||
unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
|
||||
unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
|
||||
unsigned long base_sdrc_rfr; /* base refresh timing for a set */
|
||||
unsigned char flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
|
||||
* These configurations are characterized by voltage and speed for clocks.
|
||||
* The device is only validated for certain combinations. One way to express
|
||||
* these combinations is via the 'ratio's' which the clocks operate with
|
||||
* respect to each other. These ratio sets are for a given voltage/DPLL
|
||||
* setting. All configurations can be described by a DPLL setting and a ratio
|
||||
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
|
||||
*
|
||||
* 2430 differs from 2420 in that there are no more phase synchronizers used.
|
||||
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
|
||||
* 2430 (iva2.1, NOdsp, mdm)
|
||||
*/
|
||||
|
||||
/* Core fields for cm_clksel, not ratio governed */
|
||||
#define RX_CLKSEL_DSS1 (0x10 << 8)
|
||||
#define RX_CLKSEL_DSS2 (0x0 << 13)
|
||||
#define RX_CLKSEL_SSI (0x5 << 20)
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Voltage/DPLL ratios
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* 2430 Ratio's, 2430-Ratio Config 1 */
|
||||
#define R1_CLKSEL_L3 (4 << 0)
|
||||
#define R1_CLKSEL_L4 (2 << 5)
|
||||
#define R1_CLKSEL_USB (4 << 25)
|
||||
#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
R1_CLKSEL_L4 | R1_CLKSEL_L3
|
||||
#define R1_CLKSEL_MPU (2 << 0)
|
||||
#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
|
||||
#define R1_CLKSEL_DSP (2 << 0)
|
||||
#define R1_CLKSEL_DSP_IF (2 << 5)
|
||||
#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
|
||||
#define R1_CLKSEL_GFX (2 << 0)
|
||||
#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
|
||||
#define R1_CLKSEL_MDM (4 << 0)
|
||||
#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
|
||||
|
||||
/* 2430-Ratio Config 2 */
|
||||
#define R2_CLKSEL_L3 (6 << 0)
|
||||
#define R2_CLKSEL_L4 (2 << 5)
|
||||
#define R2_CLKSEL_USB (2 << 25)
|
||||
#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
R2_CLKSEL_L4 | R2_CLKSEL_L3
|
||||
#define R2_CLKSEL_MPU (2 << 0)
|
||||
#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
|
||||
#define R2_CLKSEL_DSP (2 << 0)
|
||||
#define R2_CLKSEL_DSP_IF (3 << 5)
|
||||
#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
|
||||
#define R2_CLKSEL_GFX (2 << 0)
|
||||
#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
|
||||
#define R2_CLKSEL_MDM (6 << 0)
|
||||
#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
|
||||
|
||||
/* 2430-Ratio Bootm (BYPASS) */
|
||||
#define RB_CLKSEL_L3 (1 << 0)
|
||||
#define RB_CLKSEL_L4 (1 << 5)
|
||||
#define RB_CLKSEL_USB (1 << 25)
|
||||
#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
RB_CLKSEL_L4 | RB_CLKSEL_L3
|
||||
#define RB_CLKSEL_MPU (1 << 0)
|
||||
#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
|
||||
#define RB_CLKSEL_DSP (1 << 0)
|
||||
#define RB_CLKSEL_DSP_IF (1 << 5)
|
||||
#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
|
||||
#define RB_CLKSEL_GFX (1 << 0)
|
||||
#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
|
||||
#define RB_CLKSEL_MDM (1 << 0)
|
||||
#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
|
||||
|
||||
/* 2420 Ratio Equivalents */
|
||||
#define RXX_CLKSEL_VLYNQ (0x12 << 15)
|
||||
#define RXX_CLKSEL_SSI (0x8 << 20)
|
||||
|
||||
/* 2420-PRCM III 532MHz core */
|
||||
#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
|
||||
#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
|
||||
#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
|
||||
#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
|
||||
RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
|
||||
RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
|
||||
RIII_CLKSEL_L3
|
||||
#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
|
||||
#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
|
||||
#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
|
||||
#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
|
||||
#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
|
||||
#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
|
||||
#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
|
||||
#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
|
||||
RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
|
||||
RIII_CLKSEL_DSP
|
||||
#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
|
||||
#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
|
||||
|
||||
/* 2420-PRCM II 600MHz core */
|
||||
#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
|
||||
#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
|
||||
#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
|
||||
#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
|
||||
RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
RII_CLKSEL_L4 | RII_CLKSEL_L3
|
||||
#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
|
||||
#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
|
||||
#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
|
||||
#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
|
||||
#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
|
||||
#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
|
||||
#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
|
||||
#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
|
||||
RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
|
||||
RII_CLKSEL_DSP
|
||||
#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
|
||||
#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
|
||||
|
||||
/* 2420-PRCM I 660MHz core */
|
||||
#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
|
||||
#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
|
||||
#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
|
||||
#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
|
||||
RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
RI_CLKSEL_L4 | RI_CLKSEL_L3
|
||||
#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
|
||||
#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
|
||||
#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
|
||||
#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
|
||||
#define RI_SYNC_DSP (1 << 7) /* Activate sync */
|
||||
#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
|
||||
#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
|
||||
#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
|
||||
RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
|
||||
RI_CLKSEL_DSP
|
||||
#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
|
||||
#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
|
||||
|
||||
/* 2420-PRCM VII (boot) */
|
||||
#define RVII_CLKSEL_L3 (1 << 0)
|
||||
#define RVII_CLKSEL_L4 (1 << 5)
|
||||
#define RVII_CLKSEL_DSS1 (1 << 8)
|
||||
#define RVII_CLKSEL_DSS2 (0 << 13)
|
||||
#define RVII_CLKSEL_VLYNQ (1 << 15)
|
||||
#define RVII_CLKSEL_SSI (1 << 20)
|
||||
#define RVII_CLKSEL_USB (1 << 25)
|
||||
|
||||
#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
|
||||
RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
|
||||
RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
|
||||
|
||||
#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
|
||||
#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
|
||||
|
||||
#define RVII_CLKSEL_DSP (1 << 0)
|
||||
#define RVII_CLKSEL_DSP_IF (1 << 5)
|
||||
#define RVII_SYNC_DSP (0 << 7)
|
||||
#define RVII_CLKSEL_IVA (1 << 8)
|
||||
#define RVII_SYNC_IVA (0 << 13)
|
||||
#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
|
||||
RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
|
||||
|
||||
#define RVII_CLKSEL_GFX (1 << 0)
|
||||
#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* 2430 Target modes: Along with each configuration the CPU has several
|
||||
* modes which goes along with them. Modes mainly are the addition of
|
||||
* describe DPLL combinations to go along with a ratio.
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* Hardware governed */
|
||||
#define MX_48M_SRC (0 << 3)
|
||||
#define MX_54M_SRC (0 << 5)
|
||||
#define MX_APLLS_CLIKIN_12 (3 << 23)
|
||||
#define MX_APLLS_CLIKIN_13 (2 << 23)
|
||||
#define MX_APLLS_CLIKIN_19_2 (0 << 23)
|
||||
|
||||
/*
|
||||
* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
|
||||
* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
|
||||
*/
|
||||
#define M5A_DPLL_MULT_12 (133 << 12)
|
||||
#define M5A_DPLL_DIV_12 (5 << 8)
|
||||
#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
#define M5A_DPLL_MULT_13 (61 << 12)
|
||||
#define M5A_DPLL_DIV_13 (2 << 8)
|
||||
#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
#define M5A_DPLL_MULT_19 (55 << 12)
|
||||
#define M5A_DPLL_DIV_19 (3 << 8)
|
||||
#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2
|
||||
/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
|
||||
#define M5B_DPLL_MULT_12 (50 << 12)
|
||||
#define M5B_DPLL_DIV_12 (2 << 8)
|
||||
#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
#define M5B_DPLL_MULT_13 (200 << 12)
|
||||
#define M5B_DPLL_DIV_13 (12 << 8)
|
||||
|
||||
#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
#define M5B_DPLL_MULT_19 (125 << 12)
|
||||
#define M5B_DPLL_DIV_19 (31 << 8)
|
||||
#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2
|
||||
/*
|
||||
* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
|
||||
*/
|
||||
#define M4_DPLL_MULT_12 (133 << 12)
|
||||
#define M4_DPLL_DIV_12 (3 << 8)
|
||||
#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
|
||||
#define M4_DPLL_MULT_13 (399 << 12)
|
||||
#define M4_DPLL_DIV_13 (12 << 8)
|
||||
#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
|
||||
#define M4_DPLL_MULT_19 (145 << 12)
|
||||
#define M4_DPLL_DIV_19 (6 << 8)
|
||||
#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2
|
||||
|
||||
/*
|
||||
* #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
|
||||
*/
|
||||
#define M3_DPLL_MULT_12 (55 << 12)
|
||||
#define M3_DPLL_DIV_12 (1 << 8)
|
||||
#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
#define M3_DPLL_MULT_13 (76 << 12)
|
||||
#define M3_DPLL_DIV_13 (2 << 8)
|
||||
#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
#define M3_DPLL_MULT_19 (17 << 12)
|
||||
#define M3_DPLL_DIV_19 (0 << 8)
|
||||
#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2
|
||||
|
||||
/*
|
||||
* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
|
||||
*/
|
||||
#define M2_DPLL_MULT_12 (55 << 12)
|
||||
#define M2_DPLL_DIV_12 (1 << 8)
|
||||
#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
|
||||
/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
|
||||
* relock time issue */
|
||||
/* Core frequency changed from 330/165 to 329/164 MHz*/
|
||||
#define M2_DPLL_MULT_13 (76 << 12)
|
||||
#define M2_DPLL_DIV_13 (2 << 8)
|
||||
#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
|
||||
#define M2_DPLL_MULT_19 (17 << 12)
|
||||
#define M2_DPLL_DIV_19 (0 << 8)
|
||||
#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2
|
||||
|
||||
/* boot (boot) */
|
||||
#define MB_DPLL_MULT (1 << 12)
|
||||
#define MB_DPLL_DIV (0 << 8)
|
||||
#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
|
||||
MB_DPLL_MULT | MX_APLLS_CLIKIN_12
|
||||
|
||||
#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
|
||||
MB_DPLL_MULT | MX_APLLS_CLIKIN_13
|
||||
|
||||
#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
|
||||
MB_DPLL_MULT | MX_APLLS_CLIKIN_19
|
||||
|
||||
/*
|
||||
* 2430 - chassis (sedna)
|
||||
* 165 (ratio1) same as above #2
|
||||
* 150 (ratio1)
|
||||
* 133 (ratio2) same as above #4
|
||||
* 110 (ratio2) same as above #3
|
||||
* 104 (ratio2)
|
||||
* boot (boot)
|
||||
*/
|
||||
|
||||
/* PRCM I target DPLL = 2*330MHz = 660MHz */
|
||||
#define MI_DPLL_MULT_12 (55 << 12)
|
||||
#define MI_DPLL_DIV_12 (1 << 8)
|
||||
#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
|
||||
/*
|
||||
* 2420 Equivalent - mode registers
|
||||
* PRCM II , target DPLL = 2*300MHz = 600MHz
|
||||
*/
|
||||
#define MII_DPLL_MULT_12 (50 << 12)
|
||||
#define MII_DPLL_DIV_12 (1 << 8)
|
||||
#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
#define MII_DPLL_MULT_13 (300 << 12)
|
||||
#define MII_DPLL_DIV_13 (12 << 8)
|
||||
#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
|
||||
/* PRCM III target DPLL = 2*266 = 532MHz*/
|
||||
#define MIII_DPLL_MULT_12 (133 << 12)
|
||||
#define MIII_DPLL_DIV_12 (5 << 8)
|
||||
#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12
|
||||
#define MIII_DPLL_MULT_13 (266 << 12)
|
||||
#define MIII_DPLL_DIV_13 (12 << 8)
|
||||
#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
|
||||
MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13
|
||||
|
||||
/* PRCM VII (boot bypass) */
|
||||
#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
|
||||
#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
|
||||
|
||||
/* High and low operation value */
|
||||
#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
|
||||
#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
|
||||
|
||||
/* MPU speed defines */
|
||||
#define S12M 12000000
|
||||
#define S13M 13000000
|
||||
#define S19M 19200000
|
||||
#define S26M 26000000
|
||||
#define S100M 100000000
|
||||
#define S133M 133000000
|
||||
#define S150M 150000000
|
||||
#define S164M 164000000
|
||||
#define S165M 165000000
|
||||
#define S199M 199000000
|
||||
#define S200M 200000000
|
||||
#define S266M 266000000
|
||||
#define S300M 300000000
|
||||
#define S329M 329000000
|
||||
#define S330M 330000000
|
||||
#define S399M 399000000
|
||||
#define S400M 400000000
|
||||
#define S532M 532000000
|
||||
#define S600M 600000000
|
||||
#define S658M 658000000
|
||||
#define S660M 660000000
|
||||
#define S798M 798000000
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
|
||||
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
|
||||
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
|
||||
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
|
||||
*
|
||||
* Filling in table based on H4 boards and 2430-SDPs variants available.
|
||||
* There are quite a few more rates combinations which could be defined.
|
||||
*
|
||||
* When multiple values are defined the start up will try and choose the
|
||||
* fastest one. If a 'fast' value is defined, then automatically, the /2
|
||||
* one should be included as it can be used. Generally having more that
|
||||
* one fast set does not make sense, as static timings need to be changed
|
||||
* to change the set. The exception is the bypass setting which is
|
||||
* availble for low power bypass.
|
||||
*
|
||||
* Note: This table needs to be sorted, fastest to slowest.
|
||||
*-------------------------------------------------------------------------*/
|
||||
static struct prcm_config rate_table[] = {
|
||||
/* PRCM I - FAST */
|
||||
{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
|
||||
RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
|
||||
RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM II - FAST */
|
||||
{S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM III - FAST */
|
||||
{S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM II - SLOW */
|
||||
{S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM III - SLOW */
|
||||
{S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM-VII (boot-bypass) */
|
||||
{S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
|
||||
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
|
||||
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM-VII (boot-bypass) */
|
||||
{S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
|
||||
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
|
||||
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM #4 - ratio2 (ES2.1) - FAST */
|
||||
{S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
|
||||
R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
|
||||
R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #2 - ratio1 (ES2) - FAST */
|
||||
{S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_165MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5a - ratio1 - FAST */
|
||||
{S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5b - ratio1 - FAST */
|
||||
{S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #4 - ratio1 (ES2.1) - SLOW */
|
||||
{S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
|
||||
R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
|
||||
R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #2 - ratio1 (ES2) - SLOW */
|
||||
{S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_165MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5a - ratio1 - SLOW */
|
||||
{S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5b - ratio1 - SLOW*/
|
||||
{S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM-boot/bypass */
|
||||
{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
|
||||
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
|
||||
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM-boot/bypass */
|
||||
{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
|
||||
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
|
||||
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_243X},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* 24xx clock tree.
|
||||
*
|
||||
|
@ -708,7 +129,7 @@ static struct clk dpll_ck = {
|
|||
|
||||
static struct clk apll96_ck = {
|
||||
.name = "apll96_ck",
|
||||
.ops = &clkops_fixed,
|
||||
.ops = &clkops_apll96,
|
||||
.parent = &sys_ck,
|
||||
.rate = 96000000,
|
||||
.flags = RATE_FIXED | ENABLE_ON_INIT,
|
||||
|
@ -719,7 +140,7 @@ static struct clk apll96_ck = {
|
|||
|
||||
static struct clk apll54_ck = {
|
||||
.name = "apll54_ck",
|
||||
.ops = &clkops_fixed,
|
||||
.ops = &clkops_apll54,
|
||||
.parent = &sys_ck,
|
||||
.rate = 54000000,
|
||||
.flags = RATE_FIXED | ENABLE_ON_INIT,
|
||||
|
@ -2653,5 +2074,236 @@ static struct clk virt_prcm_set = {
|
|||
.round_rate = &omap2_round_to_table_rate,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* clkdev integration
|
||||
*/
|
||||
|
||||
static struct omap_clk omap24xx_clks[] = {
|
||||
/* external root sources */
|
||||
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
|
||||
/* internal analog sources */
|
||||
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
|
||||
/* internal prcm root sources */
|
||||
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
|
||||
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
|
||||
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
|
||||
CLK(NULL, "emul_ck", &emul_ck, CK_242X),
|
||||
/* mpu domain clocks */
|
||||
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
|
||||
/* dsp domain clocks */
|
||||
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
|
||||
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
|
||||
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
|
||||
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
|
||||
/* GFX domain clocks */
|
||||
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
|
||||
/* Modem domain clocks */
|
||||
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
|
||||
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
|
||||
/* DSS domain clocks */
|
||||
CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
|
||||
CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
|
||||
CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
|
||||
CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
|
||||
/* L3 domain clocks */
|
||||
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
|
||||
/* L4 domain clocks */
|
||||
CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
|
||||
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
|
||||
/* virtual meta-group clock */
|
||||
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
|
||||
/* general l4 interface ck, multi-parent functional clk */
|
||||
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
|
||||
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
|
||||
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
|
||||
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
|
||||
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
|
||||
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
|
||||
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
|
||||
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
|
||||
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
|
||||
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
|
||||
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
|
||||
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
|
||||
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
|
||||
CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
|
||||
CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
|
||||
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
|
||||
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
|
||||
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
|
||||
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
|
||||
CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
|
||||
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
|
||||
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
|
||||
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
|
||||
CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
|
||||
CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
|
||||
CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
|
||||
CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
|
||||
CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
|
||||
CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
|
||||
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
|
||||
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
|
||||
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
|
||||
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
|
||||
CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
|
||||
CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
|
||||
CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
|
||||
CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
|
||||
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
|
||||
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
|
||||
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
|
||||
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
|
||||
CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
|
||||
CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
|
||||
};
|
||||
|
||||
/*
|
||||
* init code
|
||||
*/
|
||||
|
||||
int __init omap2_clk_init(void)
|
||||
{
|
||||
const struct prcm_config *prcm;
|
||||
struct omap_clk *c;
|
||||
u32 clkrate;
|
||||
u16 cpu_clkflg;
|
||||
|
||||
if (cpu_is_omap242x()) {
|
||||
prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
|
||||
cpu_mask = RATE_IN_242X;
|
||||
cpu_clkflg = CK_242X;
|
||||
rate_table = omap2420_rate_table;
|
||||
} else if (cpu_is_omap2430()) {
|
||||
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
|
||||
cpu_mask = RATE_IN_243X;
|
||||
cpu_clkflg = CK_243X;
|
||||
rate_table = omap2430_rate_table;
|
||||
}
|
||||
|
||||
clk_init(&omap2_clk_functions);
|
||||
|
||||
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
||||
clk_preinit(c->lk.clk);
|
||||
|
||||
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
|
||||
propagate_rate(&osc_ck);
|
||||
sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
|
||||
propagate_rate(&sys_ck);
|
||||
|
||||
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
|
||||
if (c->cpu & cpu_clkflg) {
|
||||
clkdev_add(&c->lk);
|
||||
clk_register(c->lk.clk);
|
||||
omap2_init_clk_clkdm(c->lk.clk);
|
||||
}
|
||||
|
||||
/* Check the MPU rate set by bootloader */
|
||||
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
|
||||
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
||||
if (!(prcm->flags & cpu_mask))
|
||||
continue;
|
||||
if (prcm->xtal_speed != sys_ck.rate)
|
||||
continue;
|
||||
if (prcm->dpll_speed <= clkrate)
|
||||
break;
|
||||
}
|
||||
curr_prcm_set = prcm;
|
||||
|
||||
recalculate_root_clocks();
|
||||
|
||||
printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
|
||||
"%ld.%01ld/%ld/%ld MHz\n",
|
||||
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
||||
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
||||
|
||||
/*
|
||||
* Only enable those clocks we will need, let the drivers
|
||||
* enable other clocks as necessary
|
||||
*/
|
||||
clk_enable_init_clocks();
|
||||
|
||||
/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
|
||||
vclk = clk_get(NULL, "virt_prcm_set");
|
||||
sclk = clk_get(NULL, "sys_ck");
|
||||
dclk = clk_get(NULL, "dpll_ck");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
3289
arch/arm/mach-omap2/clock34xx_data.c
Normal file
3289
arch/arm/mach-omap2/clock34xx_data.c
Normal file
File diff suppressed because it is too large
Load Diff
33
arch/arm/mach-omap2/clock44xx.c
Normal file
33
arch/arm/mach-omap2/clock44xx.c
Normal file
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* OMAP4-specific clock framework functions
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
*
|
||||
* Rajendra Nayak (rnayak@ti.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include "clock.h"
|
||||
|
||||
struct clk_functions omap2_clk_functions = {
|
||||
.clk_enable = omap2_clk_enable,
|
||||
.clk_disable = omap2_clk_disable,
|
||||
.clk_round_rate = omap2_clk_round_rate,
|
||||
.clk_set_rate = omap2_clk_set_rate,
|
||||
.clk_set_parent = omap2_clk_set_parent,
|
||||
.clk_disable_unused = omap2_clk_disable_unused,
|
||||
};
|
||||
|
||||
const struct clkops clkops_noncore_dpll_ops = {
|
||||
.enable = &omap3_noncore_dpll_enable,
|
||||
.disable = &omap3_noncore_dpll_disable,
|
||||
};
|
||||
|
||||
void omap2_clk_prepare_for_reboot(void)
|
||||
{
|
||||
return;
|
||||
}
|
15
arch/arm/mach-omap2/clock44xx.h
Normal file
15
arch/arm/mach-omap2/clock44xx.h
Normal file
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* OMAP4 clock function prototypes and macros
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
|
||||
|
||||
#define OMAP4430_MAX_DPLL_MULT 2048
|
||||
#define OMAP4430_MAX_DPLL_DIV 128
|
||||
|
||||
extern const struct clkops clkops_noncore_dpll_ops;
|
||||
|
||||
#endif
|
2766
arch/arm/mach-omap2/clock44xx_data.c
Normal file
2766
arch/arm/mach-omap2/clock44xx_data.c
Normal file
File diff suppressed because it is too large
Load Diff
39
arch/arm/mach-omap2/clock_common_data.c
Normal file
39
arch/arm/mach-omap2/clock_common_data.c
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/clock_common_data.c
|
||||
*
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*
|
||||
* Contacts:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file contains clock data that is common to both the OMAP2xxx and
|
||||
* OMAP3xxx clock definition files.
|
||||
*/
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
/* clksel_rate data common to 24xx/343x */
|
||||
const struct clksel_rate gpt_32k_rates[] = {
|
||||
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
|
||||
{ .div = 0 }
|
||||
};
|
||||
|
||||
const struct clksel_rate gpt_sys_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
|
||||
{ .div = 0 }
|
||||
};
|
||||
|
||||
const struct clksel_rate gfx_l3_rates[] = {
|
||||
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
|
||||
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
|
||||
{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
|
||||
{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
|
||||
{ .div = 0 }
|
||||
};
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
* OMAP2/3 clockdomain framework functions
|
||||
*
|
||||
* Copyright (C) 2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008 Nokia Corporation
|
||||
* Copyright (C) 2008-2009 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley and Jouni Högander
|
||||
*
|
||||
|
@ -10,9 +10,7 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
|
||||
# define DEBUG
|
||||
#endif
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
|
|
1474
arch/arm/mach-omap2/cm-regbits-44xx.h
Normal file
1474
arch/arm/mach-omap2/cm-regbits-44xx.h
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -21,6 +21,8 @@
|
|||
|
||||
#include <asm/atomic.h>
|
||||
|
||||
#include <plat/common.h>
|
||||
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
|
|||
mask = 1 << idlest_shift;
|
||||
|
||||
/* XXX should be OMAP2 CM */
|
||||
while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) &&
|
||||
(i++ < MAX_MODULE_READY_TIME))
|
||||
udelay(1);
|
||||
omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
|
||||
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
|
||||
}
|
||||
|
|
|
@ -4,8 +4,8 @@
|
|||
/*
|
||||
* OMAP2/3 Clock Management (CM) register definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
* Copyright (C) 2007-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2009 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*
|
||||
|
@ -22,6 +22,12 @@
|
|||
OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
|
||||
#define OMAP34XX_CM_REGADDR(module, reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
|
||||
#define OMAP44XX_CM1_REGADDR(module, reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
|
||||
#define OMAP44XX_CM2_REGADDR(module, reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
|
||||
|
||||
#include "cm44xx.h"
|
||||
|
||||
/*
|
||||
* Architecture-specific global CM registers
|
||||
|
@ -89,6 +95,11 @@
|
|||
#define OMAP3430_CM_CLKSEL2_EMU 0x0050
|
||||
#define OMAP3430_CM_CLKSEL3_EMU 0x0054
|
||||
|
||||
/* CM2.CEFUSE_CM2 register offsets */
|
||||
|
||||
/* OMAP4 modulemode control */
|
||||
#define OMAP4430_MODULEMODE_HWCTRL 0
|
||||
#define OMAP4430_MODULEMODE_SWCTRL 1
|
||||
|
||||
/* Clock management domain register get/set */
|
||||
|
||||
|
|
358
arch/arm/mach-omap2/cm44xx.h
Normal file
358
arch/arm/mach-omap2/cm44xx.h
Normal file
|
@ -0,0 +1,358 @@
|
|||
/*
|
||||
* OMAP44xx CM1 & CM2 instance offset macros
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley (paul@pwsan.com)
|
||||
* Rajendra Nayak (rnayak@ti.com)
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
|
||||
|
||||
|
||||
/* CM1 */
|
||||
|
||||
|
||||
/* CM1.OCP_SOCKET_CM1 register offsets */
|
||||
#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
|
||||
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
|
||||
|
||||
/* CM1.CKGEN_CM1 register offsets */
|
||||
#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
|
||||
#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
|
||||
#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
|
||||
#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
|
||||
#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
|
||||
#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
|
||||
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
|
||||
#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
|
||||
#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
|
||||
#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
|
||||
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
|
||||
#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
|
||||
#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
|
||||
|
||||
/* CM1.MPU_CM1 register offsets */
|
||||
#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
|
||||
#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
|
||||
#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
|
||||
#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
|
||||
|
||||
/* CM1.TESLA_CM1 register offsets */
|
||||
#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
|
||||
#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
|
||||
#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
|
||||
#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
|
||||
|
||||
/* CM1.ABE_CM1 register offsets */
|
||||
#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
|
||||
#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
|
||||
#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
|
||||
#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
|
||||
#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
|
||||
#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
|
||||
#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
|
||||
#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
|
||||
#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
|
||||
#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
|
||||
#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
|
||||
#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
|
||||
#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
|
||||
#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
|
||||
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
|
||||
|
||||
/* CM1.RESTORE_CM1 register offsets */
|
||||
#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
|
||||
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
|
||||
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
|
||||
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
|
||||
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
|
||||
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
|
||||
|
||||
/* CM2 */
|
||||
|
||||
|
||||
/* CM2.OCP_SOCKET_CM2 register offsets */
|
||||
#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
|
||||
#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
|
||||
|
||||
/* CM2.CKGEN_CM2 register offsets */
|
||||
#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
|
||||
#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
|
||||
#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
|
||||
#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
|
||||
#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
|
||||
#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
|
||||
#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
|
||||
#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
|
||||
#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
|
||||
#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
|
||||
#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
|
||||
#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
|
||||
#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
|
||||
#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
|
||||
#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
|
||||
#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
|
||||
#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
|
||||
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
|
||||
#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
|
||||
#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
|
||||
#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
|
||||
#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
|
||||
#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
|
||||
#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
|
||||
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
|
||||
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
|
||||
|
||||
/* CM2.ALWAYS_ON_CM2 register offsets */
|
||||
#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
|
||||
#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
|
||||
#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
|
||||
#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
|
||||
#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
|
||||
|
||||
/* CM2.CORE_CM2 register offsets */
|
||||
#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
|
||||
#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
|
||||
#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
|
||||
#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
|
||||
#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
|
||||
#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
|
||||
#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
|
||||
#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
|
||||
#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
|
||||
#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
|
||||
#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
|
||||
#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
|
||||
#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
|
||||
#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
|
||||
#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
|
||||
#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
|
||||
#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
|
||||
#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
|
||||
#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
|
||||
#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
|
||||
#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
|
||||
#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
|
||||
#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
|
||||
#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
|
||||
#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
|
||||
#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
|
||||
#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
|
||||
#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
|
||||
#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
|
||||
#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
|
||||
#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
|
||||
#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
|
||||
#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
|
||||
#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
|
||||
#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
|
||||
#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
|
||||
#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
|
||||
#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
|
||||
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
|
||||
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
|
||||
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
|
||||
|
||||
/* CM2.IVAHD_CM2 register offsets */
|
||||
#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
|
||||
#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
|
||||
#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
|
||||
#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
|
||||
#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
|
||||
|
||||
/* CM2.CAM_CM2 register offsets */
|
||||
#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
|
||||
#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
|
||||
#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
|
||||
#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
|
||||
#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
|
||||
|
||||
/* CM2.DSS_CM2 register offsets */
|
||||
#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
|
||||
#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
|
||||
#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
|
||||
#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
|
||||
#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
|
||||
|
||||
/* CM2.GFX_CM2 register offsets */
|
||||
#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
|
||||
#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
|
||||
#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
|
||||
#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
|
||||
|
||||
/* CM2.L3INIT_CM2 register offsets */
|
||||
#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
|
||||
#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
|
||||
#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
|
||||
#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
|
||||
#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
|
||||
#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
|
||||
#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
|
||||
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
|
||||
#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
|
||||
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
|
||||
#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
|
||||
#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
|
||||
#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
|
||||
#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
|
||||
#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
|
||||
#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
|
||||
#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
|
||||
#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
|
||||
#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
|
||||
#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
|
||||
|
||||
/* CM2.L4PER_CM2 register offsets */
|
||||
#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
|
||||
#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
|
||||
#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
|
||||
#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
|
||||
#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
|
||||
#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
|
||||
#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
|
||||
#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
|
||||
#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
|
||||
#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
|
||||
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
|
||||
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
|
||||
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
|
||||
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
|
||||
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
|
||||
#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
|
||||
#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
|
||||
#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
|
||||
#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
|
||||
#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
|
||||
#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
|
||||
#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
|
||||
#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
|
||||
#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
|
||||
#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
|
||||
#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
|
||||
#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
|
||||
#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
|
||||
#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
|
||||
#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
|
||||
#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
|
||||
#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
|
||||
#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
|
||||
#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
|
||||
#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
|
||||
#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
|
||||
#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
|
||||
#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
|
||||
#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
|
||||
#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
|
||||
#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
|
||||
#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
|
||||
#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
|
||||
#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
|
||||
#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
|
||||
#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
|
||||
#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
|
||||
#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
|
||||
#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
|
||||
#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
|
||||
#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
|
||||
|
||||
/* CM2.CEFUSE_CM2 register offsets */
|
||||
#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
|
||||
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
|
||||
|
||||
/* CM2.RESTORE_CM2 register offsets */
|
||||
#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
|
||||
#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
|
||||
#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
|
||||
#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
|
||||
#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
|
||||
#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
|
||||
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
|
||||
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
|
||||
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
|
||||
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
|
||||
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
|
||||
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
|
||||
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
|
||||
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
|
||||
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
|
||||
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
|
||||
#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
|
||||
#endif
|
|
@ -27,6 +27,8 @@
|
|||
#include <mach/gpio.h>
|
||||
#include <plat/mmc.h>
|
||||
|
||||
#include "mux.h"
|
||||
|
||||
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
|
||||
|
||||
static struct resource cam_resources[] = {
|
||||
|
@ -595,27 +597,40 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
|
|||
|
||||
if (cpu_is_omap34xx()) {
|
||||
if (controller_nr == 0) {
|
||||
omap_cfg_reg(N28_3430_MMC1_CLK);
|
||||
omap_cfg_reg(M27_3430_MMC1_CMD);
|
||||
omap_cfg_reg(N27_3430_MMC1_DAT0);
|
||||
omap_mux_init_signal("sdmmc1_clk",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_cmd",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_dat0",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
if (mmc_controller->slots[0].wires == 4 ||
|
||||
mmc_controller->slots[0].wires == 8) {
|
||||
omap_cfg_reg(N26_3430_MMC1_DAT1);
|
||||
omap_cfg_reg(N25_3430_MMC1_DAT2);
|
||||
omap_cfg_reg(P28_3430_MMC1_DAT3);
|
||||
omap_mux_init_signal("sdmmc1_dat1",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_dat2",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_dat3",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
if (mmc_controller->slots[0].wires == 8) {
|
||||
omap_cfg_reg(P27_3430_MMC1_DAT4);
|
||||
omap_cfg_reg(P26_3430_MMC1_DAT5);
|
||||
omap_cfg_reg(R27_3430_MMC1_DAT6);
|
||||
omap_cfg_reg(R25_3430_MMC1_DAT7);
|
||||
omap_mux_init_signal("sdmmc1_dat4",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_dat5",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_dat6",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc1_dat7",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
}
|
||||
if (controller_nr == 1) {
|
||||
/* MMC2 */
|
||||
omap_cfg_reg(AE2_3430_MMC2_CLK);
|
||||
omap_cfg_reg(AG5_3430_MMC2_CMD);
|
||||
omap_cfg_reg(AH5_3430_MMC2_DAT0);
|
||||
omap_mux_init_signal("sdmmc2_clk",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_cmd",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_dat0",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
|
||||
/*
|
||||
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
|
||||
|
@ -623,15 +638,22 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
|
|||
*/
|
||||
if (mmc_controller->slots[0].wires == 4 ||
|
||||
mmc_controller->slots[0].wires == 8) {
|
||||
omap_cfg_reg(AH4_3430_MMC2_DAT1);
|
||||
omap_cfg_reg(AG4_3430_MMC2_DAT2);
|
||||
omap_cfg_reg(AF4_3430_MMC2_DAT3);
|
||||
omap_mux_init_signal("sdmmc2_dat1",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_dat2",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_dat3",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
if (mmc_controller->slots[0].wires == 8) {
|
||||
omap_cfg_reg(AE4_3430_MMC2_DAT4);
|
||||
omap_cfg_reg(AH3_3430_MMC2_DAT5);
|
||||
omap_cfg_reg(AF3_3430_MMC2_DAT6);
|
||||
omap_cfg_reg(AE3_3430_MMC2_DAT7);
|
||||
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
538
arch/arm/mach-omap2/dpll.c
Normal file
538
arch/arm/mach-omap2/dpll.c
Normal file
|
@ -0,0 +1,538 @@
|
|||
/*
|
||||
* OMAP3/4 - specific DPLL control functions
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
* Testing and integration fixes by Jouni Högander
|
||||
*
|
||||
* Parts of this code are based on code written by
|
||||
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/limits.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/sram.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/clkdev.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "prm.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
#include "cm.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
|
||||
#define DPLL_AUTOIDLE_DISABLE 0x0
|
||||
#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
|
||||
|
||||
#define MAX_DPLL_WAIT_TRIES 1000000
|
||||
|
||||
|
||||
/**
|
||||
* omap3_dpll_recalc - recalculate DPLL rate
|
||||
* @clk: DPLL struct clk
|
||||
*
|
||||
* Recalculate and propagate the DPLL rate.
|
||||
*/
|
||||
unsigned long omap3_dpll_recalc(struct clk *clk)
|
||||
{
|
||||
return omap2_get_dpll_rate(clk);
|
||||
}
|
||||
|
||||
/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
|
||||
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v &= ~dd->enable_mask;
|
||||
v |= clken_bits << __ffs(dd->enable_mask);
|
||||
__raw_writel(v, dd->control_reg);
|
||||
}
|
||||
|
||||
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
|
||||
static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
int i = 0;
|
||||
int ret = -EINVAL;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
state <<= __ffs(dd->idlest_mask);
|
||||
|
||||
while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
|
||||
i < MAX_DPLL_WAIT_TRIES) {
|
||||
i++;
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (i == MAX_DPLL_WAIT_TRIES) {
|
||||
printk(KERN_ERR "clock: %s failed transition to '%s'\n",
|
||||
clk->name, (state) ? "locked" : "bypassed");
|
||||
} else {
|
||||
pr_debug("clock: %s transition to '%s' in %d loops\n",
|
||||
clk->name, (state) ? "locked" : "bypassed", i);
|
||||
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* From 3430 TRM ES2 4.7.6.2 */
|
||||
static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
|
||||
{
|
||||
unsigned long fint;
|
||||
u16 f = 0;
|
||||
|
||||
fint = clk->dpll_data->clk_ref->rate / n;
|
||||
|
||||
pr_debug("clock: fint is %lu\n", fint);
|
||||
|
||||
if (fint >= 750000 && fint <= 1000000)
|
||||
f = 0x3;
|
||||
else if (fint > 1000000 && fint <= 1250000)
|
||||
f = 0x4;
|
||||
else if (fint > 1250000 && fint <= 1500000)
|
||||
f = 0x5;
|
||||
else if (fint > 1500000 && fint <= 1750000)
|
||||
f = 0x6;
|
||||
else if (fint > 1750000 && fint <= 2100000)
|
||||
f = 0x7;
|
||||
else if (fint > 7500000 && fint <= 10000000)
|
||||
f = 0xB;
|
||||
else if (fint > 10000000 && fint <= 12500000)
|
||||
f = 0xC;
|
||||
else if (fint > 12500000 && fint <= 15000000)
|
||||
f = 0xD;
|
||||
else if (fint > 15000000 && fint <= 17500000)
|
||||
f = 0xE;
|
||||
else if (fint > 17500000 && fint <= 21000000)
|
||||
f = 0xF;
|
||||
else
|
||||
pr_debug("clock: unknown freqsel setting for %d\n", n);
|
||||
|
||||
return f;
|
||||
}
|
||||
|
||||
/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
|
||||
|
||||
/*
|
||||
* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
|
||||
* @clk: pointer to a DPLL struct clk
|
||||
*
|
||||
* Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
|
||||
* readiness before returning. Will save and restore the DPLL's
|
||||
* autoidle state across the enable, per the CDP code. If the DPLL
|
||||
* locked successfully, return 0; if the DPLL did not lock in the time
|
||||
* allotted, or DPLL3 was passed in, return -EINVAL.
|
||||
*/
|
||||
static int _omap3_noncore_dpll_lock(struct clk *clk)
|
||||
{
|
||||
u8 ai;
|
||||
int r;
|
||||
|
||||
pr_debug("clock: locking DPLL %s\n", clk->name);
|
||||
|
||||
ai = omap3_dpll_autoidle_read(clk);
|
||||
|
||||
omap3_dpll_deny_idle(clk);
|
||||
|
||||
_omap3_dpll_write_clken(clk, DPLL_LOCKED);
|
||||
|
||||
r = _omap3_wait_dpll_status(clk, 1);
|
||||
|
||||
if (ai)
|
||||
omap3_dpll_allow_idle(clk);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
|
||||
* @clk: pointer to a DPLL struct clk
|
||||
*
|
||||
* Instructs a non-CORE DPLL to enter low-power bypass mode. In
|
||||
* bypass mode, the DPLL's rate is set equal to its parent clock's
|
||||
* rate. Waits for the DPLL to report readiness before returning.
|
||||
* Will save and restore the DPLL's autoidle state across the enable,
|
||||
* per the CDP code. If the DPLL entered bypass mode successfully,
|
||||
* return 0; if the DPLL did not enter bypass in the time allotted, or
|
||||
* DPLL3 was passed in, or the DPLL does not support low-power bypass,
|
||||
* return -EINVAL.
|
||||
*/
|
||||
static int _omap3_noncore_dpll_bypass(struct clk *clk)
|
||||
{
|
||||
int r;
|
||||
u8 ai;
|
||||
|
||||
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("clock: configuring DPLL %s for low-power bypass\n",
|
||||
clk->name);
|
||||
|
||||
ai = omap3_dpll_autoidle_read(clk);
|
||||
|
||||
_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
|
||||
|
||||
r = _omap3_wait_dpll_status(clk, 0);
|
||||
|
||||
if (ai)
|
||||
omap3_dpll_allow_idle(clk);
|
||||
else
|
||||
omap3_dpll_deny_idle(clk);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* _omap3_noncore_dpll_stop - instruct a DPLL to stop
|
||||
* @clk: pointer to a DPLL struct clk
|
||||
*
|
||||
* Instructs a non-CORE DPLL to enter low-power stop. Will save and
|
||||
* restore the DPLL's autoidle state across the stop, per the CDP
|
||||
* code. If DPLL3 was passed in, or the DPLL does not support
|
||||
* low-power stop, return -EINVAL; otherwise, return 0.
|
||||
*/
|
||||
static int _omap3_noncore_dpll_stop(struct clk *clk)
|
||||
{
|
||||
u8 ai;
|
||||
|
||||
if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
|
||||
return -EINVAL;
|
||||
|
||||
pr_debug("clock: stopping DPLL %s\n", clk->name);
|
||||
|
||||
ai = omap3_dpll_autoidle_read(clk);
|
||||
|
||||
_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
|
||||
|
||||
if (ai)
|
||||
omap3_dpll_allow_idle(clk);
|
||||
else
|
||||
omap3_dpll_deny_idle(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
|
||||
* @clk: pointer to a DPLL struct clk
|
||||
*
|
||||
* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
|
||||
* The choice of modes depends on the DPLL's programmed rate: if it is
|
||||
* the same as the DPLL's parent clock, it will enter bypass;
|
||||
* otherwise, it will enter lock. This code will wait for the DPLL to
|
||||
* indicate readiness before returning, unless the DPLL takes too long
|
||||
* to enter the target state. Intended to be used as the struct clk's
|
||||
* enable function. If DPLL3 was passed in, or the DPLL does not
|
||||
* support low-power stop, or if the DPLL took too long to enter
|
||||
* bypass or lock, return -EINVAL; otherwise, return 0.
|
||||
*/
|
||||
int omap3_noncore_dpll_enable(struct clk *clk)
|
||||
{
|
||||
int r;
|
||||
struct dpll_data *dd;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->rate == dd->clk_bypass->rate) {
|
||||
WARN_ON(clk->parent != dd->clk_bypass);
|
||||
r = _omap3_noncore_dpll_bypass(clk);
|
||||
} else {
|
||||
WARN_ON(clk->parent != dd->clk_ref);
|
||||
r = _omap3_noncore_dpll_lock(clk);
|
||||
}
|
||||
/*
|
||||
*FIXME: this is dubious - if clk->rate has changed, what about
|
||||
* propagating?
|
||||
*/
|
||||
if (!r)
|
||||
clk->rate = omap2_get_dpll_rate(clk);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
|
||||
* @clk: pointer to a DPLL struct clk
|
||||
*
|
||||
* Instructs a non-CORE DPLL to enter low-power stop. This function is
|
||||
* intended for use in struct clkops. No return value.
|
||||
*/
|
||||
void omap3_noncore_dpll_disable(struct clk *clk)
|
||||
{
|
||||
_omap3_noncore_dpll_stop(clk);
|
||||
}
|
||||
|
||||
|
||||
/* Non-CORE DPLL rate set code */
|
||||
|
||||
/*
|
||||
* omap3_noncore_dpll_program - set non-core DPLL M,N values directly
|
||||
* @clk: struct clk * of DPLL to set
|
||||
* @m: DPLL multiplier to set
|
||||
* @n: DPLL divider to set
|
||||
* @freqsel: FREQSEL value to set
|
||||
*
|
||||
* Program the DPLL with the supplied M, N values, and wait for the DPLL to
|
||||
* lock.. Returns -EINVAL upon error, or 0 upon success.
|
||||
*/
|
||||
int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
|
||||
{
|
||||
struct dpll_data *dd = clk->dpll_data;
|
||||
u32 v;
|
||||
|
||||
/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
|
||||
_omap3_noncore_dpll_bypass(clk);
|
||||
|
||||
/* Set jitter correction */
|
||||
if (!cpu_is_omap44xx()) {
|
||||
v = __raw_readl(dd->control_reg);
|
||||
v &= ~dd->freqsel_mask;
|
||||
v |= freqsel << __ffs(dd->freqsel_mask);
|
||||
__raw_writel(v, dd->control_reg);
|
||||
}
|
||||
|
||||
/* Set DPLL multiplier, divider */
|
||||
v = __raw_readl(dd->mult_div1_reg);
|
||||
v &= ~(dd->mult_mask | dd->div1_mask);
|
||||
v |= m << __ffs(dd->mult_mask);
|
||||
v |= (n - 1) << __ffs(dd->div1_mask);
|
||||
__raw_writel(v, dd->mult_div1_reg);
|
||||
|
||||
/* We let the clock framework set the other output dividers later */
|
||||
|
||||
/* REVISIT: Set ramp-up delay? */
|
||||
|
||||
_omap3_noncore_dpll_lock(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_noncore_dpll_set_rate - set non-core DPLL rate
|
||||
* @clk: struct clk * of DPLL to set
|
||||
* @rate: rounded target rate
|
||||
*
|
||||
* Set the DPLL CLKOUT to the target rate. If the DPLL can enter
|
||||
* low-power bypass, and the target rate is the bypass source clock
|
||||
* rate, then configure the DPLL for bypass. Otherwise, round the
|
||||
* target rate if it hasn't been done already, then program and lock
|
||||
* the DPLL. Returns -EINVAL upon error, or 0 upon success.
|
||||
*/
|
||||
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk *new_parent = NULL;
|
||||
u16 freqsel = 0;
|
||||
struct dpll_data *dd;
|
||||
int ret;
|
||||
|
||||
if (!clk || !rate)
|
||||
return -EINVAL;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
if (!dd)
|
||||
return -EINVAL;
|
||||
|
||||
if (rate == omap2_get_dpll_rate(clk))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* Ensure both the bypass and ref clocks are enabled prior to
|
||||
* doing anything; we need the bypass clock running to reprogram
|
||||
* the DPLL.
|
||||
*/
|
||||
omap2_clk_enable(dd->clk_bypass);
|
||||
omap2_clk_enable(dd->clk_ref);
|
||||
|
||||
if (dd->clk_bypass->rate == rate &&
|
||||
(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
|
||||
pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
|
||||
|
||||
ret = _omap3_noncore_dpll_bypass(clk);
|
||||
if (!ret)
|
||||
new_parent = dd->clk_bypass;
|
||||
} else {
|
||||
if (dd->last_rounded_rate != rate)
|
||||
omap2_dpll_round_rate(clk, rate);
|
||||
|
||||
if (dd->last_rounded_rate == 0)
|
||||
return -EINVAL;
|
||||
|
||||
/* No freqsel on OMAP4 */
|
||||
if (!cpu_is_omap44xx()) {
|
||||
freqsel = _omap3_dpll_compute_freqsel(clk,
|
||||
dd->last_rounded_n);
|
||||
if (!freqsel)
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
pr_debug("clock: %s: set rate: locking rate to %lu.\n",
|
||||
clk->name, rate);
|
||||
|
||||
ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
|
||||
dd->last_rounded_n, freqsel);
|
||||
if (!ret)
|
||||
new_parent = dd->clk_ref;
|
||||
}
|
||||
if (!ret) {
|
||||
/*
|
||||
* Switch the parent clock in the heirarchy, and make sure
|
||||
* that the new parent's usecount is correct. Note: we
|
||||
* enable the new parent before disabling the old to avoid
|
||||
* any unnecessary hardware disable->enable transitions.
|
||||
*/
|
||||
if (clk->usecount) {
|
||||
omap2_clk_enable(new_parent);
|
||||
omap2_clk_disable(clk->parent);
|
||||
}
|
||||
clk_reparent(clk, new_parent);
|
||||
clk->rate = rate;
|
||||
}
|
||||
omap2_clk_disable(dd->clk_ref);
|
||||
omap2_clk_disable(dd->clk_bypass);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* DPLL autoidle read/set code */
|
||||
|
||||
/**
|
||||
* omap3_dpll_autoidle_read - read a DPLL's autoidle bits
|
||||
* @clk: struct clk * of the DPLL to read
|
||||
*
|
||||
* Return the DPLL's autoidle bits, shifted down to bit 0. Returns
|
||||
* -EINVAL if passed a null pointer or if the struct clk does not
|
||||
* appear to refer to a DPLL.
|
||||
*/
|
||||
u32 omap3_dpll_autoidle_read(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return -EINVAL;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v &= dd->autoidle_mask;
|
||||
v >>= __ffs(dd->autoidle_mask);
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_dpll_allow_idle - enable DPLL autoidle bits
|
||||
* @clk: struct clk * of the DPLL to operate on
|
||||
*
|
||||
* Enable DPLL automatic idle control. This automatic idle mode
|
||||
* switching takes effect only when the DPLL is locked, at least on
|
||||
* OMAP3430. The DPLL will enter low-power stop when its downstream
|
||||
* clocks are gated. No return value.
|
||||
*/
|
||||
void omap3_dpll_allow_idle(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
/*
|
||||
* REVISIT: CORE DPLL can optionally enter low-power bypass
|
||||
* by writing 0x5 instead of 0x1. Add some mechanism to
|
||||
* optionally enter this mode.
|
||||
*/
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
|
||||
__raw_writel(v, dd->autoidle_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_dpll_deny_idle - prevent DPLL from automatically idling
|
||||
* @clk: struct clk * of the DPLL to operate on
|
||||
*
|
||||
* Disable DPLL automatic idle control. No return value.
|
||||
*/
|
||||
void omap3_dpll_deny_idle(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
||||
if (!clk || !clk->dpll_data)
|
||||
return;
|
||||
|
||||
dd = clk->dpll_data;
|
||||
|
||||
v = __raw_readl(dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
|
||||
__raw_writel(v, dd->autoidle_reg);
|
||||
|
||||
}
|
||||
|
||||
/* Clock control for DPLL outputs */
|
||||
|
||||
/**
|
||||
* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
|
||||
* @clk: DPLL output struct clk
|
||||
*
|
||||
* Using parent clock DPLL data, look up DPLL state. If locked, set our
|
||||
* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
|
||||
*/
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
unsigned long rate;
|
||||
u32 v;
|
||||
struct clk *pclk;
|
||||
|
||||
/* Walk up the parents of clk, looking for a DPLL */
|
||||
pclk = clk->parent;
|
||||
while (pclk && !pclk->dpll_data)
|
||||
pclk = pclk->parent;
|
||||
|
||||
/* clk does not have a DPLL as a parent? */
|
||||
WARN_ON(!pclk);
|
||||
|
||||
dd = pclk->dpll_data;
|
||||
|
||||
WARN_ON(!dd->enable_mask);
|
||||
|
||||
v = __raw_readl(dd->control_reg) & dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
if (v != OMAP3XXX_EN_DPLL_LOCKED)
|
||||
rate = clk->parent->rate;
|
||||
else
|
||||
rate = clk->parent->rate * 2;
|
||||
return rate;
|
||||
}
|
|
@ -33,17 +33,19 @@ static struct resource gpmc_smc91x_resources[] = {
|
|||
};
|
||||
|
||||
static struct smc91x_platdata gpmc_smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct platform_device gpmc_smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
|
||||
.resource = gpmc_smc91x_resources,
|
||||
.dev = {
|
||||
.platform_data = &gpmc_smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
|
||||
.resource = gpmc_smc91x_resources,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -517,7 +517,7 @@ void __init gpmc_init(void)
|
|||
ck = "gpmc_fck";
|
||||
l = OMAP34XX_GPMC_BASE;
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
ck = "gpmc_fck";
|
||||
ck = "gpmc_ck";
|
||||
l = OMAP44XX_GPMC_BASE;
|
||||
}
|
||||
|
||||
|
|
56
arch/arm/mach-omap2/i2c.c
Normal file
56
arch/arm/mach-omap2/i2c.c
Normal file
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Helper module for board specific I2C bus registration
|
||||
*
|
||||
* Copyright (C) 2009 Nokia Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/mux.h>
|
||||
|
||||
#include "mux.h"
|
||||
|
||||
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
struct i2c_board_info const *info,
|
||||
unsigned len)
|
||||
{
|
||||
if (cpu_is_omap24xx()) {
|
||||
const int omap24xx_pins[][2] = {
|
||||
{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
|
||||
{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
|
||||
};
|
||||
int scl, sda;
|
||||
|
||||
scl = omap24xx_pins[bus_id - 1][0];
|
||||
sda = omap24xx_pins[bus_id - 1][1];
|
||||
omap_cfg_reg(sda);
|
||||
omap_cfg_reg(scl);
|
||||
}
|
||||
|
||||
/* First I2C bus is not muxable */
|
||||
if (cpu_is_omap34xx() && bus_id > 1) {
|
||||
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
|
||||
|
||||
sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
|
||||
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
|
||||
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
|
||||
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
|
||||
}
|
||||
|
||||
return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
|
||||
}
|
|
@ -246,6 +246,31 @@ void __init omap3_check_revision(void)
|
|||
}
|
||||
}
|
||||
|
||||
void __init omap4_check_revision(void)
|
||||
{
|
||||
u32 idcode;
|
||||
u16 hawkeye;
|
||||
u8 rev;
|
||||
char *rev_name = "ES1.0";
|
||||
|
||||
/*
|
||||
* The IC rev detection is done with hawkeye and rev.
|
||||
* Note that rev does not map directly to defined processor
|
||||
* revision numbers as ES1.0 uses value 0.
|
||||
*/
|
||||
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
||||
hawkeye = (idcode >> 12) & 0xffff;
|
||||
rev = (idcode >> 28) & 0xff;
|
||||
|
||||
if ((hawkeye == 0xb852) && (rev == 0x0)) {
|
||||
omap_revision = OMAP4430_REV_ES1_0;
|
||||
pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_err("Unknown OMAP4 CPU id\n");
|
||||
}
|
||||
|
||||
#define OMAP3_SHOW_FEATURE(feat) \
|
||||
if (omap3_has_ ##feat()) \
|
||||
printk(#feat" ");
|
||||
|
@ -277,10 +302,10 @@ void __init omap3_cpuinfo(void)
|
|||
} else if (omap3_has_iva() && omap3_has_sgx()) {
|
||||
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
|
||||
strcpy(cpu_name, "OMAP3430/3530");
|
||||
} else if (omap3_has_sgx()) {
|
||||
} else if (omap3_has_iva()) {
|
||||
omap_revision = OMAP3525_REV(rev);
|
||||
strcpy(cpu_name, "OMAP3525");
|
||||
} else if (omap3_has_iva()) {
|
||||
} else if (omap3_has_sgx()) {
|
||||
omap_revision = OMAP3515_REV(rev);
|
||||
strcpy(cpu_name, "OMAP3515");
|
||||
} else {
|
||||
|
@ -336,7 +361,7 @@ void __init omap2_check_revision(void)
|
|||
omap3_check_features();
|
||||
omap3_cpuinfo();
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
|
||||
omap4_check_revision();
|
||||
return;
|
||||
} else {
|
||||
pr_err("OMAP revision unknown, please fix!\n");
|
||||
|
|
|
@ -33,9 +33,9 @@
|
|||
#include <plat/sdrc.h>
|
||||
#include <plat/gpmc.h>
|
||||
#include <plat/serial.h>
|
||||
#include <plat/mux.h>
|
||||
#include <plat/vram.h>
|
||||
|
||||
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
|
||||
#include "clock.h"
|
||||
|
||||
#include <plat/omap-pm.h>
|
||||
|
@ -44,7 +44,6 @@
|
|||
|
||||
#include <plat/clockdomain.h>
|
||||
#include "clockdomains.h"
|
||||
#endif
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include "omap_hwmod_2420.h"
|
||||
#include "omap_hwmod_2430.h"
|
||||
|
@ -321,8 +320,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
|
|||
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
|
||||
pwrdm_init(powerdomains_omap);
|
||||
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
|
||||
omap2_clk_init();
|
||||
#endif
|
||||
omap2_clk_init();
|
||||
omap_serial_early_init();
|
||||
#ifndef CONFIG_ARCH_OMAP4
|
||||
omap_hwmod_late_init();
|
||||
|
|
File diff suppressed because it is too large
Load Diff
163
arch/arm/mach-omap2/mux.h
Normal file
163
arch/arm/mach-omap2/mux.h
Normal file
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Nokia
|
||||
* Copyright (C) 2009 Texas Instruments
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "mux34xx.h"
|
||||
|
||||
#define OMAP_MUX_TERMINATOR 0xffff
|
||||
|
||||
/* 34xx mux mode options for each pin. See TRM for options */
|
||||
#define OMAP_MUX_MODE0 0
|
||||
#define OMAP_MUX_MODE1 1
|
||||
#define OMAP_MUX_MODE2 2
|
||||
#define OMAP_MUX_MODE3 3
|
||||
#define OMAP_MUX_MODE4 4
|
||||
#define OMAP_MUX_MODE5 5
|
||||
#define OMAP_MUX_MODE6 6
|
||||
#define OMAP_MUX_MODE7 7
|
||||
|
||||
/* 24xx/34xx mux bit defines */
|
||||
#define OMAP_PULL_ENA (1 << 3)
|
||||
#define OMAP_PULL_UP (1 << 4)
|
||||
#define OMAP_ALTELECTRICALSEL (1 << 5)
|
||||
|
||||
/* 34xx specific mux bit defines */
|
||||
#define OMAP_INPUT_EN (1 << 8)
|
||||
#define OMAP_OFF_EN (1 << 9)
|
||||
#define OMAP_OFFOUT_EN (1 << 10)
|
||||
#define OMAP_OFFOUT_VAL (1 << 11)
|
||||
#define OMAP_OFF_PULL_EN (1 << 12)
|
||||
#define OMAP_OFF_PULL_UP (1 << 13)
|
||||
#define OMAP_WAKEUP_EN (1 << 14)
|
||||
|
||||
/* Active pin states */
|
||||
#define OMAP_PIN_OUTPUT 0
|
||||
#define OMAP_PIN_INPUT OMAP_INPUT_EN
|
||||
#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
|
||||
| OMAP_PULL_UP)
|
||||
#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
|
||||
|
||||
/* Off mode states */
|
||||
#define OMAP_PIN_OFF_NONE 0
|
||||
#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
|
||||
| OMAP_OFFOUT_VAL)
|
||||
#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
|
||||
#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
|
||||
| OMAP_OFF_PULL_UP)
|
||||
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
|
||||
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
|
||||
|
||||
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
|
||||
|
||||
/* Flags for omap_mux_init */
|
||||
#define OMAP_PACKAGE_MASK 0xffff
|
||||
#define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */
|
||||
#define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */
|
||||
#define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */
|
||||
#define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */
|
||||
|
||||
|
||||
#define OMAP_MUX_NR_MODES 8 /* Available modes */
|
||||
#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
|
||||
|
||||
/**
|
||||
* struct omap_mux - data for omap mux register offset and it's value
|
||||
* @reg_offset: mux register offset from the mux base
|
||||
* @gpio: GPIO number
|
||||
* @muxnames: available signal modes for a ball
|
||||
*/
|
||||
struct omap_mux {
|
||||
u16 reg_offset;
|
||||
u16 gpio;
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
char *muxnames[OMAP_MUX_NR_MODES];
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
char *balls[OMAP_MUX_NR_SIDES];
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_ball - data for balls on omap package
|
||||
* @reg_offset: mux register offset from the mux base
|
||||
* @balls: available balls on the package
|
||||
*/
|
||||
struct omap_ball {
|
||||
u16 reg_offset;
|
||||
char *balls[OMAP_MUX_NR_SIDES];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_board_mux - data for initializing mux registers
|
||||
* @reg_offset: mux register offset from the mux base
|
||||
* @mux_value: desired mux value to set
|
||||
*/
|
||||
struct omap_board_mux {
|
||||
u16 reg_offset;
|
||||
u16 value;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX)
|
||||
|
||||
/**
|
||||
* omap_mux_init_gpio - initialize a signal based on the GPIO number
|
||||
* @gpio: GPIO number
|
||||
* @val: Options for the mux register value
|
||||
*/
|
||||
int omap_mux_init_gpio(int gpio, int val);
|
||||
|
||||
/**
|
||||
* omap_mux_init_signal - initialize a signal based on the signal name
|
||||
* @muxname: Mux name in mode0_name.signal_name format
|
||||
* @val: Options for the mux register value
|
||||
*/
|
||||
int omap_mux_init_signal(char *muxname, int val);
|
||||
|
||||
#else
|
||||
|
||||
static inline int omap_mux_init_gpio(int gpio, int val)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int omap_mux_init_signal(char *muxname, int val)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap_mux_get_gpio() - get mux register value based on GPIO number
|
||||
* @gpio: GPIO number
|
||||
*
|
||||
*/
|
||||
u16 omap_mux_get_gpio(int gpio);
|
||||
|
||||
/**
|
||||
* omap_mux_set_gpio() - set mux register value based on GPIO number
|
||||
* @val: New mux register value
|
||||
* @gpio: GPIO number
|
||||
*
|
||||
*/
|
||||
void omap_mux_set_gpio(u16 val, int gpio);
|
||||
|
||||
/**
|
||||
* omap3_mux_init() - initialize mux system with board specific set
|
||||
* @board_mux: Board specific mux table
|
||||
* @flags: OMAP package type used for the board
|
||||
*/
|
||||
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
|
||||
|
||||
/**
|
||||
* omap_mux_init - private mux init function, do not call
|
||||
*/
|
||||
int omap_mux_init(u32 mux_pbase, u32 mux_size,
|
||||
struct omap_mux *superset,
|
||||
struct omap_mux *package_subset,
|
||||
struct omap_board_mux *board_mux,
|
||||
struct omap_ball *package_balls);
|
2099
arch/arm/mach-omap2/mux34xx.c
Normal file
2099
arch/arm/mach-omap2/mux34xx.c
Normal file
File diff suppressed because it is too large
Load Diff
398
arch/arm/mach-omap2/mux34xx.h
Normal file
398
arch/arm/mach-omap2/mux34xx.h
Normal file
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* Copyright (C) 2009 Nokia
|
||||
* Copyright (C) 2009 Texas Instruments
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
|
||||
|
||||
#define OMAP3_MUX(mode0, mux_value) \
|
||||
{ \
|
||||
.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
|
||||
.value = (mux_value), \
|
||||
}
|
||||
|
||||
/*
|
||||
* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
|
||||
*
|
||||
* Extracted from the TRM. Add 0x48002030 to these values to get the
|
||||
* absolute addresses. The name in the macro is the mode-0 name of
|
||||
* the pin. NOTE: These registers are 16-bits wide.
|
||||
*
|
||||
* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
|
||||
* of CHASSIS for some registers. For the defines, we follow the
|
||||
* 36XX naming, and use SDMMC and CHASSIS.
|
||||
*/
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
|
||||
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
|
||||
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
|
||||
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
|
||||
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
|
||||
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
|
||||
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
|
||||
|
||||
/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
|
||||
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
|
||||
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
|
||||
#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
|
||||
#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
|
||||
#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
|
||||
#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
|
||||
#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
|
||||
#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
|
||||
#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
|
||||
#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
|
||||
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
|
||||
#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
|
||||
#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
|
||||
#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
|
||||
#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
|
||||
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
|
||||
#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
|
||||
#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
|
||||
#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
|
||||
#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
|
||||
#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
|
||||
#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
|
||||
#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
|
||||
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
|
||||
|
||||
/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
|
||||
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
|
||||
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
|
||||
|
||||
/* 36xx only */
|
||||
#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
|
||||
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
|
||||
|
||||
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
|
||||
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
|
||||
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
|
||||
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
|
||||
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
|
||||
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
|
||||
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
|
||||
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
|
||||
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
|
||||
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
|
||||
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
|
||||
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
|
||||
|
||||
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
|
||||
(OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2)
|
|
@ -27,20 +27,39 @@
|
|||
* OMAP4 specific entry point for secondary CPU to jump from ROM
|
||||
* code. This routine also provides a holding flag into which
|
||||
* secondary core is held until we're ready for it to initialise.
|
||||
* The primary core will update the this flag using a hardware
|
||||
* register AuxCoreBoot1.
|
||||
* The primary core will update this flag using a hardware
|
||||
* register AuxCoreBoot0.
|
||||
*/
|
||||
ENTRY(omap_secondary_startup)
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #0x0f
|
||||
hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1
|
||||
ldr r2, [r1]
|
||||
cmp r2, r0
|
||||
hold: ldr r12,=0x103
|
||||
dsb
|
||||
smc @ read from AuxCoreBoot0
|
||||
mov r0, r0, lsr #9
|
||||
mrc p15, 0, r4, c0, c0, 5
|
||||
and r4, r4, #0x0f
|
||||
cmp r0, r4
|
||||
bne hold
|
||||
|
||||
/*
|
||||
* we've been released from the cpu_release,secondary_stack
|
||||
* we've been released from the wait loop,secondary_stack
|
||||
* should now contain the SVC stack for this core
|
||||
*/
|
||||
b secondary_startup
|
||||
END(omap_secondary_startup)
|
||||
|
||||
|
||||
ENTRY(omap_modify_auxcoreboot0)
|
||||
stmfd sp!, {r1-r12, lr}
|
||||
ldr r12, =0x104
|
||||
dsb
|
||||
smc
|
||||
ldmfd sp!, {r1-r12, pc}
|
||||
END(omap_modify_auxcoreboot0)
|
||||
|
||||
ENTRY(omap_auxcoreboot_addr)
|
||||
stmfd sp!, {r2-r12, lr}
|
||||
ldr r12, =0x105
|
||||
dsb
|
||||
smc
|
||||
ldmfd sp!, {r2-r12, pc}
|
||||
END(omap_auxcoreboot_addr)
|
||||
|
|
|
@ -17,19 +17,15 @@
|
|||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/localtimer.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <plat/common.h>
|
||||
|
||||
/* Registers used for communicating startup information */
|
||||
static void __iomem *omap4_auxcoreboot_reg0;
|
||||
static void __iomem *omap4_auxcoreboot_reg1;
|
||||
|
||||
/* SCU base address */
|
||||
static void __iomem *scu_base;
|
||||
|
||||
|
@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
|||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/*
|
||||
* Set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
|
@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
spin_lock(&boot_lock);
|
||||
|
||||
/*
|
||||
* Update the AuxCoreBoot1 with boot state for secondary core.
|
||||
* Update the AuxCoreBoot0 with boot state for secondary core.
|
||||
* omap_secondary_startup() routine will hold the secondary core till
|
||||
* the AuxCoreBoot1 register is updated with cpu state
|
||||
* A barrier is added to ensure that write buffer is drained
|
||||
*/
|
||||
__raw_writel(cpu, omap4_auxcoreboot_reg1);
|
||||
omap_modify_auxcoreboot0(0x200, 0x0);
|
||||
flush_cache_all();
|
||||
smp_wmb();
|
||||
|
||||
timeout = jiffies + (1 * HZ);
|
||||
while (time_before(jiffies, timeout))
|
||||
;
|
||||
|
||||
/*
|
||||
* Now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
|
@ -99,17 +90,18 @@ static void __init wakeup_secondary(void)
|
|||
{
|
||||
/*
|
||||
* Write the address of secondary startup routine into the
|
||||
* AuxCoreBoot0 where ROM code will jump and start executing
|
||||
* AuxCoreBoot1 where ROM code will jump and start executing
|
||||
* on secondary core once out of WFE
|
||||
* A barrier is added to ensure that write buffer is drained
|
||||
*/
|
||||
__raw_writel(virt_to_phys(omap_secondary_startup), \
|
||||
omap4_auxcoreboot_reg0);
|
||||
omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
|
||||
smp_wmb();
|
||||
|
||||
/*
|
||||
* Send a 'sev' to wake the secondary core from WFE.
|
||||
* Drain the outstanding writes to memory
|
||||
*/
|
||||
dsb();
|
||||
set_event();
|
||||
mb();
|
||||
}
|
||||
|
@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
|
|||
{
|
||||
unsigned int ncores = get_core_count();
|
||||
unsigned int cpu = smp_processor_id();
|
||||
void __iomem *omap4_wkupgen_base;
|
||||
int i;
|
||||
|
||||
/* sanity check */
|
||||
|
@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
|
|||
for (i = 0; i < max_cpus; i++)
|
||||
set_cpu_present(i, true);
|
||||
|
||||
/* Never released */
|
||||
omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
|
||||
BUG_ON(!omap4_wkupgen_base);
|
||||
omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
|
||||
omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
|
||||
|
||||
if (max_cpus > 1) {
|
||||
/*
|
||||
* Enable the local timer or broadcast device for the
|
||||
|
|
|
@ -45,6 +45,7 @@
|
|||
#include <linux/mutex.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <plat/common.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clockdomain.h>
|
||||
#include <plat/powerdomain.h>
|
||||
|
@ -209,6 +210,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
|
||||
* @oh: struct omap_hwmod *
|
||||
* @autoidle: desired AUTOIDLE bitfield value (0 or 1)
|
||||
* @v: pointer to register contents to modify
|
||||
*
|
||||
* Update the module autoidle bit in @v to be @autoidle for the @oh
|
||||
* hwmod. The autoidle bit controls whether the module can gate
|
||||
* internal clocks automatically when it isn't doing anything; the
|
||||
* exact function of this bit varies on a per-module basis. This
|
||||
* function does not write to the hardware. Returns -EINVAL upon
|
||||
* error or 0 upon success.
|
||||
*/
|
||||
static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
|
||||
u32 *v)
|
||||
{
|
||||
if (!oh->sysconfig ||
|
||||
!(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE))
|
||||
return -EINVAL;
|
||||
|
||||
*v &= ~SYSC_AUTOIDLE_MASK;
|
||||
*v |= autoidle << SYSC_AUTOIDLE_SHIFT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
|
||||
* @oh: struct omap_hwmod *
|
||||
|
@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh)
|
|||
ret = -EINVAL;
|
||||
oh->_clk = c;
|
||||
|
||||
WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
|
||||
oh->clkdev_con_id, c->name);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh)
|
|||
_set_master_standbymode(oh, idlemode, &v);
|
||||
}
|
||||
|
||||
/* XXX OCP AUTOIDLE bit? */
|
||||
if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) {
|
||||
idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
|
||||
0 : 1;
|
||||
_set_module_autoidle(oh, idlemode, &v);
|
||||
}
|
||||
|
||||
/* XXX OCP ENAWAKEUP bit? */
|
||||
|
||||
/*
|
||||
* XXX The clock framework should handle this, by
|
||||
* calling into this code. But this must wait until the
|
||||
* clock structures are tagged with omap_hwmod entries
|
||||
*/
|
||||
if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
|
||||
oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
|
||||
_set_clockactivity(oh, oh->sysconfig->clockact, &v);
|
||||
|
@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh)
|
|||
if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
|
||||
_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
|
||||
|
||||
/* XXX clear OCP AUTOIDLE bit? */
|
||||
if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)
|
||||
_set_module_autoidle(oh, 1, &v);
|
||||
|
||||
_write_sysconfig(v, oh);
|
||||
}
|
||||
|
@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
|
|||
static int _reset(struct omap_hwmod *oh)
|
||||
{
|
||||
u32 r, v;
|
||||
int c;
|
||||
int c = 0;
|
||||
|
||||
if (!oh->sysconfig ||
|
||||
!(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
|
||||
|
@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh)
|
|||
return r;
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
c = 0;
|
||||
while (c < MAX_MODULE_RESET_WAIT &&
|
||||
!(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
|
||||
SYSS_RESETDONE_MASK)) {
|
||||
udelay(1);
|
||||
c++;
|
||||
}
|
||||
omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
|
||||
SYSS_RESETDONE_MASK),
|
||||
MAX_MODULE_RESET_WAIT, c);
|
||||
|
||||
if (c == MAX_MODULE_RESET_WAIT)
|
||||
WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
|
||||
|
@ -883,33 +921,6 @@ static int _shutdown(struct omap_hwmod *oh)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* _write_clockact_lock - set the module's clockactivity bits
|
||||
* @oh: struct omap_hwmod *
|
||||
* @clockact: CLOCKACTIVITY field bits
|
||||
*
|
||||
* Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
|
||||
* OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the
|
||||
* wrong state or returns 0.
|
||||
*/
|
||||
static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (!oh->sysconfig ||
|
||||
!(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&omap_hwmod_mutex);
|
||||
v = oh->_sysc_cache;
|
||||
_set_clockactivity(oh, clockact, &v);
|
||||
_write_sysconfig(v, oh);
|
||||
mutex_unlock(&omap_hwmod_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* _setup - do initial configuration of omap_hwmod
|
||||
* @oh: struct omap_hwmod *
|
||||
|
@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh)
|
|||
|
||||
_enable(oh);
|
||||
|
||||
if (!(oh->flags & HWMOD_INIT_NO_RESET))
|
||||
_reset(oh);
|
||||
|
||||
/* XXX OCP AUTOIDLE bit? */
|
||||
/* XXX OCP ENAWAKEUP bit? */
|
||||
if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
|
||||
/*
|
||||
* XXX Do the OCP_SYSCONFIG bits need to be
|
||||
* reprogrammed after a reset? If not, then this can
|
||||
* be removed. If they do, then probably the
|
||||
* _enable() function should be split to avoid the
|
||||
* rewrite of the OCP_SYSCONFIG register.
|
||||
*/
|
||||
if (oh->sysconfig) {
|
||||
_update_sysc_cache(oh);
|
||||
_sysc_enable(oh);
|
||||
}
|
||||
}
|
||||
|
||||
if (!(oh->flags & HWMOD_INIT_NO_IDLE))
|
||||
_idle(oh);
|
||||
|
@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
|
|||
/* For each IRQ, DMA, memory area, fill in array.*/
|
||||
|
||||
for (i = 0; i < oh->mpu_irqs_cnt; i++) {
|
||||
(res + r)->start = *(oh->mpu_irqs + i);
|
||||
(res + r)->end = *(oh->mpu_irqs + i);
|
||||
(res + r)->name = (oh->mpu_irqs + i)->name;
|
||||
(res + r)->start = (oh->mpu_irqs + i)->irq;
|
||||
(res + r)->end = (oh->mpu_irqs + i)->irq;
|
||||
(res + r)->flags = IORESOURCE_IRQ;
|
||||
r++;
|
||||
}
|
||||
|
@ -1453,62 +1473,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
|
|||
return _del_initiator_dep(oh, init_oh);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_set_clockact_none - set clockactivity test to BOTH
|
||||
* @oh: struct omap_hwmod *
|
||||
*
|
||||
* On some modules, this function can affect the wakeup latency vs.
|
||||
* power consumption balance. Intended to be called by the
|
||||
* omap_device layer. Passes along the return value from
|
||||
* _write_clockact_lock().
|
||||
*/
|
||||
int omap_hwmod_set_clockact_both(struct omap_hwmod *oh)
|
||||
{
|
||||
return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_set_clockact_none - set clockactivity test to MAIN
|
||||
* @oh: struct omap_hwmod *
|
||||
*
|
||||
* On some modules, this function can affect the wakeup latency vs.
|
||||
* power consumption balance. Intended to be called by the
|
||||
* omap_device layer. Passes along the return value from
|
||||
* _write_clockact_lock().
|
||||
*/
|
||||
int omap_hwmod_set_clockact_main(struct omap_hwmod *oh)
|
||||
{
|
||||
return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_set_clockact_none - set clockactivity test to ICLK
|
||||
* @oh: struct omap_hwmod *
|
||||
*
|
||||
* On some modules, this function can affect the wakeup latency vs.
|
||||
* power consumption balance. Intended to be called by the
|
||||
* omap_device layer. Passes along the return value from
|
||||
* _write_clockact_lock().
|
||||
*/
|
||||
int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh)
|
||||
{
|
||||
return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_set_clockact_none - set clockactivity test to NONE
|
||||
* @oh: struct omap_hwmod *
|
||||
*
|
||||
* On some modules, this function can affect the wakeup latency vs.
|
||||
* power consumption balance. Intended to be called by the
|
||||
* omap_device layer. Passes along the return value from
|
||||
* _write_clockact_lock().
|
||||
*/
|
||||
int omap_hwmod_set_clockact_none(struct omap_hwmod *oh)
|
||||
{
|
||||
return _write_clockact_lock(oh, CLOCKACT_TEST_NONE);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_hwmod_enable_wakeup - allow device to wake up the system
|
||||
* @oh: struct omap_hwmod *
|
||||
|
|
126
arch/arm/mach-omap2/opp2420_data.c
Normal file
126
arch/arm/mach-omap2/opp2420_data.c
Normal file
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* opp2420_data.c - old-style "OPP" table for OMAP2420
|
||||
*
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
|
||||
* These configurations are characterized by voltage and speed for clocks.
|
||||
* The device is only validated for certain combinations. One way to express
|
||||
* these combinations is via the 'ratio's' which the clocks operate with
|
||||
* respect to each other. These ratio sets are for a given voltage/DPLL
|
||||
* setting. All configurations can be described by a DPLL setting and a ratio
|
||||
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
|
||||
*
|
||||
* 2430 differs from 2420 in that there are no more phase synchronizers used.
|
||||
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
|
||||
* 2430 (iva2.1, NOdsp, mdm)
|
||||
*
|
||||
* XXX Missing voltage data.
|
||||
*
|
||||
* THe format described in this file is deprecated. Once a reasonable
|
||||
* OPP API exists, the data in this file should be converted to use it.
|
||||
*
|
||||
* This is technically part of the OMAP2xxx clock code.
|
||||
*/
|
||||
|
||||
#include "opp2xxx.h"
|
||||
#include "sdrc.h"
|
||||
#include "clock.h"
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
|
||||
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
|
||||
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
|
||||
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
|
||||
*
|
||||
* Filling in table based on H4 boards and 2430-SDPs variants available.
|
||||
* There are quite a few more rates combinations which could be defined.
|
||||
*
|
||||
* When multiple values are defined the start up will try and choose the
|
||||
* fastest one. If a 'fast' value is defined, then automatically, the /2
|
||||
* one should be included as it can be used. Generally having more that
|
||||
* one fast set does not make sense, as static timings need to be changed
|
||||
* to change the set. The exception is the bypass setting which is
|
||||
* availble for low power bypass.
|
||||
*
|
||||
* Note: This table needs to be sorted, fastest to slowest.
|
||||
*-------------------------------------------------------------------------*/
|
||||
const struct prcm_config omap2420_rate_table[] = {
|
||||
/* PRCM I - FAST */
|
||||
{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
|
||||
RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
|
||||
RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM II - FAST */
|
||||
{S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM III - FAST */
|
||||
{S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM II - SLOW */
|
||||
{S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
|
||||
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
|
||||
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM III - SLOW */
|
||||
{S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
{S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
|
||||
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
|
||||
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM-VII (boot-bypass) */
|
||||
{S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
|
||||
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
|
||||
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_242X},
|
||||
|
||||
/* PRCM-VII (boot-bypass) */
|
||||
{S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
|
||||
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
|
||||
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_242X},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
133
arch/arm/mach-omap2/opp2430_data.c
Normal file
133
arch/arm/mach-omap2/opp2430_data.c
Normal file
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* opp2420_data.c - old-style "OPP" table for OMAP2420
|
||||
*
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
|
||||
* These configurations are characterized by voltage and speed for clocks.
|
||||
* The device is only validated for certain combinations. One way to express
|
||||
* these combinations is via the 'ratio's' which the clocks operate with
|
||||
* respect to each other. These ratio sets are for a given voltage/DPLL
|
||||
* setting. All configurations can be described by a DPLL setting and a ratio
|
||||
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
|
||||
*
|
||||
* 2430 differs from 2420 in that there are no more phase synchronizers used.
|
||||
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
|
||||
* 2430 (iva2.1, NOdsp, mdm)
|
||||
*
|
||||
* XXX Missing voltage data.
|
||||
*
|
||||
* THe format described in this file is deprecated. Once a reasonable
|
||||
* OPP API exists, the data in this file should be converted to use it.
|
||||
*
|
||||
* This is technically part of the OMAP2xxx clock code.
|
||||
*/
|
||||
|
||||
#include "opp2xxx.h"
|
||||
#include "sdrc.h"
|
||||
#include "clock.h"
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
|
||||
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
|
||||
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
|
||||
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
|
||||
*
|
||||
* Filling in table based on H4 boards and 2430-SDPs variants available.
|
||||
* There are quite a few more rates combinations which could be defined.
|
||||
*
|
||||
* When multiple values are defined the start up will try and choose the
|
||||
* fastest one. If a 'fast' value is defined, then automatically, the /2
|
||||
* one should be included as it can be used. Generally having more that
|
||||
* one fast set does not make sense, as static timings need to be changed
|
||||
* to change the set. The exception is the bypass setting which is
|
||||
* availble for low power bypass.
|
||||
*
|
||||
* Note: This table needs to be sorted, fastest to slowest.
|
||||
*-------------------------------------------------------------------------*/
|
||||
const struct prcm_config omap2430_rate_table[] = {
|
||||
/* PRCM #4 - ratio2 (ES2.1) - FAST */
|
||||
{S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
|
||||
R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
|
||||
R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #2 - ratio1 (ES2) - FAST */
|
||||
{S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_165MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5a - ratio1 - FAST */
|
||||
{S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5b - ratio1 - FAST */
|
||||
{S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #4 - ratio1 (ES2.1) - SLOW */
|
||||
{S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
|
||||
R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
|
||||
R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #2 - ratio1 (ES2) - SLOW */
|
||||
{S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_165MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5a - ratio1 - SLOW */
|
||||
{S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_133MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM #5b - ratio1 - SLOW*/
|
||||
{S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
|
||||
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
|
||||
R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_100MHz,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM-boot/bypass */
|
||||
{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
|
||||
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
|
||||
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_243X},
|
||||
|
||||
/* PRCM-boot/bypass */
|
||||
{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
|
||||
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
|
||||
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
|
||||
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
|
||||
SDRC_RFR_CTRL_BYPASS,
|
||||
RATE_IN_243X},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
424
arch/arm/mach-omap2/opp2xxx.h
Normal file
424
arch/arm/mach-omap2/opp2xxx.h
Normal file
|
@ -0,0 +1,424 @@
|
|||
/*
|
||||
* opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
|
||||
*
|
||||
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2004-2009 Nokia Corporation
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
|
||||
* These configurations are characterized by voltage and speed for clocks.
|
||||
* The device is only validated for certain combinations. One way to express
|
||||
* these combinations is via the 'ratio's' which the clocks operate with
|
||||
* respect to each other. These ratio sets are for a given voltage/DPLL
|
||||
* setting. All configurations can be described by a DPLL setting and a ratio
|
||||
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
|
||||
*
|
||||
* 2430 differs from 2420 in that there are no more phase synchronizers used.
|
||||
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
|
||||
* 2430 (iva2.1, NOdsp, mdm)
|
||||
*
|
||||
* XXX Missing voltage data.
|
||||
*
|
||||
* THe format described in this file is deprecated. Once a reasonable
|
||||
* OPP API exists, the data in this file should be converted to use it.
|
||||
*
|
||||
* This is technically part of the OMAP2xxx clock code.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
|
||||
|
||||
/**
|
||||
* struct prcm_config - define clock rates on a per-OPP basis (24xx)
|
||||
*
|
||||
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
|
||||
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
|
||||
* CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
|
||||
*
|
||||
* This is deprecated. As soon as we have a decent OPP API, we should
|
||||
* move all this stuff to it.
|
||||
*/
|
||||
struct prcm_config {
|
||||
unsigned long xtal_speed; /* crystal rate */
|
||||
unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
|
||||
unsigned long mpu_speed; /* speed of MPU */
|
||||
unsigned long cm_clksel_mpu; /* mpu divider */
|
||||
unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
|
||||
unsigned long cm_clksel_gfx; /* gfx dividers */
|
||||
unsigned long cm_clksel1_core; /* major subsystem dividers */
|
||||
unsigned long cm_clksel1_pll; /* m,n */
|
||||
unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
|
||||
unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
|
||||
unsigned long base_sdrc_rfr; /* base refresh timing for a set */
|
||||
unsigned char flags;
|
||||
};
|
||||
|
||||
|
||||
/* Core fields for cm_clksel, not ratio governed */
|
||||
#define RX_CLKSEL_DSS1 (0x10 << 8)
|
||||
#define RX_CLKSEL_DSS2 (0x0 << 13)
|
||||
#define RX_CLKSEL_SSI (0x5 << 20)
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Voltage/DPLL ratios
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* 2430 Ratio's, 2430-Ratio Config 1 */
|
||||
#define R1_CLKSEL_L3 (4 << 0)
|
||||
#define R1_CLKSEL_L4 (2 << 5)
|
||||
#define R1_CLKSEL_USB (4 << 25)
|
||||
#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
R1_CLKSEL_L4 | R1_CLKSEL_L3)
|
||||
#define R1_CLKSEL_MPU (2 << 0)
|
||||
#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
|
||||
#define R1_CLKSEL_DSP (2 << 0)
|
||||
#define R1_CLKSEL_DSP_IF (2 << 5)
|
||||
#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
|
||||
#define R1_CLKSEL_GFX (2 << 0)
|
||||
#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
|
||||
#define R1_CLKSEL_MDM (4 << 0)
|
||||
#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
|
||||
|
||||
/* 2430-Ratio Config 2 */
|
||||
#define R2_CLKSEL_L3 (6 << 0)
|
||||
#define R2_CLKSEL_L4 (2 << 5)
|
||||
#define R2_CLKSEL_USB (2 << 25)
|
||||
#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
R2_CLKSEL_L4 | R2_CLKSEL_L3)
|
||||
#define R2_CLKSEL_MPU (2 << 0)
|
||||
#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
|
||||
#define R2_CLKSEL_DSP (2 << 0)
|
||||
#define R2_CLKSEL_DSP_IF (3 << 5)
|
||||
#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
|
||||
#define R2_CLKSEL_GFX (2 << 0)
|
||||
#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
|
||||
#define R2_CLKSEL_MDM (6 << 0)
|
||||
#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
|
||||
|
||||
/* 2430-Ratio Bootm (BYPASS) */
|
||||
#define RB_CLKSEL_L3 (1 << 0)
|
||||
#define RB_CLKSEL_L4 (1 << 5)
|
||||
#define RB_CLKSEL_USB (1 << 25)
|
||||
#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
RB_CLKSEL_L4 | RB_CLKSEL_L3)
|
||||
#define RB_CLKSEL_MPU (1 << 0)
|
||||
#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
|
||||
#define RB_CLKSEL_DSP (1 << 0)
|
||||
#define RB_CLKSEL_DSP_IF (1 << 5)
|
||||
#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
|
||||
#define RB_CLKSEL_GFX (1 << 0)
|
||||
#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
|
||||
#define RB_CLKSEL_MDM (1 << 0)
|
||||
#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
|
||||
|
||||
/* 2420 Ratio Equivalents */
|
||||
#define RXX_CLKSEL_VLYNQ (0x12 << 15)
|
||||
#define RXX_CLKSEL_SSI (0x8 << 20)
|
||||
|
||||
/* 2420-PRCM III 532MHz core */
|
||||
#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
|
||||
#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
|
||||
#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
|
||||
#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
|
||||
RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
|
||||
RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
|
||||
RIII_CLKSEL_L3)
|
||||
#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
|
||||
#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
|
||||
#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
|
||||
#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
|
||||
#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
|
||||
#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
|
||||
#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
|
||||
#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
|
||||
RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
|
||||
RIII_CLKSEL_DSP)
|
||||
#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
|
||||
#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
|
||||
|
||||
/* 2420-PRCM II 600MHz core */
|
||||
#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
|
||||
#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
|
||||
#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
|
||||
#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
|
||||
RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
|
||||
RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
|
||||
RII_CLKSEL_L3)
|
||||
#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
|
||||
#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
|
||||
#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
|
||||
#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
|
||||
#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
|
||||
#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
|
||||
#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
|
||||
#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
|
||||
RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
|
||||
RII_CLKSEL_DSP)
|
||||
#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
|
||||
#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
|
||||
|
||||
/* 2420-PRCM I 660MHz core */
|
||||
#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
|
||||
#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
|
||||
#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
|
||||
#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
|
||||
RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
|
||||
RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
|
||||
RI_CLKSEL_L4 | RI_CLKSEL_L3)
|
||||
#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
|
||||
#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
|
||||
#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
|
||||
#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
|
||||
#define RI_SYNC_DSP (1 << 7) /* Activate sync */
|
||||
#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
|
||||
#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
|
||||
#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
|
||||
RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
|
||||
RI_CLKSEL_DSP)
|
||||
#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
|
||||
#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
|
||||
|
||||
/* 2420-PRCM VII (boot) */
|
||||
#define RVII_CLKSEL_L3 (1 << 0)
|
||||
#define RVII_CLKSEL_L4 (1 << 5)
|
||||
#define RVII_CLKSEL_DSS1 (1 << 8)
|
||||
#define RVII_CLKSEL_DSS2 (0 << 13)
|
||||
#define RVII_CLKSEL_VLYNQ (1 << 15)
|
||||
#define RVII_CLKSEL_SSI (1 << 20)
|
||||
#define RVII_CLKSEL_USB (1 << 25)
|
||||
|
||||
#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
|
||||
RVII_CLKSEL_VLYNQ | \
|
||||
RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
|
||||
RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
|
||||
|
||||
#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
|
||||
#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
|
||||
|
||||
#define RVII_CLKSEL_DSP (1 << 0)
|
||||
#define RVII_CLKSEL_DSP_IF (1 << 5)
|
||||
#define RVII_SYNC_DSP (0 << 7)
|
||||
#define RVII_CLKSEL_IVA (1 << 8)
|
||||
#define RVII_SYNC_IVA (0 << 13)
|
||||
#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
|
||||
RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
|
||||
RVII_CLKSEL_DSP)
|
||||
|
||||
#define RVII_CLKSEL_GFX (1 << 0)
|
||||
#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* 2430 Target modes: Along with each configuration the CPU has several
|
||||
* modes which goes along with them. Modes mainly are the addition of
|
||||
* describe DPLL combinations to go along with a ratio.
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
/* Hardware governed */
|
||||
#define MX_48M_SRC (0 << 3)
|
||||
#define MX_54M_SRC (0 << 5)
|
||||
#define MX_APLLS_CLIKIN_12 (3 << 23)
|
||||
#define MX_APLLS_CLIKIN_13 (2 << 23)
|
||||
#define MX_APLLS_CLIKIN_19_2 (0 << 23)
|
||||
|
||||
/*
|
||||
* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
|
||||
* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
|
||||
*/
|
||||
#define M5A_DPLL_MULT_12 (133 << 12)
|
||||
#define M5A_DPLL_DIV_12 (5 << 8)
|
||||
#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
#define M5A_DPLL_MULT_13 (61 << 12)
|
||||
#define M5A_DPLL_DIV_13 (2 << 8)
|
||||
#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
#define M5A_DPLL_MULT_19 (55 << 12)
|
||||
#define M5A_DPLL_DIV_19 (3 << 8)
|
||||
#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2)
|
||||
/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
|
||||
#define M5B_DPLL_MULT_12 (50 << 12)
|
||||
#define M5B_DPLL_DIV_12 (2 << 8)
|
||||
#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
#define M5B_DPLL_MULT_13 (200 << 12)
|
||||
#define M5B_DPLL_DIV_13 (12 << 8)
|
||||
|
||||
#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
#define M5B_DPLL_MULT_19 (125 << 12)
|
||||
#define M5B_DPLL_DIV_19 (31 << 8)
|
||||
#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2)
|
||||
/*
|
||||
* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
|
||||
*/
|
||||
#define M4_DPLL_MULT_12 (133 << 12)
|
||||
#define M4_DPLL_DIV_12 (3 << 8)
|
||||
#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
|
||||
#define M4_DPLL_MULT_13 (399 << 12)
|
||||
#define M4_DPLL_DIV_13 (12 << 8)
|
||||
#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
|
||||
#define M4_DPLL_MULT_19 (145 << 12)
|
||||
#define M4_DPLL_DIV_19 (6 << 8)
|
||||
#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2)
|
||||
|
||||
/*
|
||||
* #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
|
||||
*/
|
||||
#define M3_DPLL_MULT_12 (55 << 12)
|
||||
#define M3_DPLL_DIV_12 (1 << 8)
|
||||
#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
#define M3_DPLL_MULT_13 (76 << 12)
|
||||
#define M3_DPLL_DIV_13 (2 << 8)
|
||||
#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
#define M3_DPLL_MULT_19 (17 << 12)
|
||||
#define M3_DPLL_DIV_19 (0 << 8)
|
||||
#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2)
|
||||
|
||||
/*
|
||||
* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
|
||||
*/
|
||||
#define M2_DPLL_MULT_12 (55 << 12)
|
||||
#define M2_DPLL_DIV_12 (1 << 8)
|
||||
#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
|
||||
/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
|
||||
* relock time issue */
|
||||
/* Core frequency changed from 330/165 to 329/164 MHz*/
|
||||
#define M2_DPLL_MULT_13 (76 << 12)
|
||||
#define M2_DPLL_DIV_13 (2 << 8)
|
||||
#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
|
||||
#define M2_DPLL_MULT_19 (17 << 12)
|
||||
#define M2_DPLL_DIV_19 (0 << 8)
|
||||
#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
|
||||
MX_APLLS_CLIKIN_19_2)
|
||||
|
||||
/* boot (boot) */
|
||||
#define MB_DPLL_MULT (1 << 12)
|
||||
#define MB_DPLL_DIV (0 << 8)
|
||||
#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MB_DPLL_DIV | MB_DPLL_MULT | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
|
||||
#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MB_DPLL_DIV | MB_DPLL_MULT | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
|
||||
#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MB_DPLL_DIV | MB_DPLL_MULT | \
|
||||
MX_APLLS_CLIKIN_19)
|
||||
|
||||
/*
|
||||
* 2430 - chassis (sedna)
|
||||
* 165 (ratio1) same as above #2
|
||||
* 150 (ratio1)
|
||||
* 133 (ratio2) same as above #4
|
||||
* 110 (ratio2) same as above #3
|
||||
* 104 (ratio2)
|
||||
* boot (boot)
|
||||
*/
|
||||
|
||||
/* PRCM I target DPLL = 2*330MHz = 660MHz */
|
||||
#define MI_DPLL_MULT_12 (55 << 12)
|
||||
#define MI_DPLL_DIV_12 (1 << 8)
|
||||
#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
|
||||
/*
|
||||
* 2420 Equivalent - mode registers
|
||||
* PRCM II , target DPLL = 2*300MHz = 600MHz
|
||||
*/
|
||||
#define MII_DPLL_MULT_12 (50 << 12)
|
||||
#define MII_DPLL_DIV_12 (1 << 8)
|
||||
#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
|
||||
MX_APLLS_CLIKIN_12)
|
||||
#define MII_DPLL_MULT_13 (300 << 12)
|
||||
#define MII_DPLL_DIV_13 (12 << 8)
|
||||
#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
|
||||
MX_APLLS_CLIKIN_13)
|
||||
|
||||
/* PRCM III target DPLL = 2*266 = 532MHz*/
|
||||
#define MIII_DPLL_MULT_12 (133 << 12)
|
||||
#define MIII_DPLL_DIV_12 (5 << 8)
|
||||
#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MIII_DPLL_DIV_12 | \
|
||||
MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
|
||||
#define MIII_DPLL_MULT_13 (266 << 12)
|
||||
#define MIII_DPLL_DIV_13 (12 << 8)
|
||||
#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
|
||||
MIII_DPLL_DIV_13 | \
|
||||
MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
|
||||
|
||||
/* PRCM VII (boot bypass) */
|
||||
#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
|
||||
#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
|
||||
|
||||
/* High and low operation value */
|
||||
#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
|
||||
#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
|
||||
|
||||
/* MPU speed defines */
|
||||
#define S12M 12000000
|
||||
#define S13M 13000000
|
||||
#define S19M 19200000
|
||||
#define S26M 26000000
|
||||
#define S100M 100000000
|
||||
#define S133M 133000000
|
||||
#define S150M 150000000
|
||||
#define S164M 164000000
|
||||
#define S165M 165000000
|
||||
#define S199M 199000000
|
||||
#define S200M 200000000
|
||||
#define S266M 266000000
|
||||
#define S300M 300000000
|
||||
#define S329M 329000000
|
||||
#define S330M 330000000
|
||||
#define S399M 399000000
|
||||
#define S400M 400000000
|
||||
#define S532M 532000000
|
||||
#define S600M 600000000
|
||||
#define S658M 658000000
|
||||
#define S660M 660000000
|
||||
#define S798M 798000000
|
||||
|
||||
|
||||
extern const struct prcm_config omap2420_rate_table[];
|
||||
extern const struct prcm_config omap2430_rate_table[];
|
||||
extern const struct prcm_config *rate_table;
|
||||
extern const struct prcm_config *curr_prcm_set;
|
||||
|
||||
#endif
|
|
@ -326,7 +326,7 @@ int pm_dbg_regset_save(int reg_set)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const char pwrdm_state_names[][4] = {
|
||||
static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
|
||||
"OFF",
|
||||
"RET",
|
||||
"INA",
|
||||
|
@ -381,7 +381,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
|
|||
|
||||
seq_printf(s, "%s (%s)", pwrdm->name,
|
||||
pwrdm_state_names[pwrdm->state]);
|
||||
for (i = 0; i < 4; i++)
|
||||
for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
|
||||
seq_printf(s, ",%s:%d", pwrdm_state_names[i],
|
||||
pwrdm->state_counter[i]);
|
||||
|
||||
|
|
|
@ -10,9 +10,7 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN
|
||||
# define DEBUG
|
||||
#endif
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
|
@ -160,7 +158,7 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm)
|
|||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
|
||||
pwrdm->state_counter[i] = 0;
|
||||
|
||||
pwrdm_wait_transition(pwrdm);
|
||||
|
@ -480,7 +478,7 @@ int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
if (IS_ERR(p)) {
|
||||
pr_debug("powerdomain: hardware cannot set/clear wake up of "
|
||||
"%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
|
||||
return IS_ERR(p);
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
|
||||
|
@ -513,7 +511,7 @@ int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
if (IS_ERR(p)) {
|
||||
pr_debug("powerdomain: hardware cannot set/clear wake up of "
|
||||
"%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
|
||||
return IS_ERR(p);
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
pr_debug("powerdomain: hardware will no longer wake up %s after %s "
|
||||
|
@ -550,7 +548,7 @@ int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
if (IS_ERR(p)) {
|
||||
pr_debug("powerdomain: hardware cannot set/clear wake up of "
|
||||
"%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
|
||||
return IS_ERR(p);
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
|
||||
|
@ -573,10 +571,10 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
{
|
||||
struct powerdomain *p;
|
||||
|
||||
if (!pwrdm1)
|
||||
if (!cpu_is_omap34xx())
|
||||
return -EINVAL;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
if (!pwrdm1)
|
||||
return -EINVAL;
|
||||
|
||||
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
|
||||
|
@ -584,7 +582,7 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
pr_debug("powerdomain: hardware cannot set/clear sleep "
|
||||
"dependency affecting %s from %s\n", pwrdm1->name,
|
||||
pwrdm2->name);
|
||||
return IS_ERR(p);
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
|
||||
|
@ -612,10 +610,10 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
{
|
||||
struct powerdomain *p;
|
||||
|
||||
if (!pwrdm1)
|
||||
if (!cpu_is_omap34xx())
|
||||
return -EINVAL;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
if (!pwrdm1)
|
||||
return -EINVAL;
|
||||
|
||||
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
|
||||
|
@ -623,7 +621,7 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
pr_debug("powerdomain: hardware cannot set/clear sleep "
|
||||
"dependency affecting %s from %s\n", pwrdm1->name,
|
||||
pwrdm2->name);
|
||||
return IS_ERR(p);
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
pr_debug("powerdomain: will no longer prevent %s from sleeping if "
|
||||
|
@ -655,10 +653,10 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
{
|
||||
struct powerdomain *p;
|
||||
|
||||
if (!pwrdm1)
|
||||
if (!cpu_is_omap34xx())
|
||||
return -EINVAL;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
if (!pwrdm1)
|
||||
return -EINVAL;
|
||||
|
||||
p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
|
||||
|
@ -666,7 +664,7 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
|
|||
pr_debug("powerdomain: hardware cannot set/clear sleep "
|
||||
"dependency affecting %s from %s\n", pwrdm1->name,
|
||||
pwrdm2->name);
|
||||
return IS_ERR(p);
|
||||
return PTR_ERR(p);
|
||||
}
|
||||
|
||||
return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
|
||||
|
@ -985,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
|
|||
if (pwrdm->banks < (bank + 1))
|
||||
return -EEXIST;
|
||||
|
||||
if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
|
||||
bank = 1;
|
||||
|
||||
/*
|
||||
* The register bit names below may not correspond to the
|
||||
* actual names of the bits in each powerdomain's register,
|
||||
|
@ -1032,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
|
|||
if (pwrdm->banks < (bank + 1))
|
||||
return -EEXIST;
|
||||
|
||||
if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
|
||||
bank = 1;
|
||||
|
||||
/*
|
||||
* The register bit names below may not correspond to the
|
||||
* actual names of the bits in each powerdomain's register,
|
||||
|
|
|
@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
|
|||
.wkdep_srcs = mpu_34xx_wkdeps,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.flags = PWRDM_HAS_MPU_QUIRK,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
[0] = PWRSTS_OFF_RET,
|
||||
|
|
|
@ -4,10 +4,12 @@
|
|||
/*
|
||||
* OMAP2/3 PRCM base and module definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
* Copyright (C) 2007-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2009 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
* OMAP4 defines in this file are automatically generated from the OMAP hardware
|
||||
* databases.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -49,6 +51,73 @@
|
|||
#define OMAP3430_NEON_MOD 0xb00
|
||||
#define OMAP3430ES2_USBHOST_MOD 0xc00
|
||||
|
||||
#define BITS(n_bit) \
|
||||
(((1 << n_bit) - 1) | (1 << n_bit))
|
||||
|
||||
#define BITFIELD(l_bit, u_bit) \
|
||||
(BITS(u_bit) & ~((BITS(l_bit)) >> 1))
|
||||
|
||||
/* OMAP44XX specific module offsets */
|
||||
|
||||
/* CM1 instances */
|
||||
|
||||
#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000
|
||||
#define OMAP4430_CM1_CKGEN_MOD 0x0100
|
||||
#define OMAP4430_CM1_MPU_MOD 0x0300
|
||||
#define OMAP4430_CM1_TESLA_MOD 0x0400
|
||||
#define OMAP4430_CM1_ABE_MOD 0x0500
|
||||
#define OMAP4430_CM1_RESTORE_MOD 0x0e00
|
||||
#define OMAP4430_CM1_INSTR_MOD 0x0f00
|
||||
|
||||
/* CM2 instances */
|
||||
|
||||
#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000
|
||||
#define OMAP4430_CM2_CKGEN_MOD 0x0100
|
||||
#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600
|
||||
#define OMAP4430_CM2_CORE_MOD 0x0700
|
||||
#define OMAP4430_CM2_IVAHD_MOD 0x0f00
|
||||
#define OMAP4430_CM2_CAM_MOD 0x1000
|
||||
#define OMAP4430_CM2_DSS_MOD 0x1100
|
||||
#define OMAP4430_CM2_GFX_MOD 0x1200
|
||||
#define OMAP4430_CM2_L3INIT_MOD 0x1300
|
||||
#define OMAP4430_CM2_L4PER_MOD 0x1400
|
||||
#define OMAP4430_CM2_CEFUSE_MOD 0x1600
|
||||
#define OMAP4430_CM2_RESTORE_MOD 0x1e00
|
||||
#define OMAP4430_CM2_INSTR_MOD 0x1f00
|
||||
|
||||
/* PRM instances */
|
||||
|
||||
#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000
|
||||
#define OMAP4430_PRM_CKGEN_MOD 0x0100
|
||||
#define OMAP4430_PRM_MPU_MOD 0x0300
|
||||
#define OMAP4430_PRM_TESLA_MOD 0x0400
|
||||
#define OMAP4430_PRM_ABE_MOD 0x0500
|
||||
#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600
|
||||
#define OMAP4430_PRM_CORE_MOD 0x0700
|
||||
#define OMAP4430_PRM_IVAHD_MOD 0x0f00
|
||||
#define OMAP4430_PRM_CAM_MOD 0x1000
|
||||
#define OMAP4430_PRM_DSS_MOD 0x1100
|
||||
#define OMAP4430_PRM_GFX_MOD 0x1200
|
||||
#define OMAP4430_PRM_L3INIT_MOD 0x1300
|
||||
#define OMAP4430_PRM_L4PER_MOD 0x1400
|
||||
#define OMAP4430_PRM_CEFUSE_MOD 0x1600
|
||||
#define OMAP4430_PRM_WKUP_MOD 0x1700
|
||||
#define OMAP4430_PRM_WKUP_CM_MOD 0x1800
|
||||
#define OMAP4430_PRM_EMU_MOD 0x1900
|
||||
#define OMAP4430_PRM_EMU_CM_MOD 0x1a00
|
||||
#define OMAP4430_PRM_DEVICE_MOD 0x1b00
|
||||
#define OMAP4430_PRM_INSTR_MOD 0x1f00
|
||||
|
||||
/* SCRM instances */
|
||||
|
||||
#define OMAP4430_SCRM_SCRM_MOD 0x0000
|
||||
|
||||
/* CHIRONSS instances */
|
||||
|
||||
#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000
|
||||
#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200
|
||||
#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400
|
||||
#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800
|
||||
|
||||
/* 24XX register bits shared between CM & PRM registers */
|
||||
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
|
||||
static void __iomem *prm_base;
|
||||
static void __iomem *cm_base;
|
||||
static void __iomem *cm2_base;
|
||||
|
||||
#define MAX_MODULE_ENABLE_WAIT 100000
|
||||
|
||||
|
@ -170,14 +171,12 @@ u32 prm_read_mod_reg(s16 module, u16 idx)
|
|||
{
|
||||
return __omap_prcm_read(prm_base, module, idx);
|
||||
}
|
||||
EXPORT_SYMBOL(prm_read_mod_reg);
|
||||
|
||||
/* Write into a register in a PRM module */
|
||||
void prm_write_mod_reg(u32 val, s16 module, u16 idx)
|
||||
{
|
||||
__omap_prcm_write(val, prm_base, module, idx);
|
||||
}
|
||||
EXPORT_SYMBOL(prm_write_mod_reg);
|
||||
|
||||
/* Read-modify-write a register in a PRM module. Caller must lock */
|
||||
u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
|
||||
|
@ -191,21 +190,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
|
|||
|
||||
return v;
|
||||
}
|
||||
EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
|
||||
|
||||
/* Read a register in a CM module */
|
||||
u32 cm_read_mod_reg(s16 module, u16 idx)
|
||||
{
|
||||
return __omap_prcm_read(cm_base, module, idx);
|
||||
}
|
||||
EXPORT_SYMBOL(cm_read_mod_reg);
|
||||
|
||||
/* Write into a register in a CM module */
|
||||
void cm_write_mod_reg(u32 val, s16 module, u16 idx)
|
||||
{
|
||||
__omap_prcm_write(val, cm_base, module, idx);
|
||||
}
|
||||
EXPORT_SYMBOL(cm_write_mod_reg);
|
||||
|
||||
/* Read-modify-write a register in a CM module. Caller must lock */
|
||||
u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
|
||||
|
@ -219,7 +215,6 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
|
|||
|
||||
return v;
|
||||
}
|
||||
EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
|
||||
|
||||
/**
|
||||
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
|
||||
|
@ -247,9 +242,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
|
|||
BUG();
|
||||
|
||||
/* Wait for lock */
|
||||
while (((__raw_readl(reg) & mask) != ena) &&
|
||||
(i++ < MAX_MODULE_ENABLE_WAIT))
|
||||
udelay(1);
|
||||
omap_test_timeout(((__raw_readl(reg) & mask) == ena),
|
||||
MAX_MODULE_ENABLE_WAIT, i);
|
||||
|
||||
if (i < MAX_MODULE_ENABLE_WAIT)
|
||||
pr_debug("cm: Module associated with clock %s ready after %d "
|
||||
|
@ -265,6 +259,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
|
|||
{
|
||||
prm_base = omap2_globals->prm;
|
||||
cm_base = omap2_globals->cm;
|
||||
cm2_base = omap2_globals->cm2;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
|
|
2205
arch/arm/mach-omap2/prm-regbits-44xx.h
Normal file
2205
arch/arm/mach-omap2/prm-regbits-44xx.h
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -4,8 +4,8 @@
|
|||
/*
|
||||
* OMAP2/3 Power/Reset Management (PRM) register definitions
|
||||
*
|
||||
* Copyright (C) 2007 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007 Nokia Corporation
|
||||
* Copyright (C) 2007-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*
|
||||
|
@ -22,6 +22,10 @@
|
|||
OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
|
||||
#define OMAP34XX_PRM_REGADDR(module, reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
|
||||
#define OMAP44XX_PRM_REGADDR(module, reg) \
|
||||
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
|
||||
|
||||
#include "prm44xx.h"
|
||||
|
||||
/*
|
||||
* Architecture-specific global PRM registers
|
||||
|
|
411
arch/arm/mach-omap2/prm44xx.h
Normal file
411
arch/arm/mach-omap2/prm44xx.h
Normal file
|
@ -0,0 +1,411 @@
|
|||
/*
|
||||
* OMAP44xx PRM instance offset macros
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley (paul@pwsan.com)
|
||||
* Rajendra Nayak (rnayak@ti.com)
|
||||
* Benoit Cousson (b-cousson@ti.com)
|
||||
*
|
||||
* This file is automatically generated from the OMAP hardware databases.
|
||||
* We respectfully ask that any modifications to this file be coordinated
|
||||
* with the public linux-omap@vger.kernel.org mailing list and the
|
||||
* authors above to ensure that the autogeneration scripts are kept
|
||||
* up-to-date with the file contents.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
|
||||
|
||||
|
||||
/* PRM */
|
||||
|
||||
|
||||
/* PRM.OCP_SOCKET_PRM register offsets */
|
||||
#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
|
||||
#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
|
||||
#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
|
||||
#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
|
||||
#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
|
||||
#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
|
||||
#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
|
||||
#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
|
||||
#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
|
||||
#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
|
||||
|
||||
/* PRM.CKGEN_PRM register offsets */
|
||||
#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
|
||||
#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
|
||||
#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
|
||||
#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
|
||||
#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
|
||||
|
||||
/* PRM.MPU_PRM register offsets */
|
||||
#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
|
||||
#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
|
||||
#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
|
||||
#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
|
||||
|
||||
/* PRM.TESLA_PRM register offsets */
|
||||
#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
|
||||
#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
|
||||
#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
|
||||
#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
|
||||
#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
|
||||
|
||||
/* PRM.ABE_PRM register offsets */
|
||||
#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
|
||||
#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
|
||||
#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
|
||||
#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
|
||||
#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
|
||||
#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
|
||||
#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
|
||||
#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
|
||||
#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
|
||||
#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
|
||||
#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
|
||||
#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
|
||||
#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
|
||||
#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
|
||||
#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
|
||||
#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
|
||||
#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
|
||||
#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
|
||||
#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
|
||||
#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
|
||||
#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
|
||||
#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
|
||||
#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
|
||||
#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
|
||||
#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
|
||||
#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
|
||||
#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
|
||||
|
||||
/* PRM.ALWAYS_ON_PRM register offsets */
|
||||
#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
|
||||
#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
|
||||
#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
|
||||
#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
|
||||
#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
|
||||
#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
|
||||
#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
|
||||
|
||||
/* PRM.CORE_PRM register offsets */
|
||||
#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
|
||||
#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
|
||||
#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
|
||||
#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
|
||||
#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
|
||||
#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
|
||||
#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
|
||||
#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
|
||||
#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
|
||||
#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
|
||||
#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
|
||||
#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
|
||||
#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
|
||||
#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
|
||||
#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
|
||||
#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
|
||||
#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
|
||||
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
|
||||
#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
|
||||
#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
|
||||
#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
|
||||
#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
|
||||
#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
|
||||
#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
|
||||
#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
|
||||
#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
|
||||
#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
|
||||
#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
|
||||
|
||||
/* PRM.IVAHD_PRM register offsets */
|
||||
#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
|
||||
#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
|
||||
#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
|
||||
#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
|
||||
#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
|
||||
#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
|
||||
|
||||
/* PRM.CAM_PRM register offsets */
|
||||
#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
|
||||
#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
|
||||
#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
|
||||
#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
|
||||
|
||||
/* PRM.DSS_PRM register offsets */
|
||||
#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
|
||||
#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
|
||||
#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
|
||||
#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
|
||||
#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
|
||||
|
||||
/* PRM.GFX_PRM register offsets */
|
||||
#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
|
||||
#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
|
||||
#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
|
||||
|
||||
/* PRM.L3INIT_PRM register offsets */
|
||||
#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
|
||||
#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
|
||||
#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
|
||||
#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
|
||||
#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
|
||||
#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
|
||||
#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
|
||||
#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
|
||||
#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
|
||||
#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
|
||||
#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
|
||||
#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
|
||||
#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
|
||||
#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
|
||||
#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
|
||||
#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
|
||||
#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
|
||||
#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
|
||||
#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
|
||||
#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
|
||||
#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
|
||||
#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
|
||||
#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
|
||||
#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
|
||||
#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
|
||||
#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
|
||||
#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
|
||||
#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
|
||||
#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
|
||||
#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
|
||||
#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
|
||||
|
||||
/* PRM.L4PER_PRM register offsets */
|
||||
#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
|
||||
#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
|
||||
#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
|
||||
#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
|
||||
#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
|
||||
#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
|
||||
#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
|
||||
#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
|
||||
#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
|
||||
#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
|
||||
#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
|
||||
#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
|
||||
#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
|
||||
#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
|
||||
#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
|
||||
#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
|
||||
#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
|
||||
#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
|
||||
#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
|
||||
#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
|
||||
#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
|
||||
#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
|
||||
#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
|
||||
#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
|
||||
#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
|
||||
#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
|
||||
#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
|
||||
#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
|
||||
#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
|
||||
#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
|
||||
#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
|
||||
#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
|
||||
#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
|
||||
#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
|
||||
#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
|
||||
#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
|
||||
#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
|
||||
#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
|
||||
#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
|
||||
#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
|
||||
#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
|
||||
#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
|
||||
#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
|
||||
#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
|
||||
#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
|
||||
#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
|
||||
#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
|
||||
#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
|
||||
#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
|
||||
#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
|
||||
#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
|
||||
#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
|
||||
#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
|
||||
#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
|
||||
#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
|
||||
#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
|
||||
#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
|
||||
#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
|
||||
#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
|
||||
#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
|
||||
#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
|
||||
#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
|
||||
#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
|
||||
#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
|
||||
#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
|
||||
#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
|
||||
#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
|
||||
#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
|
||||
#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
|
||||
#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
|
||||
#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
|
||||
#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
|
||||
#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
|
||||
#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
|
||||
#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
|
||||
#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
|
||||
#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
|
||||
#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
|
||||
#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
|
||||
#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
|
||||
#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
|
||||
|
||||
/* PRM.CEFUSE_PRM register offsets */
|
||||
#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
|
||||
#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
|
||||
#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
|
||||
|
||||
/* PRM.WKUP_PRM register offsets */
|
||||
#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
|
||||
#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
|
||||
#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
|
||||
#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
|
||||
#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
|
||||
#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
|
||||
#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
|
||||
#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
|
||||
#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
|
||||
#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
|
||||
#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
|
||||
#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
|
||||
#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
|
||||
#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
|
||||
#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
|
||||
#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
|
||||
#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
|
||||
#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
|
||||
|
||||
/* PRM.WKUP_CM register offsets */
|
||||
#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
|
||||
#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
|
||||
#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
|
||||
#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
|
||||
#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
|
||||
#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
|
||||
#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
|
||||
#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
|
||||
#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
|
||||
#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
|
||||
#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
|
||||
#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
|
||||
#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
|
||||
|
||||
/* PRM.EMU_PRM register offsets */
|
||||
#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
|
||||
#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
|
||||
#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
|
||||
|
||||
/* PRM.EMU_CM register offsets */
|
||||
#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
|
||||
#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
|
||||
#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
|
||||
|
||||
/* PRM.DEVICE_PRM register offsets */
|
||||
#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
|
||||
#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
|
||||
#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
|
||||
#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
|
||||
#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
|
||||
#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
|
||||
#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
|
||||
#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
|
||||
#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
|
||||
#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
|
||||
#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
|
||||
#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
|
||||
#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
|
||||
#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
|
||||
#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
|
||||
#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
|
||||
#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
|
||||
#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
|
||||
#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
|
||||
#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
|
||||
#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
|
||||
#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
|
||||
#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
|
||||
#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
|
||||
#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
|
||||
#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
|
||||
#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
|
||||
#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
|
||||
#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
|
||||
#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
|
||||
#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
|
||||
#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
|
||||
#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
|
||||
#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
|
||||
#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
|
||||
#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
|
||||
#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
|
||||
#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
|
||||
#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
|
||||
#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
|
||||
#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
|
||||
#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
|
||||
#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
|
||||
#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
|
||||
#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
|
||||
#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
|
||||
#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
|
||||
#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
|
||||
#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
|
||||
#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
|
||||
#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
|
||||
#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
|
||||
#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
|
||||
#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
|
||||
#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
|
||||
#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
|
||||
#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
|
||||
#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
|
||||
#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
|
||||
#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
|
||||
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
|
||||
#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
|
||||
|
||||
/* CHIRON_PRCM */
|
||||
|
||||
|
||||
/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
|
||||
#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
|
||||
|
||||
/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
|
||||
#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
|
||||
|
||||
/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
|
||||
#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
|
||||
#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
|
||||
#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
|
||||
#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
|
||||
#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
|
||||
#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
|
||||
#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
|
||||
|
||||
/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
|
||||
#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
|
||||
#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
|
||||
#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
|
||||
#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
|
||||
#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
|
||||
#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
|
||||
#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
|
||||
#endif
|
|
@ -18,6 +18,9 @@
|
|||
#include <plat/sdrc.h>
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
extern void __iomem *omap2_sdrc_base;
|
||||
extern void __iomem *omap2_sms_base;
|
||||
|
||||
|
@ -56,4 +59,20 @@ static inline u32 sms_read_reg(u16 reg)
|
|||
OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
/* Minimum frequency that the SDRC DLL can lock at */
|
||||
#define MIN_SDRC_DLL_LOCK_FREQ 83000000
|
||||
|
||||
/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
|
||||
#define SDRC_MPURATE_SCALE 8
|
||||
|
||||
/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
|
||||
#define SDRC_MPURATE_BASE_SHIFT 9
|
||||
|
||||
/*
|
||||
* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
|
||||
* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
|
||||
*/
|
||||
#define SDRC_MPURATE_LOOPS 96
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include "pm.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
|
||||
#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
|
||||
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
|
||||
|
||||
#define DEFAULT_TIMEOUT (5 * HZ)
|
||||
|
@ -572,6 +573,23 @@ static struct omap_uart_state omap_uart[] = {
|
|||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Override the default 8250 read handler: mem_serial_in()
|
||||
* Empty RX fifo read causes an abort on omap3630 and omap4
|
||||
* This function makes sure that an empty rx fifo is not read on these silicons
|
||||
* (OMAP1/2/3430 are not affected)
|
||||
*/
|
||||
static unsigned int serial_in_override(struct uart_port *up, int offset)
|
||||
{
|
||||
if (UART_RX == offset) {
|
||||
unsigned int lsr;
|
||||
lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
|
||||
if (!(lsr & UART_LSR_DR))
|
||||
return -EPERM;
|
||||
}
|
||||
return serial_read_reg(omap_uart[up->line].p, offset);
|
||||
}
|
||||
|
||||
void __init omap_serial_early_init(void)
|
||||
{
|
||||
int i;
|
||||
|
@ -631,24 +649,64 @@ void __init omap_serial_early_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_serial_init_port() - initialize single serial port
|
||||
* @port: serial port number (0-3)
|
||||
*
|
||||
* This function initialies serial driver for given @port only.
|
||||
* Platforms can call this function instead of omap_serial_init()
|
||||
* if they don't plan to use all available UARTs as serial ports.
|
||||
*
|
||||
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
|
||||
* use only one of the two.
|
||||
*/
|
||||
void __init omap_serial_init_port(int port)
|
||||
{
|
||||
struct omap_uart_state *uart;
|
||||
struct platform_device *pdev;
|
||||
struct device *dev;
|
||||
|
||||
BUG_ON(port < 0);
|
||||
BUG_ON(port >= ARRAY_SIZE(omap_uart));
|
||||
|
||||
uart = &omap_uart[port];
|
||||
pdev = &uart->pdev;
|
||||
dev = &pdev->dev;
|
||||
|
||||
omap_uart_reset(uart);
|
||||
omap_uart_idle_init(uart);
|
||||
|
||||
if (WARN_ON(platform_device_register(pdev)))
|
||||
return;
|
||||
|
||||
if ((cpu_is_omap34xx() && uart->padconf) ||
|
||||
(uart->wk_en && uart->wk_mask)) {
|
||||
device_init_wakeup(dev, true);
|
||||
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
|
||||
}
|
||||
|
||||
/* omap44xx: Never read empty UART fifo
|
||||
* omap3xxx: Never read empty UART fifo on UARTs
|
||||
* with IP rev >=0x52
|
||||
*/
|
||||
if (cpu_is_omap44xx())
|
||||
uart->p->serial_in = serial_in_override;
|
||||
else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
|
||||
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
|
||||
uart->p->serial_in = serial_in_override;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_serial_init() - intialize all supported serial ports
|
||||
*
|
||||
* Initializes all available UARTs as serial ports. Platforms
|
||||
* can call this function when they want to have default behaviour
|
||||
* for serial ports (e.g initialize them all as serial ports).
|
||||
*/
|
||||
void __init omap_serial_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
|
||||
struct omap_uart_state *uart = &omap_uart[i];
|
||||
struct platform_device *pdev = &uart->pdev;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
omap_uart_reset(uart);
|
||||
omap_uart_idle_init(uart);
|
||||
|
||||
if (WARN_ON(platform_device_register(pdev)))
|
||||
continue;
|
||||
if ((cpu_is_omap34xx() && uart->padconf) ||
|
||||
(uart->wk_en && uart->wk_mask)) {
|
||||
device_init_wakeup(dev, true);
|
||||
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
|
||||
}
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
|
||||
omap_serial_init_port(i);
|
||||
}
|
||||
|
|
|
@ -91,8 +91,19 @@
|
|||
* new SDRC_ACTIM_CTRL_B_1 register contents
|
||||
* new SDRC_MR_1 register value
|
||||
*
|
||||
* If the param SDRC_RFR_CTRL_1 is 0, the parameters
|
||||
* are not programmed into the SDRC CS1 registers
|
||||
* If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
|
||||
* the SDRC CS1 registers
|
||||
*
|
||||
* NOTE: This code no longer attempts to program the SDRC AC timing and MR
|
||||
* registers. This is because the code currently cannot ensure that all
|
||||
* L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
|
||||
* SDRAM when the registers are written. If the registers are changed while
|
||||
* an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
|
||||
* may enter an unpredictable state. In the future, the intent is to
|
||||
* re-enable this code in cases where we can ensure that no initiators are
|
||||
* touching the SDRAM. Until that time, users who know that their use case
|
||||
* can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
|
||||
* option.
|
||||
*/
|
||||
ENTRY(omap3_sram_configure_core_dpll)
|
||||
stmfd sp!, {r1-r12, lr} @ store regs to stack
|
||||
|
@ -219,6 +230,7 @@ configure_sdrc:
|
|||
ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
|
||||
str r12, [r11] @ store
|
||||
#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_0
|
||||
str r12, [r11]
|
||||
|
@ -228,11 +240,13 @@ configure_sdrc:
|
|||
ldr r12, omap_sdrc_mr_0_val
|
||||
ldr r11, omap3_sdrc_mr_0
|
||||
str r12, [r11]
|
||||
#endif
|
||||
ldr r12, omap_sdrc_rfr_ctrl_1_val
|
||||
cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
|
||||
beq skip_cs1_prog @ do not program cs1 params
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_1
|
||||
str r12, [r11]
|
||||
#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_1
|
||||
str r12, [r11]
|
||||
|
@ -242,6 +256,7 @@ configure_sdrc:
|
|||
ldr r12, omap_sdrc_mr_1_val
|
||||
ldr r11, omap3_sdrc_mr_1
|
||||
str r12, [r11]
|
||||
#endif
|
||||
skip_cs1_prog:
|
||||
ldr r12, [r11] @ posted-write barrier for SDRC
|
||||
bx lr
|
||||
|
|
|
@ -27,6 +27,8 @@
|
|||
#include <mach/irqs.h>
|
||||
#include <plat/usb.h>
|
||||
|
||||
#include "mux.h"
|
||||
|
||||
#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
|
||||
|
||||
static struct resource ehci_resources[] = {
|
||||
|
@ -72,32 +74,44 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
|
|||
{
|
||||
switch (port_mode[0]) {
|
||||
case EHCI_HCD_OMAP_MODE_PHY:
|
||||
omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
|
||||
omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
|
||||
omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
|
||||
omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
|
||||
omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
|
||||
omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
|
||||
omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
|
||||
omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
|
||||
omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
|
||||
omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
|
||||
omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
|
||||
omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
|
||||
omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
|
||||
break;
|
||||
case EHCI_HCD_OMAP_MODE_TLL:
|
||||
omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
|
||||
omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
|
||||
omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
|
||||
omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
|
||||
omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
|
||||
omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
|
||||
omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
|
||||
omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
|
||||
omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
|
||||
omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
|
||||
omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
|
||||
omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
|
||||
omap_mux_init_signal("hsusb1_tll_stp",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("hsusb1_tll_clk",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_dir",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_nxt",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data0",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data1",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data2",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data3",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data4",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data5",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data6",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb1_tll_data7",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
break;
|
||||
case EHCI_HCD_OMAP_MODE_UNKNOWN:
|
||||
/* FALLTHROUGH */
|
||||
|
@ -107,32 +121,52 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
|
|||
|
||||
switch (port_mode[1]) {
|
||||
case EHCI_HCD_OMAP_MODE_PHY:
|
||||
omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
|
||||
omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
|
||||
omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
|
||||
omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
|
||||
omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
|
||||
omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
|
||||
omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
|
||||
omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
|
||||
omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
|
||||
omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
|
||||
omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
|
||||
omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
|
||||
omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
|
||||
omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data0",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data1",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data2",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data3",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data4",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data5",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data6",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_data7",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
break;
|
||||
case EHCI_HCD_OMAP_MODE_TLL:
|
||||
omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
|
||||
omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
|
||||
omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
|
||||
omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
|
||||
omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
|
||||
omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
|
||||
omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
|
||||
omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
|
||||
omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
|
||||
omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
|
||||
omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
|
||||
omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
|
||||
omap_mux_init_signal("hsusb2_tll_stp",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("hsusb2_tll_clk",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_dir",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_nxt",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data0",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data1",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data2",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data3",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data4",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data5",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data6",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb2_tll_data7",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
break;
|
||||
case EHCI_HCD_OMAP_MODE_UNKNOWN:
|
||||
/* FALLTHROUGH */
|
||||
|
@ -145,18 +179,30 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
|
|||
printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
|
||||
break;
|
||||
case EHCI_HCD_OMAP_MODE_TLL:
|
||||
omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
|
||||
omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
|
||||
omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
|
||||
omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
|
||||
omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
|
||||
omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
|
||||
omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
|
||||
omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
|
||||
omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
|
||||
omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
|
||||
omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
|
||||
omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
|
||||
omap_mux_init_signal("hsusb3_tll_stp",
|
||||
OMAP_PIN_INPUT_PULLUP);
|
||||
omap_mux_init_signal("hsusb3_tll_clk",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_dir",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_nxt",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data0",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data1",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data2",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data3",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data4",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data5",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data6",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
omap_mux_init_signal("hsusb3_tll_data7",
|
||||
OMAP_PIN_INPUT_PULLDOWN);
|
||||
break;
|
||||
case EHCI_HCD_OMAP_MODE_UNKNOWN:
|
||||
/* FALLTHROUGH */
|
||||
|
|
|
@ -27,6 +27,7 @@ config ARCH_OMAP4
|
|||
bool "TI OMAP4"
|
||||
select CPU_V7
|
||||
select ARM_GIC
|
||||
select COMMON_CLKDEV
|
||||
|
||||
endchoice
|
||||
|
||||
|
@ -42,28 +43,6 @@ config OMAP_DEBUG_LEDS
|
|||
depends on OMAP_DEBUG_DEVICES
|
||||
default y if LEDS || LEDS_OMAP_DEBUG
|
||||
|
||||
config OMAP_DEBUG_POWERDOMAIN
|
||||
bool "Emit debug messages from powerdomain layer"
|
||||
depends on ARCH_OMAP2 || ARCH_OMAP3
|
||||
help
|
||||
Say Y here if you want to compile in powerdomain layer
|
||||
debugging messages for OMAP2/3. These messages can
|
||||
provide more detail as to why some powerdomain calls
|
||||
may be failing, and will also emit a descriptive message
|
||||
for every powerdomain register write. However, the
|
||||
extra detail costs some memory.
|
||||
|
||||
config OMAP_DEBUG_CLOCKDOMAIN
|
||||
bool "Emit debug messages from clockdomain layer"
|
||||
depends on ARCH_OMAP2 || ARCH_OMAP3
|
||||
help
|
||||
Say Y here if you want to compile in clockdomain layer
|
||||
debugging messages for OMAP2/3. These messages can
|
||||
provide more detail as to why some clockdomain calls
|
||||
may be failing, and will also emit a descriptive message
|
||||
for every clockdomain register write. However, the
|
||||
extra detail costs some memory.
|
||||
|
||||
config OMAP_RESET_CLOCKS
|
||||
bool "Reset unused clocks during boot"
|
||||
depends on ARCH_OMAP
|
||||
|
@ -78,28 +57,28 @@ config OMAP_RESET_CLOCKS
|
|||
|
||||
config OMAP_MUX
|
||||
bool "OMAP multiplexing support"
|
||||
depends on ARCH_OMAP
|
||||
depends on ARCH_OMAP
|
||||
default y
|
||||
help
|
||||
Pin multiplexing support for OMAP boards. If your bootloader
|
||||
sets the multiplexing correctly, say N. Otherwise, or if unsure,
|
||||
say Y.
|
||||
help
|
||||
Pin multiplexing support for OMAP boards. If your bootloader
|
||||
sets the multiplexing correctly, say N. Otherwise, or if unsure,
|
||||
say Y.
|
||||
|
||||
config OMAP_MUX_DEBUG
|
||||
bool "Multiplexing debug output"
|
||||
depends on OMAP_MUX
|
||||
help
|
||||
Makes the multiplexing functions print out a lot of debug info.
|
||||
This is useful if you want to find out the correct values of the
|
||||
multiplexing registers.
|
||||
depends on OMAP_MUX
|
||||
help
|
||||
Makes the multiplexing functions print out a lot of debug info.
|
||||
This is useful if you want to find out the correct values of the
|
||||
multiplexing registers.
|
||||
|
||||
config OMAP_MUX_WARNINGS
|
||||
bool "Warn about pins the bootloader didn't set up"
|
||||
depends on OMAP_MUX
|
||||
default y
|
||||
help
|
||||
depends on OMAP_MUX
|
||||
default y
|
||||
help
|
||||
Choose Y here to warn whenever driver initialization logic needs
|
||||
to change the pin multiplexing setup. When there are no warnings
|
||||
to change the pin multiplexing setup. When there are no warnings
|
||||
printed, it's safe to deselect OMAP_MUX for your product.
|
||||
|
||||
config OMAP_MCBSP
|
||||
|
@ -125,7 +104,7 @@ config OMAP_IOMMU_DEBUG
|
|||
tristate
|
||||
|
||||
choice
|
||||
prompt "System timer"
|
||||
prompt "System timer"
|
||||
default OMAP_MPU_TIMER
|
||||
|
||||
config OMAP_MPU_TIMER
|
||||
|
@ -148,11 +127,11 @@ config OMAP_32K_TIMER
|
|||
endchoice
|
||||
|
||||
config OMAP_32K_TIMER_HZ
|
||||
int "Kernel internal timer frequency for 32KHz timer"
|
||||
range 32 1024
|
||||
depends on OMAP_32K_TIMER
|
||||
default "128"
|
||||
help
|
||||
int "Kernel internal timer frequency for 32KHz timer"
|
||||
range 32 1024
|
||||
depends on OMAP_32K_TIMER
|
||||
default "128"
|
||||
help
|
||||
Kernel internal timer frequency should be a divisor of 32768,
|
||||
such as 64 or 128.
|
||||
|
||||
|
|
|
@ -40,36 +40,10 @@ static struct clk_functions *arch_clock;
|
|||
* clock framework is not up , it is defined here to avoid rework in
|
||||
* every driver. Also dummy prcm reset function is added */
|
||||
|
||||
/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */
|
||||
#if defined(CONFIG_ARCH_OMAP4)
|
||||
struct clk *clk_get(struct device *dev, const char *id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get);
|
||||
|
||||
void clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_put);
|
||||
|
||||
void omap2_clk_prepare_for_reboot(void)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(omap2_clk_prepare_for_reboot);
|
||||
|
||||
void omap_prcm_arch_reset(char mode)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(omap_prcm_arch_reset);
|
||||
#endif
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
if (cpu_is_omap44xx())
|
||||
/* OMAP4 clk framework not supported yet */
|
||||
return 0;
|
||||
|
||||
if (clk == NULL || IS_ERR(clk))
|
||||
return -EINVAL;
|
||||
|
|
|
@ -280,16 +280,18 @@ void __init omap2_set_globals_343x(void)
|
|||
#if defined(CONFIG_ARCH_OMAP4)
|
||||
static struct omap_globals omap4_globals = {
|
||||
.class = OMAP443X_CLASS,
|
||||
.tap = OMAP2_L4_IO_ADDRESS(0x4830a000),
|
||||
.tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
|
||||
.ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
|
||||
.prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
|
||||
.cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
|
||||
.cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
|
||||
};
|
||||
|
||||
void __init omap2_set_globals_443x(void)
|
||||
{
|
||||
omap2_set_globals_tap(&omap4_globals);
|
||||
omap2_set_globals_control(&omap4_globals);
|
||||
omap2_set_globals_prcm(&omap4_globals);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
|
@ -24,6 +25,12 @@
|
|||
* platforms include H2, H3, H4, and Perseus2.
|
||||
*/
|
||||
|
||||
static struct smc91x_platdata smc91x_info = {
|
||||
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
|
||||
.leda = RPC_LED_100_10,
|
||||
.ledb = RPC_LED_TX_RX,
|
||||
};
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = {
|
|||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &smc91x_info,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
|
|
@ -242,6 +242,39 @@ int __init omap_mmc_add(const char *name, int id, unsigned long base,
|
|||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
#define OMAP_RNG_BASE 0x480A0000
|
||||
#else
|
||||
#define OMAP_RNG_BASE 0xfffe5000
|
||||
#endif
|
||||
|
||||
static struct resource rng_resources[] = {
|
||||
{
|
||||
.start = OMAP_RNG_BASE,
|
||||
.end = OMAP_RNG_BASE + 0x4f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap_rng_device = {
|
||||
.name = "omap_rng",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rng_resources),
|
||||
.resource = rng_resources,
|
||||
};
|
||||
|
||||
static void omap_init_rng(void)
|
||||
{
|
||||
(void) platform_device_register(&omap_rng_device);
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_rng(void) {}
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
/* Numbering for the SPI-capable controllers when used for SPI:
|
||||
* spi = 1
|
||||
* uwire = 2
|
||||
|
@ -324,39 +357,6 @@ static void omap_init_wdt(void)
|
|||
static inline void omap_init_wdt(void) {}
|
||||
#endif
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
#define OMAP_RNG_BASE 0x480A0000
|
||||
#else
|
||||
#define OMAP_RNG_BASE 0xfffe5000
|
||||
#endif
|
||||
|
||||
static struct resource rng_resources[] = {
|
||||
{
|
||||
.start = OMAP_RNG_BASE,
|
||||
.end = OMAP_RNG_BASE + 0x4f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device omap_rng_device = {
|
||||
.name = "omap_rng",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rng_resources),
|
||||
.resource = rng_resources,
|
||||
};
|
||||
|
||||
static void omap_init_rng(void)
|
||||
{
|
||||
(void) platform_device_register(&omap_rng_device);
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_rng(void) {}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This gets called after board-specific INIT_MACHINE, and initializes most
|
||||
* on-chip peripherals accessible on this board (except for few like USB):
|
||||
|
@ -384,9 +384,9 @@ static int __init omap_init_devices(void)
|
|||
*/
|
||||
omap_init_dsp();
|
||||
omap_init_kp();
|
||||
omap_init_rng();
|
||||
omap_init_uwire();
|
||||
omap_init_wdt();
|
||||
omap_init_rng();
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap_init_devices);
|
||||
|
|
|
@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
|
|||
#endif
|
||||
|
||||
#define OMAP_DMA_ACTIVE 0x01
|
||||
#define OMAP_DMA_CCR_EN (1 << 7)
|
||||
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
|
||||
|
||||
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
|
||||
|
@ -1120,17 +1119,8 @@ int omap_dma_running(void)
|
|||
{
|
||||
int lch;
|
||||
|
||||
/*
|
||||
* On OMAP1510, internal LCD controller will start the transfer
|
||||
* when it gets enabled, so assume DMA running if LCD enabled.
|
||||
*/
|
||||
if (cpu_is_omap1510())
|
||||
if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
|
||||
return 1;
|
||||
|
||||
/* Check if LCD DMA is running */
|
||||
if (cpu_is_omap16xx())
|
||||
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
|
||||
if (cpu_class_is_omap1())
|
||||
if (omap_lcd_dma_running())
|
||||
return 1;
|
||||
|
||||
for (lch = 0; lch < dma_chan_count; lch++)
|
||||
|
@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
|
|||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
static struct lcd_dma_info {
|
||||
spinlock_t lock;
|
||||
int reserved;
|
||||
void (*callback)(u16 status, void *data);
|
||||
void *cb_data;
|
||||
|
||||
int active;
|
||||
unsigned long addr, size;
|
||||
int rotate, data_type, xres, yres;
|
||||
int vxres;
|
||||
int mirror;
|
||||
int xscale, yscale;
|
||||
int ext_ctrl;
|
||||
int src_port;
|
||||
int single_transfer;
|
||||
} lcd_dma;
|
||||
|
||||
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
|
||||
int data_type)
|
||||
{
|
||||
lcd_dma.addr = addr;
|
||||
lcd_dma.data_type = data_type;
|
||||
lcd_dma.xres = fb_xres;
|
||||
lcd_dma.yres = fb_yres;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
|
||||
|
||||
void omap_set_lcd_dma_src_port(int port)
|
||||
{
|
||||
lcd_dma.src_port = port;
|
||||
}
|
||||
|
||||
void omap_set_lcd_dma_ext_controller(int external)
|
||||
{
|
||||
lcd_dma.ext_ctrl = external;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
|
||||
|
||||
void omap_set_lcd_dma_single_transfer(int single)
|
||||
{
|
||||
lcd_dma.single_transfer = single;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
|
||||
|
||||
void omap_set_lcd_dma_b1_rotation(int rotate)
|
||||
{
|
||||
if (omap_dma_in_1510_mode()) {
|
||||
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
lcd_dma.rotate = rotate;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
|
||||
|
||||
void omap_set_lcd_dma_b1_mirror(int mirror)
|
||||
{
|
||||
if (omap_dma_in_1510_mode()) {
|
||||
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
|
||||
BUG();
|
||||
}
|
||||
lcd_dma.mirror = mirror;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
|
||||
|
||||
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
|
||||
{
|
||||
if (omap_dma_in_1510_mode()) {
|
||||
printk(KERN_ERR "DMA virtual resulotion is not supported "
|
||||
"in 1510 mode\n");
|
||||
BUG();
|
||||
}
|
||||
lcd_dma.vxres = vxres;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
|
||||
|
||||
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
|
||||
{
|
||||
if (omap_dma_in_1510_mode()) {
|
||||
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
|
||||
BUG();
|
||||
}
|
||||
lcd_dma.xscale = xscale;
|
||||
lcd_dma.yscale = yscale;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
|
||||
|
||||
static void set_b1_regs(void)
|
||||
{
|
||||
unsigned long top, bottom;
|
||||
int es;
|
||||
u16 w;
|
||||
unsigned long en, fn;
|
||||
long ei, fi;
|
||||
unsigned long vxres;
|
||||
unsigned int xscale, yscale;
|
||||
|
||||
switch (lcd_dma.data_type) {
|
||||
case OMAP_DMA_DATA_TYPE_S8:
|
||||
es = 1;
|
||||
break;
|
||||
case OMAP_DMA_DATA_TYPE_S16:
|
||||
es = 2;
|
||||
break;
|
||||
case OMAP_DMA_DATA_TYPE_S32:
|
||||
es = 4;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
|
||||
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
|
||||
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
|
||||
BUG_ON(vxres < lcd_dma.xres);
|
||||
|
||||
#define PIXADDR(x, y) (lcd_dma.addr + \
|
||||
((y) * vxres * yscale + (x) * xscale) * es)
|
||||
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
|
||||
|
||||
switch (lcd_dma.rotate) {
|
||||
case 0:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(0, 0);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
/* 1510 DMA requires the bottom address to be 2 more
|
||||
* than the actual last memory access location. */
|
||||
if (omap_dma_in_1510_mode() &&
|
||||
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
|
||||
bottom += 2;
|
||||
ei = PIXSTEP(0, 0, 1, 0);
|
||||
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
|
||||
} else {
|
||||
top = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
bottom = PIXADDR(0, lcd_dma.yres - 1);
|
||||
ei = PIXSTEP(1, 0, 0, 0);
|
||||
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
|
||||
}
|
||||
en = lcd_dma.xres;
|
||||
fn = lcd_dma.yres;
|
||||
break;
|
||||
case 90:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(0, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
ei = PIXSTEP(0, 1, 0, 0);
|
||||
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
|
||||
} else {
|
||||
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(0, 0);
|
||||
ei = PIXSTEP(0, 1, 0, 0);
|
||||
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
|
||||
}
|
||||
en = lcd_dma.yres;
|
||||
fn = lcd_dma.xres;
|
||||
break;
|
||||
case 180:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(0, 0);
|
||||
ei = PIXSTEP(1, 0, 0, 0);
|
||||
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
|
||||
} else {
|
||||
top = PIXADDR(0, lcd_dma.yres - 1);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
ei = PIXSTEP(0, 0, 1, 0);
|
||||
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
|
||||
}
|
||||
en = lcd_dma.xres;
|
||||
fn = lcd_dma.yres;
|
||||
break;
|
||||
case 270:
|
||||
if (!lcd_dma.mirror) {
|
||||
top = PIXADDR(lcd_dma.xres - 1, 0);
|
||||
bottom = PIXADDR(0, lcd_dma.yres - 1);
|
||||
ei = PIXSTEP(0, 0, 0, 1);
|
||||
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
|
||||
} else {
|
||||
top = PIXADDR(0, 0);
|
||||
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
|
||||
ei = PIXSTEP(0, 0, 0, 1);
|
||||
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
|
||||
}
|
||||
en = lcd_dma.yres;
|
||||
fn = lcd_dma.xres;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return; /* Suppress warning about uninitialized vars */
|
||||
}
|
||||
|
||||
if (omap_dma_in_1510_mode()) {
|
||||
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
|
||||
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
|
||||
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
|
||||
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/* 1610 regs */
|
||||
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
|
||||
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
|
||||
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
|
||||
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
|
||||
|
||||
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
|
||||
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
|
||||
w &= ~0x03;
|
||||
w |= lcd_dma.data_type;
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
/* Always set the source port as SDRAM for now*/
|
||||
w &= ~(0x03 << 6);
|
||||
if (lcd_dma.callback != NULL)
|
||||
w |= 1 << 1; /* Block interrupt enable */
|
||||
else
|
||||
w &= ~(1 << 1);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
|
||||
if (!(lcd_dma.rotate || lcd_dma.mirror ||
|
||||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
|
||||
return;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
/* Set the double-indexed addressing mode */
|
||||
w |= (0x03 << 12);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
|
||||
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
|
||||
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
|
||||
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
|
||||
}
|
||||
|
||||
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
u16 w;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
if (unlikely(!(w & (1 << 3)))) {
|
||||
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
|
||||
return IRQ_NONE;
|
||||
}
|
||||
/* Ack the IRQ */
|
||||
w |= (1 << 3);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
lcd_dma.active = 0;
|
||||
if (lcd_dma.callback != NULL)
|
||||
lcd_dma.callback(w, lcd_dma.cb_data);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
|
||||
void *data)
|
||||
{
|
||||
spin_lock_irq(&lcd_dma.lock);
|
||||
if (lcd_dma.reserved) {
|
||||
spin_unlock_irq(&lcd_dma.lock);
|
||||
printk(KERN_ERR "LCD DMA channel already reserved\n");
|
||||
BUG();
|
||||
return -EBUSY;
|
||||
}
|
||||
lcd_dma.reserved = 1;
|
||||
spin_unlock_irq(&lcd_dma.lock);
|
||||
lcd_dma.callback = callback;
|
||||
lcd_dma.cb_data = data;
|
||||
lcd_dma.active = 0;
|
||||
lcd_dma.single_transfer = 0;
|
||||
lcd_dma.rotate = 0;
|
||||
lcd_dma.vxres = 0;
|
||||
lcd_dma.mirror = 0;
|
||||
lcd_dma.xscale = 0;
|
||||
lcd_dma.yscale = 0;
|
||||
lcd_dma.ext_ctrl = 0;
|
||||
lcd_dma.src_port = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_request_lcd_dma);
|
||||
|
||||
void omap_free_lcd_dma(void)
|
||||
{
|
||||
spin_lock(&lcd_dma.lock);
|
||||
if (!lcd_dma.reserved) {
|
||||
spin_unlock(&lcd_dma.lock);
|
||||
printk(KERN_ERR "LCD DMA is not reserved\n");
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
if (!enable_1510_mode)
|
||||
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
|
||||
OMAP1610_DMA_LCD_CCR);
|
||||
lcd_dma.reserved = 0;
|
||||
spin_unlock(&lcd_dma.lock);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_free_lcd_dma);
|
||||
|
||||
void omap_enable_lcd_dma(void)
|
||||
{
|
||||
u16 w;
|
||||
|
||||
/*
|
||||
* Set the Enable bit only if an external controller is
|
||||
* connected. Otherwise the OMAP internal controller will
|
||||
* start the transfer when it gets enabled.
|
||||
*/
|
||||
if (enable_1510_mode || !lcd_dma.ext_ctrl)
|
||||
return;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
w |= 1 << 8;
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
|
||||
lcd_dma.active = 1;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
w |= 1 << 7;
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_enable_lcd_dma);
|
||||
|
||||
void omap_setup_lcd_dma(void)
|
||||
{
|
||||
BUG_ON(lcd_dma.active);
|
||||
if (!enable_1510_mode) {
|
||||
/* Set some reasonable defaults */
|
||||
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
|
||||
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
|
||||
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
|
||||
}
|
||||
set_b1_regs();
|
||||
if (!enable_1510_mode) {
|
||||
u16 w;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
/*
|
||||
* If DMA was already active set the end_prog bit to have
|
||||
* the programmed register set loaded into the active
|
||||
* register set.
|
||||
*/
|
||||
w |= 1 << 11; /* End_prog */
|
||||
if (!lcd_dma.single_transfer)
|
||||
w |= (3 << 8); /* Auto_init, repeat */
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(omap_setup_lcd_dma);
|
||||
|
||||
void omap_stop_lcd_dma(void)
|
||||
{
|
||||
u16 w;
|
||||
|
||||
lcd_dma.active = 0;
|
||||
if (enable_1510_mode || !lcd_dma.ext_ctrl)
|
||||
return;
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CCR);
|
||||
w &= ~(1 << 7);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CCR);
|
||||
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
w &= ~(1 << 8);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
}
|
||||
EXPORT_SYMBOL(omap_stop_lcd_dma);
|
||||
|
||||
void omap_dma_global_context_save(void)
|
||||
{
|
||||
omap_dma_global_context.dma_irqenable_l0 =
|
||||
|
@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
|
|||
dma_chan_count = 16;
|
||||
} else
|
||||
dma_chan_count = 9;
|
||||
if (cpu_is_omap16xx()) {
|
||||
u16 w;
|
||||
|
||||
/* this would prevent OMAP sleep */
|
||||
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
|
||||
w &= ~(1 << 8);
|
||||
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
|
||||
}
|
||||
} else if (cpu_class_is_omap2()) {
|
||||
u8 revision = dma_read(REVISION) & 0xff;
|
||||
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
|
||||
|
@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
spin_lock_init(&lcd_dma.lock);
|
||||
spin_lock_init(&dma_chan_lock);
|
||||
|
||||
for (ch = 0; ch < dma_chan_count; ch++) {
|
||||
|
@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
/* FIXME: Update LCD DMA to work on 24xx */
|
||||
if (cpu_class_is_omap1()) {
|
||||
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
|
||||
"LCD DMA", NULL);
|
||||
if (r != 0) {
|
||||
int i;
|
||||
|
||||
printk(KERN_ERR "unable to request IRQ for LCD DMA "
|
||||
"(error %d)\n", r);
|
||||
for (i = 0; i < dma_chan_count; i++)
|
||||
free_irq(omap1_dma_irq[i], (void *) (i + 1));
|
||||
goto out_free;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_free:
|
||||
|
|
|
@ -80,47 +80,8 @@ static struct platform_device omap_i2c_devices[] = {
|
|||
#endif
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP24XX)
|
||||
static const int omap24xx_pins[][2] = {
|
||||
{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
|
||||
{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
|
||||
};
|
||||
#else
|
||||
static const int omap24xx_pins[][2] = {};
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
static const int omap34xx_pins[][2] = {
|
||||
{ K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
|
||||
{ AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
|
||||
{ AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
|
||||
};
|
||||
#else
|
||||
static const int omap34xx_pins[][2] = {};
|
||||
#endif
|
||||
|
||||
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
|
||||
|
||||
static void __init omap_i2c_mux_pins(int bus)
|
||||
{
|
||||
int scl, sda;
|
||||
|
||||
if (cpu_class_is_omap1()) {
|
||||
scl = I2C_SCL;
|
||||
sda = I2C_SDA;
|
||||
} else if (cpu_is_omap24xx()) {
|
||||
scl = omap24xx_pins[bus][0];
|
||||
sda = omap24xx_pins[bus][1];
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
scl = omap34xx_pins[bus][0];
|
||||
sda = omap34xx_pins[bus][1];
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
omap_cfg_reg(sda);
|
||||
omap_cfg_reg(scl);
|
||||
}
|
||||
|
||||
static int __init omap_i2c_nr_ports(void)
|
||||
{
|
||||
int ports = 0;
|
||||
|
@ -156,7 +117,6 @@ static int __init omap_i2c_add_bus(int bus_id)
|
|||
res[1].start = irq;
|
||||
}
|
||||
|
||||
omap_i2c_mux_pins(bus_id - 1);
|
||||
return platform_device_register(pdev);
|
||||
}
|
||||
|
||||
|
@ -209,7 +169,7 @@ static int __init omap_register_i2c_bus_cmdline(void)
|
|||
subsys_initcall(omap_register_i2c_bus_cmdline);
|
||||
|
||||
/**
|
||||
* omap_register_i2c_bus - register I2C bus with device descriptors
|
||||
* omap_plat_register_i2c_bus - register I2C bus with device descriptors
|
||||
* @bus_id: bus id counting from number 1
|
||||
* @clkrate: clock rate of the bus in kHz
|
||||
* @info: pointer into I2C device descriptor table or NULL
|
||||
|
@ -217,7 +177,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline);
|
|||
*
|
||||
* Returns 0 on success or an error code.
|
||||
*/
|
||||
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
struct i2c_board_info const *info,
|
||||
unsigned len)
|
||||
{
|
||||
|
|
|
@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data {
|
|||
void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
|
||||
};
|
||||
|
||||
/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
|
||||
struct omap_gpio_switch_config {
|
||||
char name[12];
|
||||
u16 gpio;
|
||||
int flags:4;
|
||||
int type:4;
|
||||
int key_code:24; /* Linux key code */
|
||||
};
|
||||
|
||||
struct omap_uart_config {
|
||||
/* Bit field of UARTs present; bit 0 --> UART1 */
|
||||
unsigned int enabled_uarts;
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user