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devicetree: fix newly added exynos sata bindings

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Commit ba0d7ed391 "ARM: dts: enable ahci sata and sata phy for
exynos5250" added a new binding document for the sata phy device,
and changed the sata controller binding. However, in both cases
significant aspects of the binding remained undocumented.
This attempts to reconstruct the actual binding from the usage.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Arnd Bergmann 2014-03-29 02:15:43 +01:00
parent 9e0c42ea3d
commit 9dfbff16b4
2 changed files with 13 additions and 3 deletions
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10
Documentation/devicetree/bindings/ata/exynos-sata.txt
View File

@ -8,8 +8,14 @@ Required properties:
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
- phys : as mentioned in phy-bindings.txt
- phy-names : as mentioned in phy-bindings.txt
- phys : Must contain exactly one entry as specified
in phy-bindings.txt
- phy-names : Must be "sata-phy"
Optional properties:
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Shall be "sata" for the external SATA bus clock,
and "sclk_sata" for the internal controller clock.
Example:
sata@122f0000 {

6
Documentation/devicetree/bindings/phy/samsung-phy.txt
View File

@ -30,7 +30,11 @@ Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
- reg : offset and length of the SATA PHY register set;
- #phy-cells : from the generic phy bindings;
- #phy-cells : must be zero
- clocks : must be exactly one entry
- clock-names : must be "sata_phyctrl"
- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
Example:
sata_phy: sata-phy@12170000 {