AcoSail/kernel_optimize_test
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sh: get rid of div6 clock names

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Get rid of div6 clock names on
sh7343/sh7366/sh7722/sh7723/sh7724

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm 2010-05-10 14:02:09 +00:00 committed by Paul Mundt
parent 098ec49b68
commit 9e1985e13d
6 changed files with 14 additions and 18 deletions
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11
arch/sh/include/asm/clock.h
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@ -151,12 +151,11 @@ int sh_clk_div4_enable_register(struct clk *clks, int nr,
int sh_clk_div4_reparent_register(struct clk *clks, int nr,
struct clk_div4_table *table);
#define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
{ \
.name = _name, \
.parent = _parent, \
.enable_reg = (void __iomem *)_reg, \
.flags = _flags, \
#define SH_CLK_DIV6(_parent, _reg, _flags) \
{ \
.parent = _parent, \
.enable_reg = (void __iomem *)_reg, \
.flags = _flags, \
}
int sh_clk_div6_register(struct clk *clks, int nr);

2
arch/sh/kernel/cpu/sh4a/clock-sh7343.c
View File

@ -139,7 +139,7 @@ struct clk div4_clks[DIV4_NR] = {
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
#define MSTP(_str, _parent, _reg, _bit, _flags) \

2
arch/sh/kernel/cpu/sh4a/clock-sh7366.c
View File

@ -142,7 +142,7 @@ struct clk div4_clks[DIV4_NR] = {
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
#define MSTP(_str, _parent, _reg, _bit, _flags) \

2
arch/sh/kernel/cpu/sh4a/clock-sh7722.c
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@ -152,7 +152,7 @@ struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
static struct clk mstp_clks[HWBLK_NR] = {

2
arch/sh/kernel/cpu/sh4a/clock-sh7723.c
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@ -152,7 +152,7 @@ struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
enum { DIV6_V, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
[DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
};
static struct clk mstp_clks[] = {

13
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
View File

@ -166,15 +166,12 @@ struct clk div4_clks[DIV4_NR] = {
enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
#define DIV6(_str, _reg, _flags) \
SH_CLK_DIV6(_str, &div3_clk, _reg, _flags)
struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = DIV6("video_clk", VCLKCR, 0),
[DIV6_FA] = DIV6("fsia_clk", FCLKACR, 0),
[DIV6_FB] = DIV6("fsib_clk", FCLKBCR, 0),
[DIV6_I] = DIV6("irda_clk", IRDACLKCR, 0),
[DIV6_S] = DIV6("spu_clk", SPUCLKCR, CLK_ENABLE_ON_INIT),
[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
[DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
[DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
};
static struct clk mstp_clks[HWBLK_NR] = {