forked from luck/tmp_suning_uos_patched
Reset controller updates for v5.9
This tag moves the reset-simple header out of drivers/reset for use by drivers outside of drivers/reset, adds a .reset() callback to reset-simple, converts i.MX reset bindings to json-schema, fixes a compile warning in the reset-intel-gw driver, and replaces some HTTP links with HTTPS ones in comments. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXxWSARcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwAP6AP4ld+W8CqwjEw+tkTVoCcGpE3v4 rmeEao1MtXtttiG9bAEAl2y794/zu0cXI0UEYqbhuqDYG/z8uXoBRvTGEP7UqQc= =tScp -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux into arm/drivers Reset controller updates for v5.9 This tag moves the reset-simple header out of drivers/reset for use by drivers outside of drivers/reset, adds a .reset() callback to reset-simple, converts i.MX reset bindings to json-schema, fixes a compile warning in the reset-intel-gw driver, and replaces some HTTP links with HTTPS ones in comments. * tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux: reset: Replace HTTP links with HTTPS ones reset: intel: fix a compile warning about REG_OFFSET redefined dt-bindings: reset: Convert i.MX7 reset to json-schema dt-bindings: reset: Convert i.MX reset to json-schema reset: simple: Add reset callback reset: Move reset-simple header out of drivers/reset Link: https://lore.kernel.org/r/b718f052e38abbaac599d80645376b75e54aa5bd.camel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
9e586c8431
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@ -1,49 +0,0 @@
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|||
Freescale i.MX System Reset Controller
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||||
======================================
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||||
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "fsl,<chip>-src"
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- reg: should be register base and length as documented in the
|
||||
datasheet
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- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
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in this order.
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- #reset-cells: 1, see below
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example:
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src: src@20d8000 {
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compatible = "fsl,imx6q-src";
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reg = <0x020d8000 0x4000>;
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interrupts = <0 91 0x04 0 96 0x04>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The system reset controller can be used to reset the GPU, VPU,
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IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
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nodes should specify the reset line on the SRC in their resets
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property, containing a phandle to the SRC device node and a
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RESET_INDEX specifying which module to reset, as described in
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reset.txt
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example:
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ipu1: ipu@2400000 {
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resets = <&src 2>;
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};
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ipu2: ipu@2800000 {
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resets = <&src 4>;
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};
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The following RESET_INDEX values are valid for i.MX5:
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GPU_RESET 0
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VPU_RESET 1
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IPU1_RESET 2
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OPEN_VG_RESET 3
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The following additional RESET_INDEX value is valid for i.MX6:
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IPU2_RESET 4
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82
Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
Normal file
82
Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
Normal file
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@ -0,0 +1,82 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX System Reset Controller
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maintainers:
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- Philipp Zabel <p.zabel@pengutronix.de>
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|
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description: |
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The system reset controller can be used to reset the GPU, VPU,
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IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
|
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nodes should specify the reset line on the SRC in their resets
|
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property, containing a phandle to the SRC device node and a
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RESET_INDEX specifying which module to reset, as described in
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reset.txt
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|
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The following RESET_INDEX values are valid for i.MX5:
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GPU_RESET 0
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VPU_RESET 1
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IPU1_RESET 2
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OPEN_VG_RESET 3
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The following additional RESET_INDEX value is valid for i.MX6:
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IPU2_RESET 4
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properties:
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compatible:
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oneOf:
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx50-src"
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx53-src"
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx6q-src"
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx6sx-src"
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx6sl-src"
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx6ul-src"
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- const: "fsl,imx51-src"
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- items:
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- const: "fsl,imx6sll-src"
|
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- const: "fsl,imx51-src"
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|
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reg:
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maxItems: 1
|
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|
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interrupts:
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items:
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- description: SRC interrupt
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- description: CPU WDOG interrupts out of SRC
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minItems: 1
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maxItems: 2
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|
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'#reset-cells':
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const: 1
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|
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required:
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- compatible
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- reg
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- interrupts
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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reset-controller@73fd0000 {
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compatible = "fsl,imx51-src";
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reg = <0x73fd0000 0x4000>;
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interrupts = <75>;
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#reset-cells = <1>;
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};
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@ -1,56 +0,0 @@
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Freescale i.MX7 System Reset Controller
|
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======================================
|
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|
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Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
|
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- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
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- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
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- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"
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- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"
|
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- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain SRC interrupt
|
||||
- #reset-cells: 1, see below
|
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|
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example:
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src: reset-controller@30390000 {
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compatible = "fsl,imx7d-src", "syscon";
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reg = <0x30390000 0x2000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
The system reset controller can be used to reset various set of
|
||||
peripherals. Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
Example:
|
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|
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pcie: pcie@33800000 {
|
||||
|
||||
...
|
||||
|
||||
resets = <&src IMX7_RESET_PCIEPHY>,
|
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<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
|
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reset-names = "pciephy", "apps";
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||||
|
||||
...
|
||||
};
|
||||
|
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|
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For list of all valid reset indices see
|
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<dt-bindings/reset/imx7-reset.h> for i.MX7,
|
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
|
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
|
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and
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<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP
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58
Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml
Normal file
58
Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX7 System Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Andrey Smirnov <andrew.smirnov@gmail.com>
|
||||
|
||||
description: |
|
||||
The system reset controller can be used to reset various set of
|
||||
peripherals. Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For list of all valid reset indices see
|
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<dt-bindings/reset/imx7-reset.h> for i.MX7,
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||||
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
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<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
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|
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properties:
|
||||
compatible:
|
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items:
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- enum:
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- fsl,imx7d-src
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- fsl,imx8mq-src
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- fsl,imx8mp-src
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- const: syscon
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|
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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|
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'#reset-cells':
|
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const: 1
|
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|
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required:
|
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- compatible
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- reg
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- interrupts
|
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- '#reset-cells'
|
||||
|
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additionalProperties: false
|
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|
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examples:
|
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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|
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reset-controller@30390000 {
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compatible = "fsl,imx7d-src", "syscon";
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reg = <0x30390000 0x2000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
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#reset-cells = <1>;
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};
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@ -15,9 +15,9 @@
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#define RCU_RST_STAT 0x0024
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#define RCU_RST_REQ 0x0048
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#define REG_OFFSET GENMASK(31, 16)
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#define BIT_OFFSET GENMASK(15, 8)
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#define STAT_BIT_OFFSET GENMASK(7, 0)
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#define REG_OFFSET_MASK GENMASK(31, 16)
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#define BIT_OFFSET_MASK GENMASK(15, 8)
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#define STAT_BIT_OFFSET_MASK GENMASK(7, 0)
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#define to_reset_data(x) container_of(x, struct intel_reset_data, rcdev)
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|
|
@ -51,11 +51,11 @@ static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data,
|
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unsigned long id, u32 *rst_req,
|
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u32 *req_bit, u32 *stat_bit)
|
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{
|
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*rst_req = FIELD_GET(REG_OFFSET, id);
|
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*req_bit = FIELD_GET(BIT_OFFSET, id);
|
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*rst_req = FIELD_GET(REG_OFFSET_MASK, id);
|
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*req_bit = FIELD_GET(BIT_OFFSET_MASK, id);
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|
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if (data->soc_data->legacy)
|
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*stat_bit = FIELD_GET(STAT_BIT_OFFSET, id);
|
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*stat_bit = FIELD_GET(STAT_BIT_OFFSET_MASK, id);
|
||||
else
|
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*stat_bit = *req_bit;
|
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|
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|
|
@ -141,14 +141,14 @@ static int intel_reset_xlate(struct reset_controller_dev *rcdev,
|
|||
if (spec->args[1] > 31)
|
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return -EINVAL;
|
||||
|
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id = FIELD_PREP(REG_OFFSET, spec->args[0]);
|
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id |= FIELD_PREP(BIT_OFFSET, spec->args[1]);
|
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id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]);
|
||||
id |= FIELD_PREP(BIT_OFFSET_MASK, spec->args[1]);
|
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|
||||
if (data->soc_data->legacy) {
|
||||
if (spec->args[2] > 31)
|
||||
return -EINVAL;
|
||||
|
||||
id |= FIELD_PREP(STAT_BIT_OFFSET, spec->args[2]);
|
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id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, spec->args[2]);
|
||||
}
|
||||
|
||||
return id;
|
||||
|
|
@ -210,11 +210,11 @@ static int intel_reset_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
data->reboot_id = FIELD_PREP(REG_OFFSET, rb_id[0]);
|
||||
data->reboot_id |= FIELD_PREP(BIT_OFFSET, rb_id[1]);
|
||||
data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]);
|
||||
data->reboot_id |= FIELD_PREP(BIT_OFFSET_MASK, rb_id[1]);
|
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|
||||
if (data->soc_data->legacy)
|
||||
data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET, rb_id[2]);
|
||||
data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]);
|
||||
|
||||
data->restart_nb.notifier_call = intel_reset_restart_handler;
|
||||
data->restart_nb.priority = 128;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
|
|
@ -18,10 +19,9 @@
|
|||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/reset/reset-simple.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "reset-simple.h"
|
||||
|
||||
static inline struct reset_simple_data *
|
||||
to_reset_simple_data(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
|
|
@ -64,6 +64,24 @@ static int reset_simple_deassert(struct reset_controller_dev *rcdev,
|
|||
return reset_simple_update(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int reset_simple_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct reset_simple_data *data = to_reset_simple_data(rcdev);
|
||||
int ret;
|
||||
|
||||
if (!data->reset_us)
|
||||
return -ENOTSUPP;
|
||||
|
||||
ret = reset_simple_assert(rcdev, id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
usleep_range(data->reset_us, data->reset_us * 2);
|
||||
|
||||
return reset_simple_deassert(rcdev, id);
|
||||
}
|
||||
|
||||
static int reset_simple_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
|
|
@ -81,6 +99,7 @@ static int reset_simple_status(struct reset_controller_dev *rcdev,
|
|||
const struct reset_control_ops reset_simple_ops = {
|
||||
.assert = reset_simple_assert,
|
||||
.deassert = reset_simple_deassert,
|
||||
.reset = reset_simple_reset,
|
||||
.status = reset_simple_status,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(reset_simple_ops);
|
||||
|
|
|
|||
|
|
@ -11,13 +11,12 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/reset/reset-simple.h>
|
||||
#include <linux/reset/socfpga.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "reset-simple.h"
|
||||
|
||||
#define SOCFPGA_NR_BANKS 8
|
||||
|
||||
static int a10_reset_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -14,13 +14,12 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/reset/reset-simple.h>
|
||||
#include <linux/reset/sunxi.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "reset-simple.h"
|
||||
|
||||
static int sunxi_reset_init(struct device_node *np)
|
||||
{
|
||||
struct reset_simple_data *data;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* TI SYSCON regmap reset driver
|
||||
*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Andrew F. Davis <afd@ti.com>
|
||||
* Suman Anna <afd@ti.com>
|
||||
*
|
||||
|
|
|
|||
|
|
@ -9,8 +9,7 @@
|
|||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
#include "reset-simple.h"
|
||||
#include <linux/reset/reset-simple.h>
|
||||
|
||||
#define MAX_CLKS 2
|
||||
#define MAX_RSTS 2
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* TI Syscon Reset definitions
|
||||
*
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
|
||||
|
|
|
|||
|
|
@ -27,6 +27,12 @@
|
|||
* @status_active_low: if true, bits read back as cleared while the reset is
|
||||
* asserted. Otherwise, bits read back as set while the
|
||||
* reset is asserted.
|
||||
* @reset_us: Minimum delay in microseconds needed that needs to be
|
||||
* waited for between an assert and a deassert to reset the
|
||||
* device. If multiple consumers with different delay
|
||||
* requirements are connected to this controller, it must
|
||||
* be the largest minimum delay. 0 means that such a delay is
|
||||
* unknown and the reset operation is unsupported.
|
||||
*/
|
||||
struct reset_simple_data {
|
||||
spinlock_t lock;
|
||||
|
|
@ -34,6 +40,7 @@ struct reset_simple_data {
|
|||
struct reset_controller_dev rcdev;
|
||||
bool active_low;
|
||||
bool status_active_low;
|
||||
unsigned int reset_us;
|
||||
};
|
||||
|
||||
extern const struct reset_control_ops reset_simple_ops;
|
||||
Loading…
Reference in New Issue
Block a user