forked from luck/tmp_suning_uos_patched
media: tegra: Changes for v5.8-rc1
This contains a V4L2 video capture driver for Tegra210. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl6+pDETHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZfLEACBVTUrkg3OwO9D/01Llr/DpAzMZpa7 bjb462A+2ftgn41sw9Wg9hkdMpPYp3i1OSXgboPU9VxdZ3qVOEYiNp/uOMGWE1J3 QOF720wSRgeGPf/+MJvicc0XHGv9Lz0LKjmI0wyfWKYIwyVWm4/UzxJ+JdM9FA2g ivuw5aA5XcxDt6lf++B/ZD3l1imXs7F8viPYW5O/ViNG5tQ0sLFb/PA4jlO05Fsk qm+1e0ga6Cz/MO7fDNQzJ0+EX0jFYABiQzrKx4hbMZVIlxm3H56U03dwb+dLcD37 JLtAHMt6eEHX1hFYALG0lc9RY+8qOznt2bgbjcu8Fu5rgDqY+hLjRbDcgEEhw3y8 wPXROJD+c6+9TNXOfRxG8PPn1dHccPEnU4AgbkpZtZrns+rGRp+5/kgw/7xIyzfq /T3euUPDGdQq9OkJlx6P5KVY9OkJgVmI6qP1/nBPqMSqmzLAyDlBIlCahRtCBEX/ pWq1xlwccVKpRMIuBAXmNZre0W70+9/QqY41d+TbcVo4JfDbfJ/BUci9VFuCNGM1 9jiFfs5OOOfVhtmJjnUcaDHKAe1Ie9aplEdbNQNkF/oVpEbEzPjtroon5tg9bmj5 O5VhzBSamHvz4PU9HbtRtBhIdIOmmp/qd2I8gGc1LChtl9eY4pD4CkDwcxP/nMO6 G2DLtELY+mJQ2Q== =ZA0j -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers media: tegra: Changes for v5.8-rc1 This contains a V4L2 video capture driver for Tegra210. * tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: media: tegra-video: Do not enable COMPILE_TEST MAINTAINERS: correct path in TEGRA VIDEO DRIVER media: tegra-video: Make tegra210_video_formats static MAINTAINERS: Add Tegra Video driver section media: tegra-video: Add Tegra210 Video input driver dt-bindings: i2c: tegra: Document Tegra210 VI I2C dt-bindings: tegra: Add VI and CSI bindings dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 dt-bindings: clock: tegra: Remove PMC clock IDs dt-bindings: clock: tegra: Add clock ID for CSI TPG clock Link: https://lore.kernel.org/r/20200515145311.1580134-7-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
9ffc30a66d
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@ -0,0 +1,56 @@
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Binding for NVIDIA Tegra20 CPUFreq
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==================================
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Required properties:
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- clocks: Must contain an entry for the CPU clock.
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See ../clocks/clock-bindings.txt for details.
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- operating-points-v2: See ../bindings/opp/opp.txt for details.
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- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
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For each opp entry in 'operating-points-v2' table:
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- opp-supported-hw: Two bitfields indicating:
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On Tegra20:
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1. CPU process ID mask
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2. SoC speedo ID mask
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On Tegra30:
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1. CPU process ID mask
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2. CPU speedo ID mask
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A bitwise AND is performed against these values and if any bit
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matches, the OPP gets enabled.
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- opp-microvolt: CPU voltage triplet.
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Optional properties:
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- cpu-supply: Phandle to the CPU power supply.
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Example:
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regulators {
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cpu_reg: regulator0 {
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regulator-name = "vdd_cpu";
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp@456000000 {
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clock-latency-ns = <125000>;
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opp-microvolt = <825000 825000 1125000>;
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opp-supported-hw = <0x03 0x0001>;
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opp-hz = /bits/ 64 <456000000>;
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};
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...
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};
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a9";
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clocks = <&tegra_car TEGRA20_CLK_CCLK>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-supply = <&cpu_reg>;
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#cooling-cells = <2>;
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};
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};
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@ -40,14 +40,30 @@ of the following host1x client modules:
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Required properties:
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- compatible: "nvidia,tegra<chip>-vi"
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- reg: Physical base address and length of the controller's registers.
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- reg: Physical base address and length of the controller registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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- clocks: clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- vi
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- Tegra20/Tegra30/Tegra114/Tegra124:
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- vi
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- Tegra210:
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- power-domains: Must include venc powergate node as vi is in VE partition.
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- Tegra210 has CSI part of VI sharing same host interface and register space.
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So, VI device node should have CSI child node.
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- csi: mipi csi interface to vi
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Required properties:
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- compatible: "nvidia,tegra210-csi"
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- reg: Physical base address offset to parent and length of the controller
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registers.
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- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
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See ../clocks/clock-bindings.txt for details.
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- power-domains: Must include sor powergate node as csicil is in
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SOR partition.
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- epp: encoder pre-processor
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@ -309,13 +325,44 @@ Example:
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reset-names = "mpe";
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};
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vi {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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resets = <&tegra_car 100>;
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reset-names = "vi";
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vi@54080000 {
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compatible = "nvidia,tegra210-vi";
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reg = <0x0 0x54080000 0x0 0x700>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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clocks = <&tegra_car TEGRA210_CLK_VI>;
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power-domains = <&pd_venc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x54080000 0x2000>;
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csi@838 {
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compatible = "nvidia,tegra210-csi";
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reg = <0x838 0x1300>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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assigned-clock-rates = <102000000>,
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<102000000>,
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<102000000>,
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<972000000>;
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clocks = <&tegra_car TEGRA210_CLK_CSI>,
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<&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
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power-domains = <&pd_sor>;
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};
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};
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epp {
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|
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@ -35,6 +35,12 @@ Required properties:
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Due to above changes, Tegra114 I2C driver makes incompatible with
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previous hardware driver. Hence, tegra114 I2C controller is compatible
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with "nvidia,tegra114-i2c".
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nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
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host1x domain and typically used for camera use-cases. This VI I2C
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controller is mostly compatible with the programming model of the
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regular I2C controllers with a few exceptions. The I2C registers start
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at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
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(rather than 4) and the controller does not support slave mode.
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- reg: Should contain I2C controller registers physical address and length.
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- interrupts: Should contain I2C controller interrupts.
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- address-cells: Address cells for I2C device address.
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|
|
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@ -0,0 +1,82 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra210 SoC External Memory Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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description: |
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The EMC interfaces with the off-chip SDRAM to service the request stream
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sent from the memory controller.
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properties:
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compatible:
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const: nvidia,tegra210-emc
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reg:
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maxItems: 3
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clocks:
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items:
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- description: external memory clock
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clock-names:
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items:
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- const: emc
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interrupts:
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items:
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- description: EMC general interrupt
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memory-region:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to a reserved memory region describing the table of EMC
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frequencies trained by the firmware
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nvidia,memory-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of the memory controller node
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- nvidia,memory-controller
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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emc_table: emc-table@83400000 {
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compatible = "nvidia,tegra210-emc-table";
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reg = <0x83400000 0x10000>;
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};
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};
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external-memory-controller@7001b000 {
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compatible = "nvidia,tegra210-emc";
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reg = <0x7001b000 0x1000>,
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<0x7001e000 0x1000>,
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<0x7001f000 0x1000>;
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clocks = <&tegra_car TEGRA210_CLK_EMC>;
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clock-names = "emc";
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&emc_table>;
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nvidia,memory-controller = <&mc>;
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};
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10
MAINTAINERS
10
MAINTAINERS
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@ -16598,6 +16598,16 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
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S: Supported
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F: drivers/spi/spi-tegra*
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TEGRA VIDEO DRIVER
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M: Thierry Reding <thierry.reding@gmail.com>
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M: Jonathan Hunter <jonathanh@nvidia.com>
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M: Sowjanya Komatineni <skomatineni@nvidia.com>
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L: linux-media@vger.kernel.org
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L: linux-tegra@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
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F: drivers/staging/media/tegra-video/
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TEGRA XUSB PADCTL DRIVER
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M: JC Kuo <jckuo@nvidia.com>
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S: Supported
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|
|
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@ -34,6 +34,8 @@ source "drivers/staging/media/sunxi/Kconfig"
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source "drivers/staging/media/tegra-vde/Kconfig"
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source "drivers/staging/media/tegra-video/Kconfig"
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source "drivers/staging/media/ipu3/Kconfig"
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source "drivers/staging/media/soc_camera/Kconfig"
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|
|
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@ -4,6 +4,7 @@ obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/
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obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/
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obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
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obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/
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obj-$(CONFIG_TEGRA_VDE) += tegra-vde/
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obj-$(CONFIG_VIDEO_HANTRO) += hantro/
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obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/
|
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|
|
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12
drivers/staging/media/tegra-video/Kconfig
Normal file
12
drivers/staging/media/tegra-video/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config VIDEO_TEGRA
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tristate "NVIDIA Tegra VI driver"
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depends on TEGRA_HOST1X
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select VIDEO_V4L2
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select MEDIA_CONTROLLER
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select VIDEOBUF2_DMA_CONTIG
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help
|
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Choose this option if you have an NVIDIA Tegra SoC.
|
||||
|
||||
To compile this driver as a module, choose M here: the module
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will be called tegra-video.
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8
drivers/staging/media/tegra-video/Makefile
Normal file
8
drivers/staging/media/tegra-video/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
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|||
# SPDX-License-Identifier: GPL-2.0
|
||||
tegra-video-objs := \
|
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video.o \
|
||||
vi.o \
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||||
csi.o
|
||||
|
||||
tegra-video-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
|
||||
obj-$(CONFIG_VIDEO_TEGRA) += tegra-video.o
|
||||
11
drivers/staging/media/tegra-video/TODO
Normal file
11
drivers/staging/media/tegra-video/TODO
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
TODO list
|
||||
* Currently driver supports Tegra build-in TPG only with direct media links
|
||||
from CSI to VI. Add kernel config CONFIG_VIDEO_TEGRA_TPG and update the
|
||||
driver to do TPG Vs Sensor media links based on CONFIG_VIDEO_TEGRA_TPG.
|
||||
* Add real camera sensor capture support.
|
||||
* Add Tegra CSI MIPI pads calibration.
|
||||
* Add MIPI clock Settle time computation based on the data rate.
|
||||
* Add support for Ganged mode.
|
||||
* Add RAW10 packed video format support to Tegra210 video formats.
|
||||
* Add support for suspend and resume.
|
||||
* Make sure v4l2-compliance tests pass with all of the above implementations.
|
||||
539
drivers/staging/media/tegra-video/csi.c
Normal file
539
drivers/staging/media/tegra-video/csi.c
Normal file
|
|
@ -0,0 +1,539 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/host1x.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include "csi.h"
|
||||
#include "video.h"
|
||||
|
||||
static inline struct tegra_csi *
|
||||
host1x_client_to_csi(struct host1x_client *client)
|
||||
{
|
||||
return container_of(client, struct tegra_csi, client);
|
||||
}
|
||||
|
||||
static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *subdev)
|
||||
{
|
||||
return container_of(subdev, struct tegra_csi_channel, subdev);
|
||||
}
|
||||
|
||||
/*
|
||||
* CSI is a separate subdevice which has 6 source pads to generate
|
||||
* test pattern. CSI subdevice pad ops are used only for TPG and
|
||||
* allows below TPG formats.
|
||||
*/
|
||||
static const struct v4l2_mbus_framefmt tegra_csi_tpg_fmts[] = {
|
||||
{
|
||||
TEGRA_DEF_WIDTH,
|
||||
TEGRA_DEF_HEIGHT,
|
||||
MEDIA_BUS_FMT_SRGGB10_1X10,
|
||||
V4L2_FIELD_NONE,
|
||||
V4L2_COLORSPACE_SRGB
|
||||
},
|
||||
{
|
||||
TEGRA_DEF_WIDTH,
|
||||
TEGRA_DEF_HEIGHT,
|
||||
MEDIA_BUS_FMT_RGB888_1X32_PADHI,
|
||||
V4L2_FIELD_NONE,
|
||||
V4L2_COLORSPACE_SRGB
|
||||
},
|
||||
};
|
||||
|
||||
static const struct v4l2_frmsize_discrete tegra_csi_tpg_sizes[] = {
|
||||
{ 1280, 720 },
|
||||
{ 1920, 1080 },
|
||||
{ 3840, 2160 },
|
||||
};
|
||||
|
||||
/*
|
||||
* V4L2 Subdevice Pad Operations
|
||||
*/
|
||||
static int csi_enum_bus_code(struct v4l2_subdev *subdev,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_mbus_code_enum *code)
|
||||
{
|
||||
if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts))
|
||||
return -EINVAL;
|
||||
|
||||
code->code = tegra_csi_tpg_fmts[code->index].code;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csi_get_format(struct v4l2_subdev *subdev,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_format *fmt)
|
||||
{
|
||||
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
|
||||
|
||||
fmt->format = csi_chan->format;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csi_get_frmrate_table_index(struct tegra_csi *csi, u32 code,
|
||||
u32 width, u32 height)
|
||||
{
|
||||
const struct tpg_framerate *frmrate;
|
||||
unsigned int i;
|
||||
|
||||
frmrate = csi->soc->tpg_frmrate_table;
|
||||
for (i = 0; i < csi->soc->tpg_frmrate_table_size; i++) {
|
||||
if (frmrate[i].code == code &&
|
||||
frmrate[i].frmsize.width == width &&
|
||||
frmrate[i].frmsize.height == height) {
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void csi_chan_update_blank_intervals(struct tegra_csi_channel *csi_chan,
|
||||
u32 code, u32 width, u32 height)
|
||||
{
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table;
|
||||
int index;
|
||||
|
||||
index = csi_get_frmrate_table_index(csi_chan->csi, code,
|
||||
width, height);
|
||||
if (index >= 0) {
|
||||
csi_chan->h_blank = frmrate[index].h_blank;
|
||||
csi_chan->v_blank = frmrate[index].v_blank;
|
||||
csi_chan->framerate = frmrate[index].framerate;
|
||||
}
|
||||
}
|
||||
|
||||
static int csi_enum_framesizes(struct v4l2_subdev *subdev,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_frame_size_enum *fse)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++)
|
||||
if (fse->code == tegra_csi_tpg_fmts[i].code)
|
||||
break;
|
||||
|
||||
if (i == ARRAY_SIZE(tegra_csi_tpg_fmts))
|
||||
return -EINVAL;
|
||||
|
||||
fse->min_width = tegra_csi_tpg_sizes[fse->index].width;
|
||||
fse->max_width = tegra_csi_tpg_sizes[fse->index].width;
|
||||
fse->min_height = tegra_csi_tpg_sizes[fse->index].height;
|
||||
fse->max_height = tegra_csi_tpg_sizes[fse->index].height;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csi_enum_frameintervals(struct v4l2_subdev *subdev,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_frame_interval_enum *fie)
|
||||
{
|
||||
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table;
|
||||
int index;
|
||||
|
||||
/* one framerate per format and resolution */
|
||||
if (fie->index > 0)
|
||||
return -EINVAL;
|
||||
|
||||
index = csi_get_frmrate_table_index(csi_chan->csi, fie->code,
|
||||
fie->width, fie->height);
|
||||
if (index < 0)
|
||||
return -EINVAL;
|
||||
|
||||
fie->interval.numerator = 1;
|
||||
fie->interval.denominator = frmrate[index].framerate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int csi_set_format(struct v4l2_subdev *subdev,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_format *fmt)
|
||||
{
|
||||
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
|
||||
struct v4l2_mbus_framefmt *format = &fmt->format;
|
||||
const struct v4l2_frmsize_discrete *sizes;
|
||||
unsigned int i;
|
||||
|
||||
sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes,
|
||||
ARRAY_SIZE(tegra_csi_tpg_sizes),
|
||||
width, height,
|
||||
format->width, format->width);
|
||||
format->width = sizes->width;
|
||||
format->height = sizes->height;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++)
|
||||
if (format->code == tegra_csi_tpg_fmts[i].code)
|
||||
break;
|
||||
|
||||
if (i == ARRAY_SIZE(tegra_csi_tpg_fmts))
|
||||
i = 0;
|
||||
|
||||
format->code = tegra_csi_tpg_fmts[i].code;
|
||||
format->field = V4L2_FIELD_NONE;
|
||||
|
||||
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
|
||||
return 0;
|
||||
|
||||
/* update blanking intervals from frame rate table and format */
|
||||
csi_chan_update_blank_intervals(csi_chan, format->code,
|
||||
format->width, format->height);
|
||||
csi_chan->format = *format;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* V4L2 Subdevice Video Operations
|
||||
*/
|
||||
static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev,
|
||||
struct v4l2_subdev_frame_interval *vfi)
|
||||
{
|
||||
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
|
||||
|
||||
vfi->interval.numerator = 1;
|
||||
vfi->interval.denominator = csi_chan->framerate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable)
|
||||
{
|
||||
struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev);
|
||||
struct tegra_csi_channel *csi_chan = to_csi_chan(subdev);
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
int ret = 0;
|
||||
|
||||
csi_chan->pg_mode = chan->pg_mode;
|
||||
if (enable) {
|
||||
ret = pm_runtime_get_sync(csi->dev);
|
||||
if (ret < 0) {
|
||||
dev_err(csi->dev,
|
||||
"failed to get runtime PM: %d\n", ret);
|
||||
pm_runtime_put_noidle(csi->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = csi->ops->csi_start_streaming(csi_chan);
|
||||
if (ret < 0)
|
||||
goto rpm_put;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
csi->ops->csi_stop_streaming(csi_chan);
|
||||
|
||||
rpm_put:
|
||||
pm_runtime_put(csi->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* V4L2 Subdevice Operations
|
||||
*/
|
||||
static const struct v4l2_subdev_video_ops tegra_csi_video_ops = {
|
||||
.s_stream = tegra_csi_s_stream,
|
||||
.g_frame_interval = tegra_csi_g_frame_interval,
|
||||
.s_frame_interval = tegra_csi_g_frame_interval,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_pad_ops tegra_csi_pad_ops = {
|
||||
.enum_mbus_code = csi_enum_bus_code,
|
||||
.enum_frame_size = csi_enum_framesizes,
|
||||
.enum_frame_interval = csi_enum_frameintervals,
|
||||
.get_fmt = csi_get_format,
|
||||
.set_fmt = csi_set_format,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_ops tegra_csi_ops = {
|
||||
.video = &tegra_csi_video_ops,
|
||||
.pad = &tegra_csi_pad_ops,
|
||||
};
|
||||
|
||||
static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi)
|
||||
{
|
||||
struct device_node *node = csi->dev->of_node;
|
||||
unsigned int port_num;
|
||||
struct tegra_csi_channel *chan;
|
||||
unsigned int tpg_channels = csi->soc->csi_max_channels;
|
||||
|
||||
/* allocate CSI channel for each CSI x2 ports */
|
||||
for (port_num = 0; port_num < tpg_channels; port_num++) {
|
||||
chan = kzalloc(sizeof(*chan), GFP_KERNEL);
|
||||
if (!chan)
|
||||
return -ENOMEM;
|
||||
|
||||
list_add_tail(&chan->list, &csi->csi_chans);
|
||||
chan->csi = csi;
|
||||
chan->csi_port_num = port_num;
|
||||
chan->numlanes = 2;
|
||||
chan->of_node = node;
|
||||
chan->numpads = 1;
|
||||
chan->pads[0].flags = MEDIA_PAD_FL_SOURCE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_csi_channel_init(struct tegra_csi_channel *chan)
|
||||
{
|
||||
struct tegra_csi *csi = chan->csi;
|
||||
struct v4l2_subdev *subdev;
|
||||
int ret;
|
||||
|
||||
/* initialize the default format */
|
||||
chan->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
|
||||
chan->format.field = V4L2_FIELD_NONE;
|
||||
chan->format.colorspace = V4L2_COLORSPACE_SRGB;
|
||||
chan->format.width = TEGRA_DEF_WIDTH;
|
||||
chan->format.height = TEGRA_DEF_HEIGHT;
|
||||
csi_chan_update_blank_intervals(chan, chan->format.code,
|
||||
chan->format.width,
|
||||
chan->format.height);
|
||||
/* initialize V4L2 subdevice and media entity */
|
||||
subdev = &chan->subdev;
|
||||
v4l2_subdev_init(subdev, &tegra_csi_ops);
|
||||
subdev->dev = csi->dev;
|
||||
snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg",
|
||||
chan->csi_port_num);
|
||||
|
||||
v4l2_set_subdevdata(subdev, chan);
|
||||
subdev->fwnode = of_fwnode_handle(chan->of_node);
|
||||
subdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
|
||||
|
||||
/* initialize media entity pads */
|
||||
ret = media_entity_pads_init(&subdev->entity, chan->numpads,
|
||||
chan->pads);
|
||||
if (ret < 0) {
|
||||
dev_err(csi->dev,
|
||||
"failed to initialize media entity: %d\n", ret);
|
||||
subdev->dev = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void tegra_csi_error_recover(struct v4l2_subdev *sd)
|
||||
{
|
||||
struct tegra_csi_channel *csi_chan = to_csi_chan(sd);
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
|
||||
/* stop streaming during error recovery */
|
||||
csi->ops->csi_stop_streaming(csi_chan);
|
||||
csi->ops->csi_err_recover(csi_chan);
|
||||
csi->ops->csi_start_streaming(csi_chan);
|
||||
}
|
||||
|
||||
static int tegra_csi_channels_init(struct tegra_csi *csi)
|
||||
{
|
||||
struct tegra_csi_channel *chan;
|
||||
int ret;
|
||||
|
||||
list_for_each_entry(chan, &csi->csi_chans, list) {
|
||||
ret = tegra_csi_channel_init(chan);
|
||||
if (ret) {
|
||||
dev_err(csi->dev,
|
||||
"failed to initialize channel-%d: %d\n",
|
||||
chan->csi_port_num, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_csi_channels_cleanup(struct tegra_csi *csi)
|
||||
{
|
||||
struct v4l2_subdev *subdev;
|
||||
struct tegra_csi_channel *chan, *tmp;
|
||||
|
||||
list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) {
|
||||
subdev = &chan->subdev;
|
||||
if (subdev->dev)
|
||||
media_entity_cleanup(&subdev->entity);
|
||||
list_del(&chan->list);
|
||||
kfree(chan);
|
||||
}
|
||||
}
|
||||
|
||||
static int __maybe_unused csi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct tegra_csi *csi = dev_get_drvdata(dev);
|
||||
|
||||
clk_bulk_disable_unprepare(csi->soc->num_clks, csi->clks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused csi_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct tegra_csi *csi = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(csi->soc->num_clks, csi->clks);
|
||||
if (ret < 0) {
|
||||
dev_err(csi->dev, "failed to enable clocks: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_csi_init(struct host1x_client *client)
|
||||
{
|
||||
struct tegra_csi *csi = host1x_client_to_csi(client);
|
||||
struct tegra_video_device *vid = dev_get_drvdata(client->host);
|
||||
int ret;
|
||||
|
||||
INIT_LIST_HEAD(&csi->csi_chans);
|
||||
|
||||
ret = tegra_csi_tpg_channels_alloc(csi);
|
||||
if (ret < 0) {
|
||||
dev_err(csi->dev,
|
||||
"failed to allocate tpg channels: %d\n", ret);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
ret = tegra_csi_channels_init(csi);
|
||||
if (ret < 0)
|
||||
goto cleanup;
|
||||
|
||||
vid->csi = csi;
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
tegra_csi_channels_cleanup(csi);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra_csi_exit(struct host1x_client *client)
|
||||
{
|
||||
struct tegra_csi *csi = host1x_client_to_csi(client);
|
||||
|
||||
tegra_csi_channels_cleanup(csi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct host1x_client_ops csi_client_ops = {
|
||||
.init = tegra_csi_init,
|
||||
.exit = tegra_csi_exit,
|
||||
};
|
||||
|
||||
static int tegra_csi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_csi *csi;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
|
||||
if (!csi)
|
||||
return -ENOMEM;
|
||||
|
||||
csi->iomem = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(csi->iomem))
|
||||
return PTR_ERR(csi->iomem);
|
||||
|
||||
csi->soc = of_device_get_match_data(&pdev->dev);
|
||||
|
||||
csi->clks = devm_kcalloc(&pdev->dev, csi->soc->num_clks,
|
||||
sizeof(*csi->clks), GFP_KERNEL);
|
||||
if (!csi->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < csi->soc->num_clks; i++)
|
||||
csi->clks[i].id = csi->soc->clk_names[i];
|
||||
|
||||
ret = devm_clk_bulk_get(&pdev->dev, csi->soc->num_clks, csi->clks);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to get the clocks: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!pdev->dev.pm_domain) {
|
||||
ret = -ENOENT;
|
||||
dev_warn(&pdev->dev, "PM domain is not attached: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
csi->dev = &pdev->dev;
|
||||
csi->ops = csi->soc->ops;
|
||||
platform_set_drvdata(pdev, csi);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
/* initialize host1x interface */
|
||||
INIT_LIST_HEAD(&csi->client.list);
|
||||
csi->client.ops = &csi_client_ops;
|
||||
csi->client.dev = &pdev->dev;
|
||||
|
||||
ret = host1x_client_register(&csi->client);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to register host1x client: %d\n", ret);
|
||||
goto rpm_disable;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
rpm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra_csi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_csi *csi = platform_get_drvdata(pdev);
|
||||
int err;
|
||||
|
||||
err = host1x_client_unregister(&csi->client);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to unregister host1x client: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra_csi_of_id_table[] = {
|
||||
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
{ .compatible = "nvidia,tegra210-csi", .data = &tegra210_csi_soc },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra_csi_of_id_table);
|
||||
|
||||
static const struct dev_pm_ops tegra_csi_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(csi_runtime_suspend, csi_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
struct platform_driver tegra_csi_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-csi",
|
||||
.of_match_table = tegra_csi_of_id_table,
|
||||
.pm = &tegra_csi_pm_ops,
|
||||
},
|
||||
.probe = tegra_csi_probe,
|
||||
.remove = tegra_csi_remove,
|
||||
};
|
||||
147
drivers/staging/media/tegra-video/csi.h
Normal file
147
drivers/staging/media/tegra-video/csi.h
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA_CSI_H__
|
||||
#define __TEGRA_CSI_H__
|
||||
|
||||
#include <media/media-entity.h>
|
||||
#include <media/v4l2-subdev.h>
|
||||
|
||||
/*
|
||||
* Each CSI brick supports max of 4 lanes that can be used as either
|
||||
* one x4 port using both CILA and CILB partitions of a CSI brick or can
|
||||
* be used as two x2 ports with one x2 from CILA and the other x2 from
|
||||
* CILB.
|
||||
*/
|
||||
#define CSI_PORTS_PER_BRICK 2
|
||||
|
||||
/* each CSI channel can have one sink and one source pads */
|
||||
#define TEGRA_CSI_PADS_NUM 2
|
||||
|
||||
enum tegra_csi_cil_port {
|
||||
PORT_A = 0,
|
||||
PORT_B,
|
||||
};
|
||||
|
||||
enum tegra_csi_block {
|
||||
CSI_CIL_AB = 0,
|
||||
CSI_CIL_CD,
|
||||
CSI_CIL_EF,
|
||||
};
|
||||
|
||||
struct tegra_csi;
|
||||
|
||||
/**
|
||||
* struct tegra_csi_channel - Tegra CSI channel
|
||||
*
|
||||
* @list: list head for this entry
|
||||
* @subdev: V4L2 subdevice associated with this channel
|
||||
* @pads: media pads for the subdevice entity
|
||||
* @numpads: number of pads.
|
||||
* @csi: Tegra CSI device structure
|
||||
* @of_node: csi device tree node
|
||||
* @numlanes: number of lanes used per port/channel
|
||||
* @csi_port_num: CSI channel port number
|
||||
* @pg_mode: test pattern generator mode for channel
|
||||
* @format: active format of the channel
|
||||
* @framerate: active framerate for TPG
|
||||
* @h_blank: horizontal blanking for TPG active format
|
||||
* @v_blank: vertical blanking for TPG active format
|
||||
*/
|
||||
struct tegra_csi_channel {
|
||||
struct list_head list;
|
||||
struct v4l2_subdev subdev;
|
||||
struct media_pad pads[TEGRA_CSI_PADS_NUM];
|
||||
unsigned int numpads;
|
||||
struct tegra_csi *csi;
|
||||
struct device_node *of_node;
|
||||
unsigned int numlanes;
|
||||
u8 csi_port_num;
|
||||
u8 pg_mode;
|
||||
struct v4l2_mbus_framefmt format;
|
||||
unsigned int framerate;
|
||||
unsigned int h_blank;
|
||||
unsigned int v_blank;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tpg_framerate - Tegra CSI TPG framerate configuration
|
||||
*
|
||||
* @frmsize: frame resolution
|
||||
* @code: media bus format code
|
||||
* @h_blank: horizontal blanking used for TPG
|
||||
* @v_blank: vertical blanking interval used for TPG
|
||||
* @framerate: framerate achieved with the corresponding blanking intervals,
|
||||
* format and resolution.
|
||||
*/
|
||||
struct tpg_framerate {
|
||||
struct v4l2_frmsize_discrete frmsize;
|
||||
u32 code;
|
||||
unsigned int h_blank;
|
||||
unsigned int v_blank;
|
||||
unsigned int framerate;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_csi_ops - Tegra CSI operations
|
||||
*
|
||||
* @csi_start_streaming: programs csi hardware to enable streaming.
|
||||
* @csi_stop_streaming: programs csi hardware to disable streaming.
|
||||
* @csi_err_recover: csi hardware block recovery in case of any capture errors
|
||||
* due to missing source stream or due to improper csi input from
|
||||
* the external source.
|
||||
*/
|
||||
struct tegra_csi_ops {
|
||||
int (*csi_start_streaming)(struct tegra_csi_channel *csi_chan);
|
||||
void (*csi_stop_streaming)(struct tegra_csi_channel *csi_chan);
|
||||
void (*csi_err_recover)(struct tegra_csi_channel *csi_chan);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_csi_soc - NVIDIA Tegra CSI SoC structure
|
||||
*
|
||||
* @ops: csi hardware operations
|
||||
* @csi_max_channels: supported max streaming channels
|
||||
* @clk_names: csi and cil clock names
|
||||
* @num_clks: total clocks count
|
||||
* @tpg_frmrate_table: csi tpg frame rate table with blanking intervals
|
||||
* @tpg_frmrate_table_size: size of frame rate table
|
||||
*/
|
||||
struct tegra_csi_soc {
|
||||
const struct tegra_csi_ops *ops;
|
||||
unsigned int csi_max_channels;
|
||||
const char * const *clk_names;
|
||||
unsigned int num_clks;
|
||||
const struct tpg_framerate *tpg_frmrate_table;
|
||||
unsigned int tpg_frmrate_table_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_csi - NVIDIA Tegra CSI device structure
|
||||
*
|
||||
* @dev: device struct
|
||||
* @client: host1x_client struct
|
||||
* @iomem: register base
|
||||
* @clks: clock for CSI and CIL
|
||||
* @soc: pointer to SoC data structure
|
||||
* @ops: csi operations
|
||||
* @channels: list head for CSI channels
|
||||
*/
|
||||
struct tegra_csi {
|
||||
struct device *dev;
|
||||
struct host1x_client client;
|
||||
void __iomem *iomem;
|
||||
struct clk_bulk_data *clks;
|
||||
const struct tegra_csi_soc *soc;
|
||||
const struct tegra_csi_ops *ops;
|
||||
struct list_head csi_chans;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
extern const struct tegra_csi_soc tegra210_csi_soc;
|
||||
#endif
|
||||
|
||||
void tegra_csi_error_recover(struct v4l2_subdev *subdev);
|
||||
#endif
|
||||
978
drivers/staging/media/tegra-video/tegra210.c
Normal file
978
drivers/staging/media/tegra-video/tegra210.c
Normal file
|
|
@ -0,0 +1,978 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This source file contains Tegra210 supported video formats,
|
||||
* VI and CSI SoC specific data, operations and registers accessors.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/host1x.h>
|
||||
#include <linux/kthread.h>
|
||||
|
||||
#include "csi.h"
|
||||
#include "vi.h"
|
||||
|
||||
#define TEGRA_VI_SYNCPT_WAIT_TIMEOUT msecs_to_jiffies(200)
|
||||
|
||||
/* Tegra210 VI registers */
|
||||
#define TEGRA_VI_CFG_VI_INCR_SYNCPT 0x000
|
||||
#define VI_CFG_VI_INCR_SYNCPT_COND(x) (((x) & 0xff) << 8)
|
||||
#define VI_CSI_PP_FRAME_START(port) (5 + (port) * 4)
|
||||
#define VI_CSI_MW_ACK_DONE(port) (7 + (port) * 4)
|
||||
#define TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL 0x004
|
||||
#define VI_INCR_SYNCPT_NO_STALL BIT(8)
|
||||
#define TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR 0x008
|
||||
#define TEGRA_VI_CFG_CG_CTRL 0x0b8
|
||||
#define VI_CG_2ND_LEVEL_EN 0x1
|
||||
|
||||
/* Tegra210 VI CSI registers */
|
||||
#define TEGRA_VI_CSI_SW_RESET 0x000
|
||||
#define TEGRA_VI_CSI_SINGLE_SHOT 0x004
|
||||
#define SINGLE_SHOT_CAPTURE 0x1
|
||||
#define TEGRA_VI_CSI_IMAGE_DEF 0x00c
|
||||
#define BYPASS_PXL_TRANSFORM_OFFSET 24
|
||||
#define IMAGE_DEF_FORMAT_OFFSET 16
|
||||
#define IMAGE_DEF_DEST_MEM 0x1
|
||||
#define TEGRA_VI_CSI_IMAGE_SIZE 0x018
|
||||
#define IMAGE_SIZE_HEIGHT_OFFSET 16
|
||||
#define TEGRA_VI_CSI_IMAGE_SIZE_WC 0x01c
|
||||
#define TEGRA_VI_CSI_IMAGE_DT 0x020
|
||||
#define TEGRA_VI_CSI_SURFACE0_OFFSET_MSB 0x024
|
||||
#define TEGRA_VI_CSI_SURFACE0_OFFSET_LSB 0x028
|
||||
#define TEGRA_VI_CSI_SURFACE1_OFFSET_MSB 0x02c
|
||||
#define TEGRA_VI_CSI_SURFACE1_OFFSET_LSB 0x030
|
||||
#define TEGRA_VI_CSI_SURFACE2_OFFSET_MSB 0x034
|
||||
#define TEGRA_VI_CSI_SURFACE2_OFFSET_LSB 0x038
|
||||
#define TEGRA_VI_CSI_SURFACE0_STRIDE 0x054
|
||||
#define TEGRA_VI_CSI_SURFACE1_STRIDE 0x058
|
||||
#define TEGRA_VI_CSI_SURFACE2_STRIDE 0x05c
|
||||
#define TEGRA_VI_CSI_SURFACE_HEIGHT0 0x060
|
||||
#define TEGRA_VI_CSI_ERROR_STATUS 0x084
|
||||
|
||||
/* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
|
||||
#define TEGRA_CSI_INPUT_STREAM_CONTROL 0x000
|
||||
#define CSI_SKIP_PACKET_THRESHOLD_OFFSET 16
|
||||
#define TEGRA_CSI_PIXEL_STREAM_CONTROL0 0x004
|
||||
#define CSI_PP_PACKET_HEADER_SENT BIT(4)
|
||||
#define CSI_PP_DATA_IDENTIFIER_ENABLE BIT(5)
|
||||
#define CSI_PP_WORD_COUNT_SELECT_HEADER BIT(6)
|
||||
#define CSI_PP_CRC_CHECK_ENABLE BIT(7)
|
||||
#define CSI_PP_WC_CHECK BIT(8)
|
||||
#define CSI_PP_OUTPUT_FORMAT_STORE (0x3 << 16)
|
||||
#define CSI_PPA_PAD_LINE_NOPAD (0x2 << 24)
|
||||
#define CSI_PP_HEADER_EC_DISABLE (0x1 << 27)
|
||||
#define CSI_PPA_PAD_FRAME_NOPAD (0x2 << 28)
|
||||
#define TEGRA_CSI_PIXEL_STREAM_CONTROL1 0x008
|
||||
#define CSI_PP_TOP_FIELD_FRAME_OFFSET 0
|
||||
#define CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET 4
|
||||
#define TEGRA_CSI_PIXEL_STREAM_GAP 0x00c
|
||||
#define PP_FRAME_MIN_GAP_OFFSET 16
|
||||
#define TEGRA_CSI_PIXEL_STREAM_PP_COMMAND 0x010
|
||||
#define CSI_PP_ENABLE 0x1
|
||||
#define CSI_PP_DISABLE 0x2
|
||||
#define CSI_PP_RST 0x3
|
||||
#define CSI_PP_SINGLE_SHOT_ENABLE (0x1 << 2)
|
||||
#define CSI_PP_START_MARKER_FRAME_MAX_OFFSET 12
|
||||
#define TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME 0x014
|
||||
#define TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK 0x018
|
||||
#define TEGRA_CSI_PIXEL_PARSER_STATUS 0x01c
|
||||
|
||||
/* Tegra210 CSI PHY registers */
|
||||
/* CSI_PHY_CIL_COMMAND_0 offset 0x0d0 from TEGRA_CSI_PIXEL_PARSER_0_BASE */
|
||||
#define TEGRA_CSI_PHY_CIL_COMMAND 0x0d0
|
||||
#define CSI_A_PHY_CIL_NOP 0x0
|
||||
#define CSI_A_PHY_CIL_ENABLE 0x1
|
||||
#define CSI_A_PHY_CIL_DISABLE 0x2
|
||||
#define CSI_A_PHY_CIL_ENABLE_MASK 0x3
|
||||
#define CSI_B_PHY_CIL_NOP (0x0 << 8)
|
||||
#define CSI_B_PHY_CIL_ENABLE (0x1 << 8)
|
||||
#define CSI_B_PHY_CIL_DISABLE (0x2 << 8)
|
||||
#define CSI_B_PHY_CIL_ENABLE_MASK (0x3 << 8)
|
||||
|
||||
#define TEGRA_CSI_CIL_PAD_CONFIG0 0x000
|
||||
#define BRICK_CLOCK_A_4X (0x1 << 16)
|
||||
#define BRICK_CLOCK_B_4X (0x2 << 16)
|
||||
#define TEGRA_CSI_CIL_PAD_CONFIG1 0x004
|
||||
#define TEGRA_CSI_CIL_PHY_CONTROL 0x008
|
||||
#define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c
|
||||
#define TEGRA_CSI_CIL_STATUS 0x010
|
||||
#define TEGRA_CSI_CILX_STATUS 0x014
|
||||
#define TEGRA_CSI_CIL_SW_SENSOR_RESET 0x020
|
||||
|
||||
#define TEGRA_CSI_PATTERN_GENERATOR_CTRL 0x000
|
||||
#define PG_MODE_OFFSET 2
|
||||
#define PG_ENABLE 0x1
|
||||
#define PG_DISABLE 0x0
|
||||
#define TEGRA_CSI_PG_BLANK 0x004
|
||||
#define PG_VBLANK_OFFSET 16
|
||||
#define TEGRA_CSI_PG_PHASE 0x008
|
||||
#define TEGRA_CSI_PG_RED_FREQ 0x00c
|
||||
#define PG_RED_VERT_INIT_FREQ_OFFSET 16
|
||||
#define PG_RED_HOR_INIT_FREQ_OFFSET 0
|
||||
#define TEGRA_CSI_PG_RED_FREQ_RATE 0x010
|
||||
#define TEGRA_CSI_PG_GREEN_FREQ 0x014
|
||||
#define PG_GREEN_VERT_INIT_FREQ_OFFSET 16
|
||||
#define PG_GREEN_HOR_INIT_FREQ_OFFSET 0
|
||||
#define TEGRA_CSI_PG_GREEN_FREQ_RATE 0x018
|
||||
#define TEGRA_CSI_PG_BLUE_FREQ 0x01c
|
||||
#define PG_BLUE_VERT_INIT_FREQ_OFFSET 16
|
||||
#define PG_BLUE_HOR_INIT_FREQ_OFFSET 0
|
||||
#define TEGRA_CSI_PG_BLUE_FREQ_RATE 0x020
|
||||
#define TEGRA_CSI_PG_AOHDR 0x024
|
||||
#define TEGRA_CSI_CSI_SW_STATUS_RESET 0x214
|
||||
#define TEGRA_CSI_CLKEN_OVERRIDE 0x218
|
||||
|
||||
#define TEGRA210_CSI_PORT_OFFSET 0x34
|
||||
#define TEGRA210_CSI_CIL_OFFSET 0x0f4
|
||||
#define TEGRA210_CSI_TPG_OFFSET 0x18c
|
||||
|
||||
#define CSI_PP_OFFSET(block) ((block) * 0x800)
|
||||
#define TEGRA210_VI_CSI_BASE(x) (0x100 + (x) * 0x100)
|
||||
|
||||
/* Tegra210 VI registers accessors */
|
||||
static void tegra_vi_write(struct tegra_vi_channel *chan, unsigned int addr,
|
||||
u32 val)
|
||||
{
|
||||
writel_relaxed(val, chan->vi->iomem + addr);
|
||||
}
|
||||
|
||||
static u32 tegra_vi_read(struct tegra_vi_channel *chan, unsigned int addr)
|
||||
{
|
||||
return readl_relaxed(chan->vi->iomem + addr);
|
||||
}
|
||||
|
||||
/* Tegra210 VI_CSI registers accessors */
|
||||
static void vi_csi_write(struct tegra_vi_channel *chan, unsigned int addr,
|
||||
u32 val)
|
||||
{
|
||||
void __iomem *vi_csi_base;
|
||||
|
||||
vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(chan->portno);
|
||||
|
||||
writel_relaxed(val, vi_csi_base + addr);
|
||||
}
|
||||
|
||||
static u32 vi_csi_read(struct tegra_vi_channel *chan, unsigned int addr)
|
||||
{
|
||||
void __iomem *vi_csi_base;
|
||||
|
||||
vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(chan->portno);
|
||||
|
||||
return readl_relaxed(vi_csi_base + addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Tegra210 VI channel capture operations
|
||||
*/
|
||||
static int tegra_channel_capture_setup(struct tegra_vi_channel *chan)
|
||||
{
|
||||
u32 height = chan->format.height;
|
||||
u32 width = chan->format.width;
|
||||
u32 format = chan->fmtinfo->img_fmt;
|
||||
u32 data_type = chan->fmtinfo->img_dt;
|
||||
u32 word_count = (width * chan->fmtinfo->bit_width) / 8;
|
||||
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, 0xffffffff);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_DEF,
|
||||
((chan->pg_mode ? 0 : 1) << BYPASS_PXL_TRANSFORM_OFFSET) |
|
||||
(format << IMAGE_DEF_FORMAT_OFFSET) |
|
||||
IMAGE_DEF_DEST_MEM);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_DT, data_type);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_SIZE_WC, word_count);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_SIZE,
|
||||
(height << IMAGE_SIZE_HEIGHT_OFFSET) | width);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan)
|
||||
{
|
||||
/* disable clock gating to enable continuous clock */
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, 0);
|
||||
/*
|
||||
* Soft reset memory client interface, pixel format logic, sensor
|
||||
* control logic, and a shadow copy logic to bring VI to clean state.
|
||||
*/
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0xf);
|
||||
usleep_range(100, 200);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0x0);
|
||||
|
||||
/* enable back VI clock gating */
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, VI_CG_2ND_LEVEL_EN);
|
||||
}
|
||||
|
||||
static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan)
|
||||
{
|
||||
struct v4l2_subdev *subdev;
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Recover VI and CSI hardware blocks in case of missing frame start
|
||||
* events due to source not streaming or noisy csi inputs from the
|
||||
* external source or many outstanding frame start or MW_ACK_DONE
|
||||
* events which can cause CSI and VI hardware hang.
|
||||
* This helps to have a clean capture for next frame.
|
||||
*/
|
||||
val = vi_csi_read(chan, TEGRA_VI_CSI_ERROR_STATUS);
|
||||
dev_dbg(&chan->video.dev, "TEGRA_VI_CSI_ERROR_STATUS 0x%08x\n", val);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, val);
|
||||
|
||||
val = tegra_vi_read(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR);
|
||||
dev_dbg(&chan->video.dev,
|
||||
"TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR 0x%08x\n", val);
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR, val);
|
||||
|
||||
/* recover VI by issuing software reset and re-setup for capture */
|
||||
tegra_channel_vi_soft_reset(chan);
|
||||
tegra_channel_capture_setup(chan);
|
||||
|
||||
/* recover CSI block */
|
||||
subdev = tegra_channel_get_remote_subdev(chan);
|
||||
tegra_csi_error_recover(subdev);
|
||||
}
|
||||
|
||||
static struct tegra_channel_buffer *
|
||||
dequeue_buf_done(struct tegra_vi_channel *chan)
|
||||
{
|
||||
struct tegra_channel_buffer *buf = NULL;
|
||||
|
||||
spin_lock(&chan->done_lock);
|
||||
if (list_empty(&chan->done)) {
|
||||
spin_unlock(&chan->done_lock);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
buf = list_first_entry(&chan->done,
|
||||
struct tegra_channel_buffer, queue);
|
||||
if (buf)
|
||||
list_del_init(&buf->queue);
|
||||
spin_unlock(&chan->done_lock);
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
||||
static void release_buffer(struct tegra_vi_channel *chan,
|
||||
struct tegra_channel_buffer *buf,
|
||||
enum vb2_buffer_state state)
|
||||
{
|
||||
struct vb2_v4l2_buffer *vb = &buf->buf;
|
||||
|
||||
vb->sequence = chan->sequence++;
|
||||
vb->field = V4L2_FIELD_NONE;
|
||||
vb->vb2_buf.timestamp = ktime_get_ns();
|
||||
vb2_buffer_done(&vb->vb2_buf, state);
|
||||
}
|
||||
|
||||
static int tegra_channel_capture_frame(struct tegra_vi_channel *chan,
|
||||
struct tegra_channel_buffer *buf)
|
||||
{
|
||||
u32 thresh, value, frame_start, mw_ack_done;
|
||||
int bytes_per_line = chan->format.bytesperline;
|
||||
int err;
|
||||
|
||||
/* program buffer address by using surface 0 */
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB,
|
||||
(u64)buf->addr >> 32);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, buf->addr);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line);
|
||||
|
||||
/*
|
||||
* Tegra VI block interacts with host1x syncpt for synchronizing
|
||||
* programmed condition of capture state and hardware operation.
|
||||
* Frame start and Memory write acknowledge syncpts has their own
|
||||
* FIFO of depth 2.
|
||||
*
|
||||
* Syncpoint trigger conditions set through VI_INCR_SYNCPT register
|
||||
* are added to HW syncpt FIFO and when the HW triggers, syncpt
|
||||
* condition is removed from the FIFO and counter at syncpoint index
|
||||
* will be incremented by the hardware and software can wait for
|
||||
* counter to reach threshold to synchronize capturing frame with the
|
||||
* hardware capture events.
|
||||
*/
|
||||
|
||||
/* increase channel syncpoint threshold for FRAME_START */
|
||||
thresh = host1x_syncpt_incr_max(chan->frame_start_sp, 1);
|
||||
|
||||
/* Program FRAME_START trigger condition syncpt request */
|
||||
frame_start = VI_CSI_PP_FRAME_START(chan->portno);
|
||||
value = VI_CFG_VI_INCR_SYNCPT_COND(frame_start) |
|
||||
host1x_syncpt_id(chan->frame_start_sp);
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value);
|
||||
|
||||
/* increase channel syncpoint threshold for MW_ACK_DONE */
|
||||
buf->mw_ack_sp_thresh = host1x_syncpt_incr_max(chan->mw_ack_sp, 1);
|
||||
|
||||
/* Program MW_ACK_DONE trigger condition syncpt request */
|
||||
mw_ack_done = VI_CSI_MW_ACK_DONE(chan->portno);
|
||||
value = VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) |
|
||||
host1x_syncpt_id(chan->mw_ack_sp);
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value);
|
||||
|
||||
/* enable single shot capture */
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_SINGLE_SHOT, SINGLE_SHOT_CAPTURE);
|
||||
|
||||
/* wait for syncpt counter to reach frame start event threshold */
|
||||
err = host1x_syncpt_wait(chan->frame_start_sp, thresh,
|
||||
TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value);
|
||||
if (err) {
|
||||
dev_err_ratelimited(&chan->video.dev,
|
||||
"frame start syncpt timeout: %d\n", err);
|
||||
/* increment syncpoint counter for timedout events */
|
||||
host1x_syncpt_incr(chan->frame_start_sp);
|
||||
spin_lock(&chan->sp_incr_lock);
|
||||
host1x_syncpt_incr(chan->mw_ack_sp);
|
||||
spin_unlock(&chan->sp_incr_lock);
|
||||
/* clear errors and recover */
|
||||
tegra_channel_capture_error_recover(chan);
|
||||
release_buffer(chan, buf, VB2_BUF_STATE_ERROR);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* move buffer to capture done queue */
|
||||
spin_lock(&chan->done_lock);
|
||||
list_add_tail(&buf->queue, &chan->done);
|
||||
spin_unlock(&chan->done_lock);
|
||||
|
||||
/* wait up kthread for capture done */
|
||||
wake_up_interruptible(&chan->done_wait);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_channel_capture_done(struct tegra_vi_channel *chan,
|
||||
struct tegra_channel_buffer *buf)
|
||||
{
|
||||
enum vb2_buffer_state state = VB2_BUF_STATE_DONE;
|
||||
u32 value;
|
||||
int ret;
|
||||
|
||||
/* wait for syncpt counter to reach MW_ACK_DONE event threshold */
|
||||
ret = host1x_syncpt_wait(chan->mw_ack_sp, buf->mw_ack_sp_thresh,
|
||||
TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value);
|
||||
if (ret) {
|
||||
dev_err_ratelimited(&chan->video.dev,
|
||||
"MW_ACK_DONE syncpt timeout: %d\n", ret);
|
||||
state = VB2_BUF_STATE_ERROR;
|
||||
/* increment syncpoint counter for timedout event */
|
||||
spin_lock(&chan->sp_incr_lock);
|
||||
host1x_syncpt_incr(chan->mw_ack_sp);
|
||||
spin_unlock(&chan->sp_incr_lock);
|
||||
}
|
||||
|
||||
release_buffer(chan, buf, state);
|
||||
}
|
||||
|
||||
static int chan_capture_kthread_start(void *data)
|
||||
{
|
||||
struct tegra_vi_channel *chan = data;
|
||||
struct tegra_channel_buffer *buf;
|
||||
int err = 0;
|
||||
|
||||
while (1) {
|
||||
/*
|
||||
* Source is not streaming if error is non-zero.
|
||||
* So, do not dequeue buffers on error and let the thread sleep
|
||||
* till kthread stop signal is received.
|
||||
*/
|
||||
wait_event_interruptible(chan->start_wait,
|
||||
kthread_should_stop() ||
|
||||
(!list_empty(&chan->capture) &&
|
||||
!err));
|
||||
|
||||
if (kthread_should_stop())
|
||||
break;
|
||||
|
||||
/* dequeue the buffer and start capture */
|
||||
spin_lock(&chan->start_lock);
|
||||
if (list_empty(&chan->capture)) {
|
||||
spin_unlock(&chan->start_lock);
|
||||
continue;
|
||||
}
|
||||
|
||||
buf = list_first_entry(&chan->capture,
|
||||
struct tegra_channel_buffer, queue);
|
||||
list_del_init(&buf->queue);
|
||||
spin_unlock(&chan->start_lock);
|
||||
|
||||
err = tegra_channel_capture_frame(chan, buf);
|
||||
if (err)
|
||||
vb2_queue_error(&chan->queue);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chan_capture_kthread_finish(void *data)
|
||||
{
|
||||
struct tegra_vi_channel *chan = data;
|
||||
struct tegra_channel_buffer *buf;
|
||||
|
||||
while (1) {
|
||||
wait_event_interruptible(chan->done_wait,
|
||||
!list_empty(&chan->done) ||
|
||||
kthread_should_stop());
|
||||
|
||||
/* dequeue buffers and finish capture */
|
||||
buf = dequeue_buf_done(chan);
|
||||
while (buf) {
|
||||
tegra_channel_capture_done(chan, buf);
|
||||
buf = dequeue_buf_done(chan);
|
||||
}
|
||||
|
||||
if (kthread_should_stop())
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra210_vi_start_streaming(struct vb2_queue *vq, u32 count)
|
||||
{
|
||||
struct tegra_vi_channel *chan = vb2_get_drv_priv(vq);
|
||||
struct media_pipeline *pipe = &chan->video.pipe;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, VI_CG_2ND_LEVEL_EN);
|
||||
|
||||
/* clear errors */
|
||||
val = vi_csi_read(chan, TEGRA_VI_CSI_ERROR_STATUS);
|
||||
vi_csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, val);
|
||||
|
||||
val = tegra_vi_read(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR);
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR, val);
|
||||
|
||||
/*
|
||||
* Sync point FIFO full stalls the host interface.
|
||||
* Setting NO_STALL will drop INCR_SYNCPT methods when fifos are
|
||||
* full and the corresponding condition bits in INCR_SYNCPT_ERROR
|
||||
* register will be set.
|
||||
* This allows SW to process error recovery.
|
||||
*/
|
||||
tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_CNTRL,
|
||||
VI_INCR_SYNCPT_NO_STALL);
|
||||
|
||||
/* start the pipeline */
|
||||
ret = media_pipeline_start(&chan->video.entity, pipe);
|
||||
if (ret < 0)
|
||||
goto error_pipeline_start;
|
||||
|
||||
tegra_channel_capture_setup(chan);
|
||||
ret = tegra_channel_set_stream(chan, true);
|
||||
if (ret < 0)
|
||||
goto error_set_stream;
|
||||
|
||||
chan->sequence = 0;
|
||||
|
||||
/* start kthreads to capture data to buffer and return them */
|
||||
chan->kthread_start_capture = kthread_run(chan_capture_kthread_start,
|
||||
chan, "%s:0",
|
||||
chan->video.name);
|
||||
if (IS_ERR(chan->kthread_start_capture)) {
|
||||
ret = PTR_ERR(chan->kthread_start_capture);
|
||||
chan->kthread_start_capture = NULL;
|
||||
dev_err(&chan->video.dev,
|
||||
"failed to run capture start kthread: %d\n", ret);
|
||||
goto error_kthread_start;
|
||||
}
|
||||
|
||||
chan->kthread_finish_capture = kthread_run(chan_capture_kthread_finish,
|
||||
chan, "%s:1",
|
||||
chan->video.name);
|
||||
if (IS_ERR(chan->kthread_finish_capture)) {
|
||||
ret = PTR_ERR(chan->kthread_finish_capture);
|
||||
chan->kthread_finish_capture = NULL;
|
||||
dev_err(&chan->video.dev,
|
||||
"failed to run capture finish kthread: %d\n", ret);
|
||||
goto error_kthread_done;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
error_kthread_done:
|
||||
kthread_stop(chan->kthread_start_capture);
|
||||
error_kthread_start:
|
||||
tegra_channel_set_stream(chan, false);
|
||||
error_set_stream:
|
||||
media_pipeline_stop(&chan->video.entity);
|
||||
error_pipeline_start:
|
||||
tegra_channel_release_buffers(chan, VB2_BUF_STATE_QUEUED);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void tegra210_vi_stop_streaming(struct vb2_queue *vq)
|
||||
{
|
||||
struct tegra_vi_channel *chan = vb2_get_drv_priv(vq);
|
||||
|
||||
if (chan->kthread_start_capture) {
|
||||
kthread_stop(chan->kthread_start_capture);
|
||||
chan->kthread_start_capture = NULL;
|
||||
}
|
||||
|
||||
if (chan->kthread_finish_capture) {
|
||||
kthread_stop(chan->kthread_finish_capture);
|
||||
chan->kthread_finish_capture = NULL;
|
||||
}
|
||||
|
||||
tegra_channel_release_buffers(chan, VB2_BUF_STATE_ERROR);
|
||||
tegra_channel_set_stream(chan, false);
|
||||
media_pipeline_stop(&chan->video.entity);
|
||||
}
|
||||
|
||||
/*
|
||||
* Tegra210 VI Pixel memory format enum.
|
||||
* These format enum value gets programmed into corresponding Tegra VI
|
||||
* channel register bits.
|
||||
*/
|
||||
enum tegra210_image_format {
|
||||
TEGRA210_IMAGE_FORMAT_T_L8 = 16,
|
||||
|
||||
TEGRA210_IMAGE_FORMAT_T_R16_I = 32,
|
||||
TEGRA210_IMAGE_FORMAT_T_B5G6R5,
|
||||
TEGRA210_IMAGE_FORMAT_T_R5G6B5,
|
||||
TEGRA210_IMAGE_FORMAT_T_A1B5G5R5,
|
||||
TEGRA210_IMAGE_FORMAT_T_A1R5G5B5,
|
||||
TEGRA210_IMAGE_FORMAT_T_B5G5R5A1,
|
||||
TEGRA210_IMAGE_FORMAT_T_R5G5B5A1,
|
||||
TEGRA210_IMAGE_FORMAT_T_A4B4G4R4,
|
||||
TEGRA210_IMAGE_FORMAT_T_A4R4G4B4,
|
||||
TEGRA210_IMAGE_FORMAT_T_B4G4R4A4,
|
||||
TEGRA210_IMAGE_FORMAT_T_R4G4B4A4,
|
||||
|
||||
TEGRA210_IMAGE_FORMAT_T_A8B8G8R8 = 64,
|
||||
TEGRA210_IMAGE_FORMAT_T_A8R8G8B8,
|
||||
TEGRA210_IMAGE_FORMAT_T_B8G8R8A8,
|
||||
TEGRA210_IMAGE_FORMAT_T_R8G8B8A8,
|
||||
TEGRA210_IMAGE_FORMAT_T_A2B10G10R10,
|
||||
TEGRA210_IMAGE_FORMAT_T_A2R10G10B10,
|
||||
TEGRA210_IMAGE_FORMAT_T_B10G10R10A2,
|
||||
TEGRA210_IMAGE_FORMAT_T_R10G10B10A2,
|
||||
|
||||
TEGRA210_IMAGE_FORMAT_T_A8Y8U8V8 = 193,
|
||||
TEGRA210_IMAGE_FORMAT_T_V8U8Y8A8,
|
||||
|
||||
TEGRA210_IMAGE_FORMAT_T_A2Y10U10V10 = 197,
|
||||
TEGRA210_IMAGE_FORMAT_T_V10U10Y10A2,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8_U8__Y8_V8,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8_V8__Y8_U8,
|
||||
TEGRA210_IMAGE_FORMAT_T_U8_Y8__V8_Y8,
|
||||
TEGRA210_IMAGE_FORMAT_T_V8_Y8__U8_Y8,
|
||||
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__U8__V8_N444 = 224,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__U8V8_N444,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__V8U8_N444,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__U8__V8_N422,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__U8V8_N422,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__V8U8_N422,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__U8__V8_N420,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__U8V8_N420,
|
||||
TEGRA210_IMAGE_FORMAT_T_Y8__V8U8_N420,
|
||||
TEGRA210_IMAGE_FORMAT_T_X2LC10LB10LA10,
|
||||
TEGRA210_IMAGE_FORMAT_T_A2R6R6R6R6R6,
|
||||
};
|
||||
|
||||
#define TEGRA210_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, \
|
||||
FORMAT, FOURCC) \
|
||||
{ \
|
||||
TEGRA_IMAGE_DT_##DATA_TYPE, \
|
||||
BIT_WIDTH, \
|
||||
MEDIA_BUS_FMT_##MBUS_CODE, \
|
||||
BPP, \
|
||||
TEGRA210_IMAGE_FORMAT_##FORMAT, \
|
||||
V4L2_PIX_FMT_##FOURCC, \
|
||||
}
|
||||
|
||||
/* Tegra210 supported video formats */
|
||||
static const struct tegra_video_format tegra210_video_formats[] = {
|
||||
/* RAW 8 */
|
||||
TEGRA210_VIDEO_FMT(RAW8, 8, SRGGB8_1X8, 1, T_L8, SRGGB8),
|
||||
TEGRA210_VIDEO_FMT(RAW8, 8, SGRBG8_1X8, 1, T_L8, SGRBG8),
|
||||
TEGRA210_VIDEO_FMT(RAW8, 8, SGBRG8_1X8, 1, T_L8, SGBRG8),
|
||||
TEGRA210_VIDEO_FMT(RAW8, 8, SBGGR8_1X8, 1, T_L8, SBGGR8),
|
||||
/* RAW 10 */
|
||||
TEGRA210_VIDEO_FMT(RAW10, 10, SRGGB10_1X10, 2, T_R16_I, SRGGB10),
|
||||
TEGRA210_VIDEO_FMT(RAW10, 10, SGRBG10_1X10, 2, T_R16_I, SGRBG10),
|
||||
TEGRA210_VIDEO_FMT(RAW10, 10, SGBRG10_1X10, 2, T_R16_I, SGBRG10),
|
||||
TEGRA210_VIDEO_FMT(RAW10, 10, SBGGR10_1X10, 2, T_R16_I, SBGGR10),
|
||||
/* RAW 12 */
|
||||
TEGRA210_VIDEO_FMT(RAW12, 12, SRGGB12_1X12, 2, T_R16_I, SRGGB12),
|
||||
TEGRA210_VIDEO_FMT(RAW12, 12, SGRBG12_1X12, 2, T_R16_I, SGRBG12),
|
||||
TEGRA210_VIDEO_FMT(RAW12, 12, SGBRG12_1X12, 2, T_R16_I, SGBRG12),
|
||||
TEGRA210_VIDEO_FMT(RAW12, 12, SBGGR12_1X12, 2, T_R16_I, SBGGR12),
|
||||
/* RGB888 */
|
||||
TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X24, 4, T_A8R8G8B8, RGB24),
|
||||
TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X32_PADHI, 4, T_A8B8G8R8,
|
||||
XBGR32),
|
||||
/* YUV422 */
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 2, T_U8_Y8__V8_Y8, UYVY),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 2, T_V8_Y8__U8_Y8, VYUY),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 2, T_Y8_U8__Y8_V8, YUYV),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 2, T_Y8_V8__Y8_U8, YVYU),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 1, T_Y8__V8U8_N422, NV16),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 2, T_U8_Y8__V8_Y8, UYVY),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 2, T_V8_Y8__U8_Y8, VYUY),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 2, T_Y8_U8__Y8_V8, YUYV),
|
||||
TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 2, T_Y8_V8__Y8_U8, YVYU),
|
||||
};
|
||||
|
||||
/* Tegra210 VI operations */
|
||||
static const struct tegra_vi_ops tegra210_vi_ops = {
|
||||
.vi_start_streaming = tegra210_vi_start_streaming,
|
||||
.vi_stop_streaming = tegra210_vi_stop_streaming,
|
||||
};
|
||||
|
||||
/* Tegra210 VI SoC data */
|
||||
const struct tegra_vi_soc tegra210_vi_soc = {
|
||||
.video_formats = tegra210_video_formats,
|
||||
.nformats = ARRAY_SIZE(tegra210_video_formats),
|
||||
.ops = &tegra210_vi_ops,
|
||||
.hw_revision = 3,
|
||||
.vi_max_channels = 6,
|
||||
.vi_max_clk_hz = 499200000,
|
||||
};
|
||||
|
||||
/* Tegra210 CSI PHY registers accessors */
|
||||
static void csi_write(struct tegra_csi *csi, u8 portno, unsigned int addr,
|
||||
u32 val)
|
||||
{
|
||||
void __iomem *csi_pp_base;
|
||||
|
||||
csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1);
|
||||
|
||||
writel_relaxed(val, csi_pp_base + addr);
|
||||
}
|
||||
|
||||
/* Tegra210 CSI Pixel parser registers accessors */
|
||||
static void pp_write(struct tegra_csi *csi, u8 portno, u32 addr, u32 val)
|
||||
{
|
||||
void __iomem *csi_pp_base;
|
||||
unsigned int offset;
|
||||
|
||||
csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1);
|
||||
offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET;
|
||||
|
||||
writel_relaxed(val, csi_pp_base + offset + addr);
|
||||
}
|
||||
|
||||
static u32 pp_read(struct tegra_csi *csi, u8 portno, u32 addr)
|
||||
{
|
||||
void __iomem *csi_pp_base;
|
||||
unsigned int offset;
|
||||
|
||||
csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1);
|
||||
offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET;
|
||||
|
||||
return readl_relaxed(csi_pp_base + offset + addr);
|
||||
}
|
||||
|
||||
/* Tegra210 CSI CIL A/B port registers accessors */
|
||||
static void cil_write(struct tegra_csi *csi, u8 portno, u32 addr, u32 val)
|
||||
{
|
||||
void __iomem *csi_cil_base;
|
||||
unsigned int offset;
|
||||
|
||||
csi_cil_base = csi->iomem + CSI_PP_OFFSET(portno >> 1) +
|
||||
TEGRA210_CSI_CIL_OFFSET;
|
||||
offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET;
|
||||
|
||||
writel_relaxed(val, csi_cil_base + offset + addr);
|
||||
}
|
||||
|
||||
static u32 cil_read(struct tegra_csi *csi, u8 portno, u32 addr)
|
||||
{
|
||||
void __iomem *csi_cil_base;
|
||||
unsigned int offset;
|
||||
|
||||
csi_cil_base = csi->iomem + CSI_PP_OFFSET(portno >> 1) +
|
||||
TEGRA210_CSI_CIL_OFFSET;
|
||||
offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET;
|
||||
|
||||
return readl_relaxed(csi_cil_base + offset + addr);
|
||||
}
|
||||
|
||||
/* Tegra210 CSI Test pattern generator registers accessor */
|
||||
static void tpg_write(struct tegra_csi *csi, u8 portno, unsigned int addr,
|
||||
u32 val)
|
||||
{
|
||||
void __iomem *csi_pp_base;
|
||||
unsigned int offset;
|
||||
|
||||
csi_pp_base = csi->iomem + CSI_PP_OFFSET(portno >> 1);
|
||||
offset = (portno % CSI_PORTS_PER_BRICK) * TEGRA210_CSI_PORT_OFFSET +
|
||||
TEGRA210_CSI_TPG_OFFSET;
|
||||
|
||||
writel_relaxed(val, csi_pp_base + offset + addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Tegra210 CSI operations
|
||||
*/
|
||||
static void tegra210_csi_error_recover(struct tegra_csi_channel *csi_chan)
|
||||
{
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
unsigned int portno = csi_chan->csi_port_num;
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Recover CSI hardware in case of capture errors by issuing
|
||||
* software reset to CSICIL sensor, pixel parser, and clear errors
|
||||
* to have clean capture on next streaming.
|
||||
*/
|
||||
val = pp_read(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS);
|
||||
dev_dbg(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val);
|
||||
|
||||
val = cil_read(csi, portno, TEGRA_CSI_CIL_STATUS);
|
||||
dev_dbg(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val);
|
||||
|
||||
val = cil_read(csi, portno, TEGRA_CSI_CILX_STATUS);
|
||||
dev_dbg(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val);
|
||||
|
||||
if (csi_chan->numlanes == 4) {
|
||||
/* reset CSI CIL sensor */
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x1);
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x1);
|
||||
/*
|
||||
* SW_STATUS_RESET resets all status bits of PPA, PPB, CILA,
|
||||
* CILB status registers and debug counters.
|
||||
* So, SW_STATUS_RESET can be used only when CSI brick is in
|
||||
* x4 mode.
|
||||
*/
|
||||
csi_write(csi, portno, TEGRA_CSI_CSI_SW_STATUS_RESET, 0x1);
|
||||
|
||||
/* sleep for 20 clock cycles to drain the FIFO */
|
||||
usleep_range(10, 20);
|
||||
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x0);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x0);
|
||||
csi_write(csi, portno, TEGRA_CSI_CSI_SW_STATUS_RESET, 0x0);
|
||||
} else {
|
||||
/* reset CSICIL sensor */
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x1);
|
||||
usleep_range(10, 20);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_SW_SENSOR_RESET, 0x0);
|
||||
|
||||
/* clear the errors */
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS,
|
||||
0xffffffff);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_STATUS, 0xffffffff);
|
||||
cil_write(csi, portno, TEGRA_CSI_CILX_STATUS, 0xffffffff);
|
||||
}
|
||||
}
|
||||
|
||||
static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan)
|
||||
{
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
unsigned int portno = csi_chan->csi_port_num;
|
||||
u32 val;
|
||||
|
||||
csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0);
|
||||
|
||||
/* clean up status */
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS, 0xffffffff);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_STATUS, 0xffffffff);
|
||||
cil_write(csi, portno, TEGRA_CSI_CILX_STATUS, 0xffffffff);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);
|
||||
|
||||
/* CIL PHY registers setup */
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 0xa);
|
||||
|
||||
/*
|
||||
* The CSI unit provides for connection of up to six cameras in
|
||||
* the system and is organized as three identical instances of
|
||||
* two MIPI support blocks, each with a separate 4-lane
|
||||
* interface that can be configured as a single camera with 4
|
||||
* lanes or as a dual camera with 2 lanes available for each
|
||||
* camera.
|
||||
*/
|
||||
if (csi_chan->numlanes == 4) {
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_STATUS, 0xffffffff);
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CILX_STATUS, 0xffffffff);
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);
|
||||
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0,
|
||||
BRICK_CLOCK_A_4X);
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0);
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0);
|
||||
cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 0xa);
|
||||
csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND,
|
||||
CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE);
|
||||
} else {
|
||||
val = ((portno & 1) == PORT_A) ?
|
||||
CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_NOP :
|
||||
CSI_B_PHY_CIL_ENABLE | CSI_A_PHY_CIL_NOP;
|
||||
csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, val);
|
||||
}
|
||||
|
||||
/* CSI pixel parser registers setup */
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
|
||||
(0xf << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
|
||||
CSI_PP_SINGLE_SHOT_ENABLE | CSI_PP_RST);
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_INTERRUPT_MASK, 0x0);
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_CONTROL0,
|
||||
CSI_PP_PACKET_HEADER_SENT |
|
||||
CSI_PP_DATA_IDENTIFIER_ENABLE |
|
||||
CSI_PP_WORD_COUNT_SELECT_HEADER |
|
||||
CSI_PP_CRC_CHECK_ENABLE | CSI_PP_WC_CHECK |
|
||||
CSI_PP_OUTPUT_FORMAT_STORE | CSI_PPA_PAD_LINE_NOPAD |
|
||||
CSI_PP_HEADER_EC_DISABLE | CSI_PPA_PAD_FRAME_NOPAD |
|
||||
(portno & 1));
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_CONTROL1,
|
||||
(0x1 << CSI_PP_TOP_FIELD_FRAME_OFFSET) |
|
||||
(0x1 << CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET));
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_GAP,
|
||||
0x14 << PP_FRAME_MIN_GAP_OFFSET);
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME, 0x0);
|
||||
pp_write(csi, portno, TEGRA_CSI_INPUT_STREAM_CONTROL,
|
||||
(0x3f << CSI_SKIP_PACKET_THRESHOLD_OFFSET) |
|
||||
(csi_chan->numlanes - 1));
|
||||
|
||||
/* TPG setup */
|
||||
if (csi_chan->pg_mode) {
|
||||
tpg_write(csi, portno, TEGRA_CSI_PATTERN_GENERATOR_CTRL,
|
||||
((csi_chan->pg_mode - 1) << PG_MODE_OFFSET) |
|
||||
PG_ENABLE);
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_BLANK,
|
||||
csi_chan->v_blank << PG_VBLANK_OFFSET |
|
||||
csi_chan->h_blank);
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_PHASE, 0x0);
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_RED_FREQ,
|
||||
(0x10 << PG_RED_VERT_INIT_FREQ_OFFSET) |
|
||||
(0x10 << PG_RED_HOR_INIT_FREQ_OFFSET));
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_RED_FREQ_RATE, 0x0);
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_GREEN_FREQ,
|
||||
(0x10 << PG_GREEN_VERT_INIT_FREQ_OFFSET) |
|
||||
(0x10 << PG_GREEN_HOR_INIT_FREQ_OFFSET));
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_GREEN_FREQ_RATE, 0x0);
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_BLUE_FREQ,
|
||||
(0x10 << PG_BLUE_VERT_INIT_FREQ_OFFSET) |
|
||||
(0x10 << PG_BLUE_HOR_INIT_FREQ_OFFSET));
|
||||
tpg_write(csi, portno, TEGRA_CSI_PG_BLUE_FREQ_RATE, 0x0);
|
||||
}
|
||||
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
|
||||
(0xf << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
|
||||
CSI_PP_SINGLE_SHOT_ENABLE | CSI_PP_ENABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra210_csi_stop_streaming(struct tegra_csi_channel *csi_chan)
|
||||
{
|
||||
struct tegra_csi *csi = csi_chan->csi;
|
||||
unsigned int portno = csi_chan->csi_port_num;
|
||||
u32 val;
|
||||
|
||||
val = pp_read(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS);
|
||||
|
||||
dev_dbg(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val);
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS, val);
|
||||
|
||||
val = cil_read(csi, portno, TEGRA_CSI_CIL_STATUS);
|
||||
dev_dbg(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val);
|
||||
cil_write(csi, portno, TEGRA_CSI_CIL_STATUS, val);
|
||||
|
||||
val = cil_read(csi, portno, TEGRA_CSI_CILX_STATUS);
|
||||
dev_dbg(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val);
|
||||
cil_write(csi, portno, TEGRA_CSI_CILX_STATUS, val);
|
||||
|
||||
pp_write(csi, portno, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
|
||||
(0xf << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
|
||||
CSI_PP_DISABLE);
|
||||
|
||||
if (csi_chan->pg_mode) {
|
||||
tpg_write(csi, portno, TEGRA_CSI_PATTERN_GENERATOR_CTRL,
|
||||
PG_DISABLE);
|
||||
return;
|
||||
}
|
||||
|
||||
if (csi_chan->numlanes == 4) {
|
||||
csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND,
|
||||
CSI_A_PHY_CIL_DISABLE |
|
||||
CSI_B_PHY_CIL_DISABLE);
|
||||
} else {
|
||||
val = ((portno & 1) == PORT_A) ?
|
||||
CSI_A_PHY_CIL_DISABLE | CSI_B_PHY_CIL_NOP :
|
||||
CSI_B_PHY_CIL_DISABLE | CSI_A_PHY_CIL_NOP;
|
||||
csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, val);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Tegra210 CSI TPG frame rate table with horizontal and vertical
|
||||
* blanking intervals for corresponding format and resolution.
|
||||
* Blanking intervals are tuned values from design team for max TPG
|
||||
* clock rate.
|
||||
*/
|
||||
static const struct tpg_framerate tegra210_tpg_frmrate_table[] = {
|
||||
{
|
||||
.frmsize = { 1280, 720 },
|
||||
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
|
||||
.framerate = 120,
|
||||
.h_blank = 512,
|
||||
.v_blank = 8,
|
||||
},
|
||||
{
|
||||
.frmsize = { 1920, 1080 },
|
||||
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
|
||||
.framerate = 60,
|
||||
.h_blank = 512,
|
||||
.v_blank = 8,
|
||||
},
|
||||
{
|
||||
.frmsize = { 3840, 2160 },
|
||||
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
|
||||
.framerate = 20,
|
||||
.h_blank = 8,
|
||||
.v_blank = 8,
|
||||
},
|
||||
{
|
||||
.frmsize = { 1280, 720 },
|
||||
.code = MEDIA_BUS_FMT_RGB888_1X32_PADHI,
|
||||
.framerate = 60,
|
||||
.h_blank = 512,
|
||||
.v_blank = 8,
|
||||
},
|
||||
{
|
||||
.frmsize = { 1920, 1080 },
|
||||
.code = MEDIA_BUS_FMT_RGB888_1X32_PADHI,
|
||||
.framerate = 30,
|
||||
.h_blank = 512,
|
||||
.v_blank = 8,
|
||||
},
|
||||
{
|
||||
.frmsize = { 3840, 2160 },
|
||||
.code = MEDIA_BUS_FMT_RGB888_1X32_PADHI,
|
||||
.framerate = 8,
|
||||
.h_blank = 8,
|
||||
.v_blank = 8,
|
||||
},
|
||||
};
|
||||
|
||||
static const char * const tegra210_csi_cil_clks[] = {
|
||||
"csi",
|
||||
"cilab",
|
||||
"cilcd",
|
||||
"cile",
|
||||
"csi_tpg",
|
||||
};
|
||||
|
||||
/* Tegra210 CSI operations */
|
||||
static const struct tegra_csi_ops tegra210_csi_ops = {
|
||||
.csi_start_streaming = tegra210_csi_start_streaming,
|
||||
.csi_stop_streaming = tegra210_csi_stop_streaming,
|
||||
.csi_err_recover = tegra210_csi_error_recover,
|
||||
};
|
||||
|
||||
/* Tegra210 CSI SoC data */
|
||||
const struct tegra_csi_soc tegra210_csi_soc = {
|
||||
.ops = &tegra210_csi_ops,
|
||||
.csi_max_channels = 6,
|
||||
.clk_names = tegra210_csi_cil_clks,
|
||||
.num_clks = ARRAY_SIZE(tegra210_csi_cil_clks),
|
||||
.tpg_frmrate_table = tegra210_tpg_frmrate_table,
|
||||
.tpg_frmrate_table_size = ARRAY_SIZE(tegra210_tpg_frmrate_table),
|
||||
};
|
||||
1074
drivers/staging/media/tegra-video/vi.c
Normal file
1074
drivers/staging/media/tegra-video/vi.c
Normal file
File diff suppressed because it is too large
Load Diff
257
drivers/staging/media/tegra-video/vi.h
Normal file
257
drivers/staging/media/tegra-video/vi.h
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA_VI_H__
|
||||
#define __TEGRA_VI_H__
|
||||
|
||||
#include <linux/host1x.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/wait.h>
|
||||
|
||||
#include <media/media-entity.h>
|
||||
#include <media/v4l2-ctrls.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/v4l2-dev.h>
|
||||
#include <media/v4l2-subdev.h>
|
||||
#include <media/videobuf2-v4l2.h>
|
||||
|
||||
#define TEGRA_MIN_WIDTH 32U
|
||||
#define TEGRA_MAX_WIDTH 32768U
|
||||
#define TEGRA_MIN_HEIGHT 32U
|
||||
#define TEGRA_MAX_HEIGHT 32768U
|
||||
|
||||
#define TEGRA_DEF_WIDTH 1920
|
||||
#define TEGRA_DEF_HEIGHT 1080
|
||||
#define TEGRA_IMAGE_FORMAT_DEF 32
|
||||
|
||||
#define MAX_FORMAT_NUM 64
|
||||
|
||||
enum tegra_vi_pg_mode {
|
||||
TEGRA_VI_PG_DISABLED = 0,
|
||||
TEGRA_VI_PG_DIRECT,
|
||||
TEGRA_VI_PG_PATCH,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_vi_ops - Tegra VI operations
|
||||
* @vi_start_streaming: starts media pipeline, subdevice streaming, sets up
|
||||
* VI for capture and runs capture start and capture finish
|
||||
* kthreads for capturing frames to buffer and returns them back.
|
||||
* @vi_stop_streaming: stops media pipeline and subdevice streaming and returns
|
||||
* back any queued buffers.
|
||||
*/
|
||||
struct tegra_vi_ops {
|
||||
int (*vi_start_streaming)(struct vb2_queue *vq, u32 count);
|
||||
void (*vi_stop_streaming)(struct vb2_queue *vq);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_vi_soc - NVIDIA Tegra Video Input SoC structure
|
||||
*
|
||||
* @video_formats: supported video formats
|
||||
* @nformats: total video formats
|
||||
* @ops: vi operations
|
||||
* @hw_revision: VI hw_revision
|
||||
* @vi_max_channels: supported max streaming channels
|
||||
* @vi_max_clk_hz: VI clock max frequency
|
||||
*/
|
||||
struct tegra_vi_soc {
|
||||
const struct tegra_video_format *video_formats;
|
||||
const unsigned int nformats;
|
||||
const struct tegra_vi_ops *ops;
|
||||
u32 hw_revision;
|
||||
unsigned int vi_max_channels;
|
||||
unsigned int vi_max_clk_hz;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_vi - NVIDIA Tegra Video Input device structure
|
||||
*
|
||||
* @dev: device struct
|
||||
* @client: host1x_client struct
|
||||
* @iomem: register base
|
||||
* @clk: main clock for VI block
|
||||
* @vdd: vdd regulator for VI hardware, normally it is avdd_dsi_csi
|
||||
* @soc: pointer to SoC data structure
|
||||
* @ops: vi operations
|
||||
* @vi_chans: list head for VI channels
|
||||
*/
|
||||
struct tegra_vi {
|
||||
struct device *dev;
|
||||
struct host1x_client client;
|
||||
void __iomem *iomem;
|
||||
struct clk *clk;
|
||||
struct regulator *vdd;
|
||||
const struct tegra_vi_soc *soc;
|
||||
const struct tegra_vi_ops *ops;
|
||||
struct list_head vi_chans;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_vi_channel - Tegra video channel
|
||||
*
|
||||
* @list: list head for this entry
|
||||
* @video: V4L2 video device associated with the video channel
|
||||
* @video_lock: protects the @format and @queue fields
|
||||
* @pad: media pad for the video device entity
|
||||
*
|
||||
* @vi: Tegra video input device structure
|
||||
* @frame_start_sp: host1x syncpoint pointer to synchronize programmed capture
|
||||
* start condition with hardware frame start events through host1x
|
||||
* syncpoint counters.
|
||||
* @mw_ack_sp: host1x syncpoint pointer to synchronize programmed memory write
|
||||
* ack trigger condition with hardware memory write done at end of
|
||||
* frame through host1x syncpoint counters.
|
||||
* @sp_incr_lock: protects cpu syncpoint increment.
|
||||
*
|
||||
* @kthread_start_capture: kthread to start capture of single frame when
|
||||
* vb buffer is available. This thread programs VI CSI hardware
|
||||
* for single frame capture and waits for frame start event from
|
||||
* the hardware. On receiving frame start event, it wakes up
|
||||
* kthread_finish_capture thread to wait for finishing frame data
|
||||
* write to the memory. In case of missing frame start event, this
|
||||
* thread returns buffer back to vb with VB2_BUF_STATE_ERROR.
|
||||
* @start_wait: waitqueue for starting frame capture when buffer is available.
|
||||
* @kthread_finish_capture: kthread to finish the buffer capture and return to.
|
||||
* This thread is woken up by kthread_start_capture on receiving
|
||||
* frame start event from the hardware and this thread waits for
|
||||
* MW_ACK_DONE event which indicates completion of writing frame
|
||||
* data to the memory. On receiving MW_ACK_DONE event, buffer is
|
||||
* returned back to vb with VB2_BUF_STATE_DONE and in case of
|
||||
* missing MW_ACK_DONE event, buffer is returned back to vb with
|
||||
* VB2_BUF_STATE_ERROR.
|
||||
* @done_wait: waitqueue for finishing capture data writes to memory.
|
||||
*
|
||||
* @format: active V4L2 pixel format
|
||||
* @fmtinfo: format information corresponding to the active @format
|
||||
* @queue: vb2 buffers queue
|
||||
* @sequence: V4L2 buffers sequence number
|
||||
*
|
||||
* @capture: list of queued buffers for capture
|
||||
* @start_lock: protects the capture queued list
|
||||
* @done: list of capture done queued buffers
|
||||
* @done_lock: protects the capture done queue list
|
||||
*
|
||||
* @portno: VI channel port number
|
||||
*
|
||||
* @ctrl_handler: V4L2 control handler of this video channel
|
||||
* @tpg_fmts_bitmap: a bitmap for supported TPG formats
|
||||
* @pg_mode: test pattern generator mode (disabled/direct/patch)
|
||||
*/
|
||||
struct tegra_vi_channel {
|
||||
struct list_head list;
|
||||
struct video_device video;
|
||||
/* protects the @format and @queue fields */
|
||||
struct mutex video_lock;
|
||||
struct media_pad pad;
|
||||
|
||||
struct tegra_vi *vi;
|
||||
struct host1x_syncpt *frame_start_sp;
|
||||
struct host1x_syncpt *mw_ack_sp;
|
||||
/* protects the cpu syncpoint increment */
|
||||
spinlock_t sp_incr_lock;
|
||||
|
||||
struct task_struct *kthread_start_capture;
|
||||
wait_queue_head_t start_wait;
|
||||
struct task_struct *kthread_finish_capture;
|
||||
wait_queue_head_t done_wait;
|
||||
|
||||
struct v4l2_pix_format format;
|
||||
const struct tegra_video_format *fmtinfo;
|
||||
struct vb2_queue queue;
|
||||
u32 sequence;
|
||||
|
||||
struct list_head capture;
|
||||
/* protects the capture queued list */
|
||||
spinlock_t start_lock;
|
||||
struct list_head done;
|
||||
/* protects the capture done queue list */
|
||||
spinlock_t done_lock;
|
||||
|
||||
unsigned char portno;
|
||||
|
||||
struct v4l2_ctrl_handler ctrl_handler;
|
||||
DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM);
|
||||
enum tegra_vi_pg_mode pg_mode;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_channel_buffer - video channel buffer
|
||||
*
|
||||
* @buf: vb2 buffer base object
|
||||
* @queue: buffer list entry in the channel queued buffers list
|
||||
* @chan: channel that uses the buffer
|
||||
* @addr: Tegra IOVA buffer address for VI output
|
||||
* @mw_ack_sp_thresh: MW_ACK_DONE syncpoint threshold corresponding
|
||||
* to the capture buffer.
|
||||
*/
|
||||
struct tegra_channel_buffer {
|
||||
struct vb2_v4l2_buffer buf;
|
||||
struct list_head queue;
|
||||
struct tegra_vi_channel *chan;
|
||||
dma_addr_t addr;
|
||||
u32 mw_ack_sp_thresh;
|
||||
};
|
||||
|
||||
/*
|
||||
* VI channel input data type enum.
|
||||
* These data type enum value gets programmed into corresponding Tegra VI
|
||||
* channel register bits.
|
||||
*/
|
||||
enum tegra_image_dt {
|
||||
TEGRA_IMAGE_DT_YUV420_8 = 24,
|
||||
TEGRA_IMAGE_DT_YUV420_10,
|
||||
|
||||
TEGRA_IMAGE_DT_YUV420CSPS_8 = 28,
|
||||
TEGRA_IMAGE_DT_YUV420CSPS_10,
|
||||
TEGRA_IMAGE_DT_YUV422_8,
|
||||
TEGRA_IMAGE_DT_YUV422_10,
|
||||
TEGRA_IMAGE_DT_RGB444,
|
||||
TEGRA_IMAGE_DT_RGB555,
|
||||
TEGRA_IMAGE_DT_RGB565,
|
||||
TEGRA_IMAGE_DT_RGB666,
|
||||
TEGRA_IMAGE_DT_RGB888,
|
||||
|
||||
TEGRA_IMAGE_DT_RAW6 = 40,
|
||||
TEGRA_IMAGE_DT_RAW7,
|
||||
TEGRA_IMAGE_DT_RAW8,
|
||||
TEGRA_IMAGE_DT_RAW10,
|
||||
TEGRA_IMAGE_DT_RAW12,
|
||||
TEGRA_IMAGE_DT_RAW14,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tegra_video_format - Tegra video format description
|
||||
*
|
||||
* @img_dt: image data type
|
||||
* @bit_width: format width in bits per component
|
||||
* @code: media bus format code
|
||||
* @bpp: bytes per pixel (when stored in memory)
|
||||
* @img_fmt: image format
|
||||
* @fourcc: V4L2 pixel format FCC identifier
|
||||
*/
|
||||
struct tegra_video_format {
|
||||
enum tegra_image_dt img_dt;
|
||||
unsigned int bit_width;
|
||||
unsigned int code;
|
||||
unsigned int bpp;
|
||||
u32 img_fmt;
|
||||
u32 fourcc;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
extern const struct tegra_vi_soc tegra210_vi_soc;
|
||||
#endif
|
||||
|
||||
struct v4l2_subdev *
|
||||
tegra_channel_get_remote_subdev(struct tegra_vi_channel *chan);
|
||||
int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on);
|
||||
void tegra_channel_release_buffers(struct tegra_vi_channel *chan,
|
||||
enum vb2_buffer_state state);
|
||||
void tegra_channels_cleanup(struct tegra_vi *vi);
|
||||
#endif
|
||||
155
drivers/staging/media/tegra-video/video.c
Normal file
155
drivers/staging/media/tegra-video/video.c
Normal file
|
|
@ -0,0 +1,155 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/host1x.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "video.h"
|
||||
|
||||
static void tegra_v4l2_dev_release(struct v4l2_device *v4l2_dev)
|
||||
{
|
||||
struct tegra_video_device *vid;
|
||||
|
||||
vid = container_of(v4l2_dev, struct tegra_video_device, v4l2_dev);
|
||||
|
||||
/* cleanup channels here as all video device nodes are released */
|
||||
tegra_channels_cleanup(vid->vi);
|
||||
|
||||
v4l2_device_unregister(v4l2_dev);
|
||||
media_device_unregister(&vid->media_dev);
|
||||
media_device_cleanup(&vid->media_dev);
|
||||
kfree(vid);
|
||||
}
|
||||
|
||||
static int host1x_video_probe(struct host1x_device *dev)
|
||||
{
|
||||
struct tegra_video_device *vid;
|
||||
int ret;
|
||||
|
||||
vid = kzalloc(sizeof(*vid), GFP_KERNEL);
|
||||
if (!vid)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(&dev->dev, vid);
|
||||
|
||||
vid->media_dev.dev = &dev->dev;
|
||||
strscpy(vid->media_dev.model, "NVIDIA Tegra Video Input Device",
|
||||
sizeof(vid->media_dev.model));
|
||||
|
||||
media_device_init(&vid->media_dev);
|
||||
ret = media_device_register(&vid->media_dev);
|
||||
if (ret < 0) {
|
||||
dev_err(&dev->dev,
|
||||
"failed to register media device: %d\n", ret);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
vid->v4l2_dev.mdev = &vid->media_dev;
|
||||
vid->v4l2_dev.release = tegra_v4l2_dev_release;
|
||||
ret = v4l2_device_register(&dev->dev, &vid->v4l2_dev);
|
||||
if (ret < 0) {
|
||||
dev_err(&dev->dev,
|
||||
"V4L2 device registration failed: %d\n", ret);
|
||||
goto unregister_media;
|
||||
}
|
||||
|
||||
ret = host1x_device_init(dev);
|
||||
if (ret < 0)
|
||||
goto unregister_v4l2;
|
||||
|
||||
/*
|
||||
* Both vi and csi channels are available now.
|
||||
* Register v4l2 nodes and create media links for TPG.
|
||||
*/
|
||||
ret = tegra_v4l2_nodes_setup_tpg(vid);
|
||||
if (ret < 0) {
|
||||
dev_err(&dev->dev,
|
||||
"failed to setup tpg graph: %d\n", ret);
|
||||
goto device_exit;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
device_exit:
|
||||
host1x_device_exit(dev);
|
||||
/* vi exit ops does not clean channels, so clean them here */
|
||||
tegra_channels_cleanup(vid->vi);
|
||||
unregister_v4l2:
|
||||
v4l2_device_unregister(&vid->v4l2_dev);
|
||||
unregister_media:
|
||||
media_device_unregister(&vid->media_dev);
|
||||
cleanup:
|
||||
media_device_cleanup(&vid->media_dev);
|
||||
kfree(vid);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int host1x_video_remove(struct host1x_device *dev)
|
||||
{
|
||||
struct tegra_video_device *vid = dev_get_drvdata(&dev->dev);
|
||||
|
||||
tegra_v4l2_nodes_cleanup_tpg(vid);
|
||||
|
||||
host1x_device_exit(dev);
|
||||
|
||||
/* This calls v4l2_dev release callback on last reference */
|
||||
v4l2_device_put(&vid->v4l2_dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id host1x_video_subdevs[] = {
|
||||
#if defined(CONFIG_ARCH_TEGRA_210_SOC)
|
||||
{ .compatible = "nvidia,tegra210-csi", },
|
||||
{ .compatible = "nvidia,tegra210-vi", },
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct host1x_driver host1x_video_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-video",
|
||||
},
|
||||
.probe = host1x_video_probe,
|
||||
.remove = host1x_video_remove,
|
||||
.subdevs = host1x_video_subdevs,
|
||||
};
|
||||
|
||||
static struct platform_driver * const drivers[] = {
|
||||
&tegra_csi_driver,
|
||||
&tegra_vi_driver,
|
||||
};
|
||||
|
||||
static int __init host1x_video_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = host1x_driver_register(&host1x_video_driver);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
||||
if (err < 0)
|
||||
goto unregister_host1x;
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_host1x:
|
||||
host1x_driver_unregister(&host1x_video_driver);
|
||||
return err;
|
||||
}
|
||||
module_init(host1x_video_init);
|
||||
|
||||
static void __exit host1x_video_exit(void)
|
||||
{
|
||||
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
||||
host1x_driver_unregister(&host1x_video_driver);
|
||||
}
|
||||
module_exit(host1x_video_exit);
|
||||
|
||||
MODULE_AUTHOR("Sowjanya Komatineni <skomatineni@nvidia.com>");
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra Host1x Video driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
29
drivers/staging/media/tegra-video/video.h
Normal file
29
drivers/staging/media/tegra-video/video.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA_VIDEO_H__
|
||||
#define __TEGRA_VIDEO_H__
|
||||
|
||||
#include <linux/host1x.h>
|
||||
|
||||
#include <media/media-device.h>
|
||||
#include <media/v4l2-device.h>
|
||||
|
||||
#include "vi.h"
|
||||
#include "csi.h"
|
||||
|
||||
struct tegra_video_device {
|
||||
struct v4l2_device v4l2_dev;
|
||||
struct media_device media_dev;
|
||||
struct tegra_vi *vi;
|
||||
struct tegra_csi *csi;
|
||||
};
|
||||
|
||||
int tegra_v4l2_nodes_setup_tpg(struct tegra_video_device *vid);
|
||||
void tegra_v4l2_nodes_cleanup_tpg(struct tegra_video_device *vid);
|
||||
|
||||
extern struct platform_driver tegra_vi_driver;
|
||||
extern struct platform_driver tegra_csi_driver;
|
||||
#endif
|
||||
|
|
@ -272,10 +272,10 @@
|
|||
#define TEGRA114_CLK_AUDIO3 242
|
||||
#define TEGRA114_CLK_AUDIO4 243
|
||||
#define TEGRA114_CLK_SPDIF 244
|
||||
#define TEGRA114_CLK_CLK_OUT_1 245
|
||||
#define TEGRA114_CLK_CLK_OUT_2 246
|
||||
#define TEGRA114_CLK_CLK_OUT_3 247
|
||||
#define TEGRA114_CLK_BLINK 248
|
||||
/* 245 */
|
||||
/* 246 */
|
||||
/* 247 */
|
||||
/* 248 */
|
||||
#define TEGRA114_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
|
|
@ -335,9 +335,9 @@
|
|||
#define TEGRA114_CLK_AUDIO3_MUX 303
|
||||
#define TEGRA114_CLK_AUDIO4_MUX 304
|
||||
#define TEGRA114_CLK_SPDIF_MUX 305
|
||||
#define TEGRA114_CLK_CLK_OUT_1_MUX 306
|
||||
#define TEGRA114_CLK_CLK_OUT_2_MUX 307
|
||||
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
|
||||
/* 306 */
|
||||
/* 307 */
|
||||
/* 308 */
|
||||
#define TEGRA114_CLK_DSIA_MUX 309
|
||||
#define TEGRA114_CLK_DSIB_MUX 310
|
||||
#define TEGRA114_CLK_XUSB_SS_DIV2 311
|
||||
|
|
|
|||
|
|
@ -271,10 +271,10 @@
|
|||
#define TEGRA124_CLK_AUDIO3 242
|
||||
#define TEGRA124_CLK_AUDIO4 243
|
||||
#define TEGRA124_CLK_SPDIF 244
|
||||
#define TEGRA124_CLK_CLK_OUT_1 245
|
||||
#define TEGRA124_CLK_CLK_OUT_2 246
|
||||
#define TEGRA124_CLK_CLK_OUT_3 247
|
||||
#define TEGRA124_CLK_BLINK 248
|
||||
/* 245 */
|
||||
/* 246 */
|
||||
/* 247 */
|
||||
/* 248 */
|
||||
#define TEGRA124_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
|
|
@ -334,9 +334,9 @@
|
|||
#define TEGRA124_CLK_AUDIO3_MUX 303
|
||||
#define TEGRA124_CLK_AUDIO4_MUX 304
|
||||
#define TEGRA124_CLK_SPDIF_MUX 305
|
||||
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
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#define TEGRA124_CLK_CLK_OUT_2_MUX 307
|
||||
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
|
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/* 306 */
|
||||
/* 307 */
|
||||
/* 308 */
|
||||
/* 309 */
|
||||
/* 310 */
|
||||
#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@
|
|||
#define TEGRA20_CLK_CCLK 108
|
||||
#define TEGRA20_CLK_HCLK 109
|
||||
#define TEGRA20_CLK_PCLK 110
|
||||
#define TEGRA20_CLK_BLINK 111
|
||||
/* 111 */
|
||||
#define TEGRA20_CLK_PLL_A 112
|
||||
#define TEGRA20_CLK_PLL_A_OUT0 113
|
||||
#define TEGRA20_CLK_PLL_C 114
|
||||
|
|
|
|||
|
|
@ -306,10 +306,10 @@
|
|||
#define TEGRA210_CLK_AUDIO3 274
|
||||
#define TEGRA210_CLK_AUDIO4 275
|
||||
#define TEGRA210_CLK_SPDIF 276
|
||||
#define TEGRA210_CLK_CLK_OUT_1 277
|
||||
#define TEGRA210_CLK_CLK_OUT_2 278
|
||||
#define TEGRA210_CLK_CLK_OUT_3 279
|
||||
#define TEGRA210_CLK_BLINK 280
|
||||
/* 277 */
|
||||
/* 278 */
|
||||
/* 279 */
|
||||
/* 280 */
|
||||
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
|
||||
#define TEGRA210_CLK_SOR0_OUT 281
|
||||
#define TEGRA210_CLK_SOR1_OUT 282
|
||||
|
|
@ -358,7 +358,7 @@
|
|||
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
|
||||
/* 325 */
|
||||
#define TEGRA210_CLK_OSC 326
|
||||
/* 327 */
|
||||
#define TEGRA210_CLK_CSI_TPG 327
|
||||
/* 328 */
|
||||
/* 329 */
|
||||
/* 330 */
|
||||
|
|
@ -388,9 +388,9 @@
|
|||
#define TEGRA210_CLK_AUDIO3_MUX 353
|
||||
#define TEGRA210_CLK_AUDIO4_MUX 354
|
||||
#define TEGRA210_CLK_SPDIF_MUX 355
|
||||
#define TEGRA210_CLK_CLK_OUT_1_MUX 356
|
||||
#define TEGRA210_CLK_CLK_OUT_2_MUX 357
|
||||
#define TEGRA210_CLK_CLK_OUT_3_MUX 358
|
||||
/* 356 */
|
||||
/* 357 */
|
||||
/* 358 */
|
||||
#define TEGRA210_CLK_DSIA_MUX 359
|
||||
#define TEGRA210_CLK_DSIB_MUX 360
|
||||
/* 361 */
|
||||
|
|
|
|||
|
|
@ -232,11 +232,11 @@
|
|||
#define TEGRA30_CLK_AUDIO3 204
|
||||
#define TEGRA30_CLK_AUDIO4 205
|
||||
#define TEGRA30_CLK_SPDIF 206
|
||||
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
|
||||
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
|
||||
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
|
||||
/* 207 */
|
||||
/* 208 */
|
||||
/* 209 */
|
||||
#define TEGRA30_CLK_SCLK 210
|
||||
#define TEGRA30_CLK_BLINK 211
|
||||
/* 211 */
|
||||
#define TEGRA30_CLK_CCLK_G 212
|
||||
#define TEGRA30_CLK_CCLK_LP 213
|
||||
#define TEGRA30_CLK_TWD 214
|
||||
|
|
@ -262,9 +262,9 @@
|
|||
/* 297 */
|
||||
/* 298 */
|
||||
/* 299 */
|
||||
#define TEGRA30_CLK_CLK_OUT_1_MUX 300
|
||||
#define TEGRA30_CLK_CLK_OUT_2_MUX 301
|
||||
#define TEGRA30_CLK_CLK_OUT_3_MUX 302
|
||||
/* 300 */
|
||||
/* 301 */
|
||||
/* 302 */
|
||||
#define TEGRA30_CLK_AUDIO0_MUX 303
|
||||
#define TEGRA30_CLK_AUDIO1_MUX 304
|
||||
#define TEGRA30_CLK_AUDIO2_MUX 305
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user