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Realtek ARM64 based SoC DT for v5.5

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Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
 Add reset controllers for RTD129x and start using them for UARTs.
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Merge tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek into arm/dt

Realtek ARM64 based SoC DT for v5.5

Add RTD1293 and RTD1296 DTs. Add the watchdog for all of RTD129x DTs.
Add reset controllers for RTD129x and start using them for UARTs.

* tag 'realtek-arm64-dt-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek:
  arm64: dts: realtek: Add RTD129x UART resets
  arm64: dts: realtek: Add RTD129x reset controller nodes
  dt-bindings: reset: Add Realtek RTD1295
  arm64: dts: realtek: Add watchdog node for RTD129x
  arm64: dts: realtek: Add oscillator for RTD129x
  arm64: dts: realtek: Add RTD1296 and Synology DS418
  dt-bindings: arm: realtek: Document RTD1296 and Synology DS418
  arm64: dts: realtek: Add RTD1293 and Synology DS418j
  arm64: dts: realtek: Change dual-license from MIT to BSD
  dt-bindings: arm: realtek: Document RTD1293 and Synology DS418j
  dt-bindings: arm: realtek: Tidy up conversion to json-schema

Link: https://lore.kernel.org/r/20191030041000.31848-2-afaerber@suse.de
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-03 16:54:32 -08:00
commit a1094a7c27
10 changed files with 362 additions and 13 deletions
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27
Documentation/devicetree/bindings/arm/realtek.yaml
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@ -13,11 +13,24 @@ properties:
$nodename:
const: '/'
compatible:
# RTD1295 SoC based boards
items:
- enum:
- mele,v9
- probox2,ava
- zidoo,x9s
- const: realtek,rtd1295
oneOf:
# RTD1293 SoC based boards
- items:
- enum:
- synology,ds418j # Synology DiskStation DS418j
- const: realtek,rtd1293
# RTD1295 SoC based boards
- items:
- enum:
- mele,v9 # MeLE V9
- probox2,ava # ProBox2 AVA
- zidoo,x9s # Zidoo X9S
- const: realtek,rtd1295
# RTD1296 SoC based boards
- items:
- enum:
- synology,ds418 # Synology DiskStation DS418
- const: realtek,rtd1296
...

5
arch/arm64/boot/dts/realtek/Makefile
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@ -1,4 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb

30
arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2017 Andreas Färber
*/
/dts-v1/;
#include "rtd1293.dtsi"
/ {
compatible = "synology,ds418j", "realtek,rtd1293";
model = "Synology DiskStation DS418j";
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};

51
arch/arm64/boot/dts/realtek/rtd1293.dtsi Normal file
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@ -0,0 +1,51 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1293 SoC
*
* Copyright (c) 2017-2019 Andreas Färber
*/
#include "rtd129x.dtsi"
/ {
compatible = "realtek,rtd1293";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};

3
arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts
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@ -1,7 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2016-2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;

3
arch/arm64/boot/dts/realtek/rtd1295.dtsi
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@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1295 SoC
*
* Copyright (c) 2016-2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include "rtd129x.dtsi"

30
arch/arm64/boot/dts/realtek/rtd1296-ds418.dts Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2017-2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1296.dtsi"
/ {
compatible = "synology,ds418", "realtek,rtd1296";
model = "Synology DiskStation DS418";
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};

65
arch/arm64/boot/dts/realtek/rtd1296.dtsi Normal file
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@ -0,0 +1,65 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1296 SoC
*
* Copyright (c) 2017-2019 Andreas Färber
*/
#include "rtd129x.dtsi"
/ {
compatible = "realtek,rtd1296";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};

50
arch/arm64/boot/dts/realtek/rtd129x.dtsi
View File

@ -1,9 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1293/RTD1295/RTD1296 SoC
*
* Copyright (c) 2016-2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/memreserve/ 0x0000000000000000 0x0000000000030000;
@ -13,6 +12,7 @@
/memreserve/ 0x0000000001ffe000 0x0000000000004000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/realtek,rtd1295.h>
/ {
interrupt-parent = <&gic>;
@ -24,6 +24,13 @@ arm_pmu: arm-pmu {
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
osc27M: osc {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
clock-output-names = "osc27M";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -31,12 +38,49 @@ soc {
/* Exclude up to 2 GiB of RAM */
ranges = <0x80000000 0x80000000 0x80000000>;
reset1: reset-controller@98000000 {
compatible = "snps,dw-low-reset";
reg = <0x98000000 0x4>;
#reset-cells = <1>;
};
reset2: reset-controller@98000004 {
compatible = "snps,dw-low-reset";
reg = <0x98000004 0x4>;
#reset-cells = <1>;
};
reset3: reset-controller@98000008 {
compatible = "snps,dw-low-reset";
reg = <0x98000008 0x4>;
#reset-cells = <1>;
};
reset4: reset-controller@98000050 {
compatible = "snps,dw-low-reset";
reg = <0x98000050 0x4>;
#reset-cells = <1>;
};
iso_reset: reset-controller@98007088 {
compatible = "snps,dw-low-reset";
reg = <0x98007088 0x4>;
#reset-cells = <1>;
};
wdt: watchdog@98007680 {
compatible = "realtek,rtd1295-watchdog";
reg = <0x98007680 0x100>;
clocks = <&osc27M>;
};
uart0: serial@98007800 {
compatible = "snps,dw-apb-uart";
reg = <0x98007800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
status = "disabled";
};
@ -46,6 +90,7 @@ uart1: serial@9801b200 {
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR1>;
status = "disabled";
};
@ -55,6 +100,7 @@ uart2: serial@9801b400 {
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR2>;
status = "disabled";
};

111
include/dt-bindings/reset/realtek,rtd1295.h Normal file
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@ -0,0 +1,111 @@
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
/*
* Realtek RTD1295 reset controllers
*
* Copyright (c) 2017 Andreas Färber
*/
#ifndef DT_BINDINGS_RESET_RTD1295_H
#define DT_BINDINGS_RESET_RTD1295_H
/* soft reset 1 */
#define RTD1295_RSTN_MISC 0
#define RTD1295_RSTN_NAT 1
#define RTD1295_RSTN_USB3_PHY0_POW 2
#define RTD1295_RSTN_GSPI 3
#define RTD1295_RSTN_USB3_P0_MDIO 4
#define RTD1295_RSTN_SATA_0 5
#define RTD1295_RSTN_USB 6
#define RTD1295_RSTN_SATA_PHY_0 7
#define RTD1295_RSTN_USB_PHY0 8
#define RTD1295_RSTN_USB_PHY1 9
#define RTD1295_RSTN_SATA_PHY_POW_0 10
#define RTD1295_RSTN_SATA_FUNC_EXIST_0 11
#define RTD1295_RSTN_HDMI 12
#define RTD1295_RSTN_VE1 13
#define RTD1295_RSTN_VE2 14
#define RTD1295_RSTN_VE3 15
#define RTD1295_RSTN_ETN 16
#define RTD1295_RSTN_AIO 17
#define RTD1295_RSTN_GPU 18
#define RTD1295_RSTN_TVE 19
#define RTD1295_RSTN_VO 20
#define RTD1295_RSTN_LVDS 21
#define RTD1295_RSTN_SE 22
#define RTD1295_RSTN_DCU 23
#define RTD1295_RSTN_DC_PHY 24
#define RTD1295_RSTN_CP 25
#define RTD1295_RSTN_MD 26
#define RTD1295_RSTN_TP 27
#define RTD1295_RSTN_AE 28
#define RTD1295_RSTN_NF 29
#define RTD1295_RSTN_MIPI 30
#define RTD1295_RSTN_RSA 31
/* soft reset 2 */
#define RTD1295_RSTN_ACPU 0
#define RTD1295_RSTN_JPEG 1
#define RTD1295_RSTN_USB_PHY3 2
#define RTD1295_RSTN_USB_PHY2 3
#define RTD1295_RSTN_USB3_PHY1_POW 4
#define RTD1295_RSTN_USB3_P1_MDIO 5
#define RTD1295_RSTN_PCIE0_STITCH 6
#define RTD1295_RSTN_PCIE0_PHY 7
#define RTD1295_RSTN_PCIE0 8
#define RTD1295_RSTN_PCR_CNT 9
#define RTD1295_RSTN_CR 10
#define RTD1295_RSTN_EMMC 11
#define RTD1295_RSTN_SDIO 12
#define RTD1295_RSTN_PCIE0_CORE 13
#define RTD1295_RSTN_PCIE0_POWER 14
#define RTD1295_RSTN_PCIE0_NONSTICH 15
#define RTD1295_RSTN_PCIE1_PHY 16
#define RTD1295_RSTN_PCIE1 17
#define RTD1295_RSTN_I2C_5 18
#define RTD1295_RSTN_PCIE1_STITCH 19
#define RTD1295_RSTN_PCIE1_CORE 20
#define RTD1295_RSTN_PCIE1_POWER 21
#define RTD1295_RSTN_PCIE1_NONSTICH 22
#define RTD1295_RSTN_I2C_4 23
#define RTD1295_RSTN_I2C_3 24
#define RTD1295_RSTN_I2C_2 25
#define RTD1295_RSTN_I2C_1 26
#define RTD1295_RSTN_UR2 27
#define RTD1295_RSTN_UR1 28
#define RTD1295_RSTN_MISC_SC 29
#define RTD1295_RSTN_CBUS_TX 30
#define RTD1295_RSTN_SDS_PHY 31
/* soft reset 4 */
#define RTD1295_RSTN_DCPHY_CRT 0
#define RTD1295_RSTN_DCPHY_ALERT_RX 1
#define RTD1295_RSTN_DCPHY_PTR 2
#define RTD1295_RSTN_DCPHY_LDO 3
#define RTD1295_RSTN_DCPHY_SSC_DIG 4
#define RTD1295_RSTN_HDMIRX 5
#define RTD1295_RSTN_CBUSRX 6
#define RTD1295_RSTN_SATA_PHY_POW_1 7
#define RTD1295_RSTN_SATA_FUNC_EXIST_1 8
#define RTD1295_RSTN_SATA_PHY_1 9
#define RTD1295_RSTN_SATA_1 10
#define RTD1295_RSTN_FAN 11
#define RTD1295_RSTN_HDMIRX_WRAP 12
#define RTD1295_RSTN_PCIE0_PHY_MDIO 13
#define RTD1295_RSTN_PCIE1_PHY_MDIO 14
#define RTD1295_RSTN_DISP 15
/* iso reset */
#define RTD1295_ISO_RSTN_IR 1
#define RTD1295_ISO_RSTN_CEC0 2
#define RTD1295_ISO_RSTN_CEC1 3
#define RTD1295_ISO_RSTN_DP 4
#define RTD1295_ISO_RSTN_CBUSTX 5
#define RTD1295_ISO_RSTN_CBUSRX 6
#define RTD1295_ISO_RSTN_EFUSE 7
#define RTD1295_ISO_RSTN_UR0 8
#define RTD1295_ISO_RSTN_GMAC 9
#define RTD1295_ISO_RSTN_GPHY 10
#define RTD1295_ISO_RSTN_I2C_0 11
#define RTD1295_ISO_RSTN_I2C_1 12
#define RTD1295_ISO_RSTN_CBUS 13
#endif