forked from luck/tmp_suning_uos_patched
Marvell Ethernet driver fix + clk support
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEABECAAYFAlCsAOYACgkQ9lPLMJjT96eCqQCffyg9LHzmTC74je1RdaVNDbdl zHMAn0I3VvirlsRHK6dQBmvNyAZMHvxT =v9GL -----END PGP SIGNATURE----- Merge tag 'marvell-mvneta-fix-and-clk-support-3.8' of github.com:MISL-EBU-System-SW/mainline-public into test-the-merge Marvell Ethernet driver fix + clk support
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a19aab5792
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@ -8,7 +8,7 @@ Required properties:
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property, a single integer).
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- phy-mode: The interface between the SoC and the PHY (a string that
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of_get_phy_mode() can understand)
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- clock-frequency: frequency of the peripheral clock of the SoC.
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- clocks: a pointer to the reference clock for this device.
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Example:
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@ -16,7 +16,7 @@ ethernet@d0070000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0070000 0x2500>;
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interrupts = <8>;
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clock-frequency = <250000000>;
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clocks = <&gate_clk 4>;
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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@ -29,6 +29,7 @@
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#include <linux/of_net.h>
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#include <linux/of_address.h>
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#include <linux/phy.h>
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#include <linux/clk.h>
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/* Registers */
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#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
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@ -242,7 +243,7 @@ struct mvneta_port {
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int weight;
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/* Core clock */
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unsigned int clk_rate_hz;
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struct clk *clk;
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u8 mcast_count[256];
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u16 tx_ring_size;
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u16 rx_ring_size;
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@ -1029,7 +1030,11 @@ static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
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static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
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struct mvneta_rx_queue *rxq, u32 value)
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{
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u32 val = (pp->clk_rate_hz / 1000000) * value;
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u32 val;
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unsigned long clk_rate;
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clk_rate = clk_get_rate(pp->clk);
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val = (clk_rate / 1000000) * value;
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mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
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rxq->time_coal = value;
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@ -2601,7 +2606,7 @@ static int __devinit mvneta_init(struct mvneta_port *pp, int phy_addr)
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return 0;
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}
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static void __devexit mvneta_deinit(struct mvneta_port *pp)
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static void mvneta_deinit(struct mvneta_port *pp)
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{
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kfree(pp->txqs);
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kfree(pp->rxqs);
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@ -2671,7 +2676,7 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
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const struct mbus_dram_target_info *dram_target_info;
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struct device_node *dn = pdev->dev.of_node;
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struct device_node *phy_node;
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u32 phy_addr, clk_rate_hz;
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u32 phy_addr;
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struct mvneta_port *pp;
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struct net_device *dev;
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const char *mac_addr;
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@ -2710,12 +2715,6 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
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goto err_free_irq;
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}
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if (of_property_read_u32(dn, "clock-frequency", &clk_rate_hz) != 0) {
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dev_err(&pdev->dev, "could not read clock-frequency\n");
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err = -EINVAL;
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goto err_free_irq;
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}
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mac_addr = of_get_mac_address(dn);
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if (!mac_addr || !is_valid_ether_addr(mac_addr))
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@ -2736,7 +2735,6 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
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clear_bit(MVNETA_F_TX_DONE_TIMER_BIT, &pp->flags);
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pp->weight = MVNETA_RX_POLL_WEIGHT;
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pp->clk_rate_hz = clk_rate_hz;
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pp->phy_node = phy_node;
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pp->phy_interface = phy_mode;
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@ -2746,6 +2744,14 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
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goto err_free_irq;
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}
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pp->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pp->clk)) {
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err = PTR_ERR(pp->clk);
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goto err_unmap;
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}
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clk_prepare_enable(pp->clk);
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pp->tx_done_timer.data = (unsigned long)dev;
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pp->tx_ring_size = MVNETA_MAX_TXD;
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@ -2757,7 +2763,7 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
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err = mvneta_init(pp, phy_addr);
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if (err < 0) {
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dev_err(&pdev->dev, "can't init eth hal\n");
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goto err_unmap;
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goto err_clk;
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}
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mvneta_port_power_up(pp, phy_mode);
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@ -2785,6 +2791,8 @@ static int __devinit mvneta_probe(struct platform_device *pdev)
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err_deinit:
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mvneta_deinit(pp);
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err_clk:
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clk_disable_unprepare(pp->clk);
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err_unmap:
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iounmap(pp->base);
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err_free_irq:
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@ -2802,6 +2810,7 @@ static int __devexit mvneta_remove(struct platform_device *pdev)
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unregister_netdev(dev);
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mvneta_deinit(pp);
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clk_disable_unprepare(pp->clk);
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iounmap(pp->base);
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irq_dispose_mapping(dev->irq);
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free_netdev(dev);
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