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[ARM] 3951/1: AT91: Rename user peripheral header files

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Most of the AT91RM9200 user peripherals are also integrated into the
Atmel SAM9 range of processors.  This patch renames the headers from
at91rm9200_xx.h to at91_xx.h to indicate they're not
at91rm9200-specific.

The new SAM9-specific registers and register bits have also been
defined.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor 2006-11-30 16:08:49 +01:00 committed by Russell King
parent 6171de8f57
commit a5c474580b
6 changed files with 38 additions and 62 deletions
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24
include/asm-arm/arch-at91rm9200/at91rm9200_mci.h → include/asm-arm/arch-at91rm9200/at91_mci.h
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@ -1,11 +1,11 @@
/* /*
* include/asm-arm/arch-at91rm9200/at91rm9200_mci.h * include/asm-arm/arch-at91rm9200/at91_mci.h
* *
* Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People * Copyright (C) SAN People
* *
* MultiMedia Card Interface (MCI) registers. * MultiMedia Card Interface (MCI) registers.
* Based on AT91RM9200 datasheet revision E. * Based on AT91RM9200 datasheet revision F.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -13,8 +13,8 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#ifndef AT91RM9200_MCI_H #ifndef AT91_MCI_H
#define AT91RM9200_MCI_H #define AT91_MCI_H
#define AT91_MCI_CR 0x00 /* Control Register */ #define AT91_MCI_CR 0x00 /* Control Register */
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
@ -25,10 +25,10 @@
#define AT91_MCI_MR 0x04 /* Mode Register */ #define AT91_MCI_MR 0x04 /* Mode Register */
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */ #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
@ -43,8 +43,8 @@
#define AT91_MCI_DTOMUL_1M (7 << 4) #define AT91_MCI_DTOMUL_1M (7 << 4)
#define AT91_MCI_SDCR 0x0c /* SD Card Register */ #define AT91_MCI_SDCR 0x0c /* SD Card Register */
#define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */ #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91_MCI_ARGR 0x10 /* Argument Register */ #define AT91_MCI_ARGR 0x10 /* Argument Register */
@ -78,18 +78,20 @@
#define AT91_MCI_SR 0x40 /* Status Register */ #define AT91_MCI_SR 0x40 /* Status Register */
#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */

8
include/asm-arm/arch-at91rm9200/at91rm9200_spi.h → include/asm-arm/arch-at91rm9200/at91_spi.h
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@ -1,5 +1,5 @@
/* /*
* include/asm-arm/arch-at91rm9200/at91rm9200_spi.h * include/asm-arm/arch-at91rm9200/at91_spi.h
* *
* Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People * Copyright (C) SAN People
@ -13,8 +13,8 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#ifndef AT91RM9200_SPI_H #ifndef AT91_SPI_H
#define AT91RM9200_SPI_H #define AT91_SPI_H
#define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_CR 0x00 /* Control Register */
#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
@ -28,7 +28,7 @@
#define AT91_SPI_PS_FIXED (0 << 1) #define AT91_SPI_PS_FIXED (0 << 1)
#define AT91_SPI_PS_VARIABLE (1 << 1) #define AT91_SPI_PS_VARIABLE (1 << 1)
#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */ #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */

16
include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h → include/asm-arm/arch-at91rm9200/at91_ssc.h
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@ -1,5 +1,5 @@
/* /*
* include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h * include/asm-arm/arch-at91rm9200/at91_ssc.h
* *
* Copyright (C) SAN People * Copyright (C) SAN People
* *
@ -12,8 +12,8 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#ifndef AT91RM9200_SSC_H #ifndef AT91_SSC_H
#define AT91RM9200_SSC_H #define AT91_SSC_H
#define AT91_SSC_CR 0x00 /* Control Register */ #define AT91_SSC_CR 0x00 /* Control Register */
#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
@ -36,6 +36,10 @@
#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
#define AT91_SSC_CKI_FALLING (0 << 5) #define AT91_SSC_CKI_FALLING (0 << 5)
#define AT91_SSC_CK_RISING (1 << 5) #define AT91_SSC_CK_RISING (1 << 5)
#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
#define AT91_SSC_CKG_NONE (0 << 6)
#define AT91_SSC_CKG_RFLOW (1 << 6)
#define AT91_SSC_CKG_RFHIGH (2 << 6)
#define AT91_SSC_START (0xf << 8) /* Start Selection */ #define AT91_SSC_START (0xf << 8) /* Start Selection */
#define AT91_SSC_START_CONTINUOUS (0 << 8) #define AT91_SSC_START_CONTINUOUS (0 << 8)
#define AT91_SSC_START_TX_RX (1 << 8) #define AT91_SSC_START_TX_RX (1 << 8)
@ -45,6 +49,7 @@
#define AT91_SSC_START_RISING_RF (5 << 8) #define AT91_SSC_START_RISING_RF (5 << 8)
#define AT91_SSC_START_LEVEL_RF (6 << 8) #define AT91_SSC_START_LEVEL_RF (6 << 8)
#define AT91_SSC_START_EDGE_RF (7 << 8) #define AT91_SSC_START_EDGE_RF (7 << 8)
#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
@ -75,6 +80,9 @@
#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
#define AT91_SSC_SR 0x40 /* Status Register */ #define AT91_SSC_SR 0x40 /* Status Register */
#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
@ -84,6 +92,8 @@
#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */

6
include/asm-arm/arch-at91rm9200/at91rm9200_tc.h → include/asm-arm/arch-at91rm9200/at91_tc.h
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@ -1,5 +1,5 @@
/* /*
* include/asm-arm/arch-at91rm9200/at91rm9200_tc.h * include/asm-arm/arch-at91rm9200/at91_tc.h
* *
* Copyright (C) SAN People * Copyright (C) SAN People
* *
@ -12,8 +12,8 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#ifndef AT91RM9200_TC_H #ifndef AT91_TC_H
#define AT91RM9200_TC_H #define AT91_TC_H
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */ #define AT91_TC_BCR 0xc0 /* TC Block Control Register */
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */ #define AT91_TC_SYNC (1 << 0) /* Synchro Command */

10
include/asm-arm/arch-at91rm9200/at91rm9200_twi.h → include/asm-arm/arch-at91rm9200/at91_twi.h
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@ -1,5 +1,5 @@
/* /*
* include/asm-arm/arch-at91rm9200/at91rm9200_twi.h * include/asm-arm/arch-at91rm9200/at91_twi.h
* *
* Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People * Copyright (C) SAN People
@ -13,8 +13,8 @@
* (at your option) any later version. * (at your option) any later version.
*/ */
#ifndef AT91RM9200_TWI_H #ifndef AT91_TWI_H
#define AT91RM9200_TWI_H #define AT91_TWI_H
#define AT91_TWI_CR 0x00 /* Control Register */ #define AT91_TWI_CR 0x00 /* Control Register */
#define AT91_TWI_START (1 << 0) /* Send a Start Condition */ #define AT91_TWI_START (1 << 0) /* Send a Start Condition */
@ -43,8 +43,8 @@
#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */ #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */ #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */

36
include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
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@ -1,36 +0,0 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Peripheral Data Controller (PDC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_PDC_H
#define AT91RM9200_PDC_H
#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
#endif