forked from luck/tmp_suning_uos_patched
ide: add CS5536 host driver (v3)
This is a port of libata's pata_cs5536.c (written by Martin K. Petersen) to IDE subsystem. Changes done while at it: * Reprogram PIO/MWDMA timings if needed before and after DMA transfer (chipset uses shared PIO/MWDMA timings). * Fix cable detection to report 80-wires cable if BIOS set it for any device on a port (IDE core will do drive-side cable detection later). * Don't disable UDMA while programming PIO timings. * Simplify PCI/MSR support. Pros of having IDE host driver in addition to libata's one: * IDE is much lighter than SCSI+libata, the host driver itself is also a bit smaller: text data bss dec hex filename 1261 496 4 1761 6e1 drivers/ata/pata_cs5536.o 1242 128 4 1374 55e drivers/ide/cs5536.o * This allows use of IDE features which are unavailable under libata. v2: * Fixes per review from Sergei: - simplify dependency check in Kconfig - use IDE_DRV_MASK also for ->drive_data - disable UDMA when programming MWDMA - program new DTC timings only when necessary - fix printk() level in cs5536_init_one() * Fix patch description according to comments from Alan and Sergei. v3: * Smarter masking of UDMA bits per Sergei's suggestion. Cc: Martin K. Petersen <mkp@mkp.net> Cc: Karl Auerbach <karl@iwl.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
parent
9f6514c1c5
commit
a77dcc437c
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@ -465,6 +465,16 @@ config BLK_DEV_CS5535
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It is safe to say Y to this question.
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It is safe to say Y to this question.
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config BLK_DEV_CS5536
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tristate "CS5536 chipset support"
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depends on X86_32
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select BLK_DEV_IDEDMA_PCI
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help
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This option enables support for the AMD CS5536
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companion chip used with the Geode LX processor family.
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If unsure, say N.
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config BLK_DEV_HPT366
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config BLK_DEV_HPT366
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tristate "HPT36X/37X chipset support"
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tristate "HPT36X/37X chipset support"
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select BLK_DEV_IDEDMA_PCI
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select BLK_DEV_IDEDMA_PCI
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@ -43,6 +43,7 @@ obj-$(CONFIG_BLK_DEV_CMD64X) += cmd64x.o
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obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o
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obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o
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obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
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obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
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obj-$(CONFIG_BLK_DEV_CS5535) += cs5535.o
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obj-$(CONFIG_BLK_DEV_CS5535) += cs5535.o
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obj-$(CONFIG_BLK_DEV_CS5536) += cs5536.o
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obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o
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obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o
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obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
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obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
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obj-$(CONFIG_BLK_DEV_DELKIN) += delkin_cb.o
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obj-$(CONFIG_BLK_DEV_DELKIN) += delkin_cb.o
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308
drivers/ide/cs5536.c
Normal file
308
drivers/ide/cs5536.c
Normal file
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@ -0,0 +1,308 @@
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/*
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* CS5536 PATA support
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* (C) 2007 Martin K. Petersen <mkp@mkp.net>
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* (C) 2009 Bartlomiej Zolnierkiewicz
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Documentation:
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* Available from AMD web site.
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*
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* The IDE timing registers for the CS5536 live in the Geode Machine
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* Specific Register file and not PCI config space. Most BIOSes
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* virtualize the PCI registers so the chip looks like a standard IDE
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* controller. Unfortunately not all implementations get this right.
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* In particular some have problems with unaligned accesses to the
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* virtualized PCI registers. This driver always does full dword
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* writes to work around the issue. Also, in case of a bad BIOS this
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* driver can be loaded with the "msr=1" parameter which forces using
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* the Machine Specific Registers to configure the device.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/msr.h>
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#define DRV_NAME "cs5536"
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enum {
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MSR_IDE_CFG = 0x51300010,
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PCI_IDE_CFG = 0x40,
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CFG = 0,
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DTC = 2,
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CAST = 3,
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ETC = 4,
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IDE_CFG_CHANEN = (1 << 1),
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IDE_CFG_CABLE = (1 << 17) | (1 << 16),
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IDE_D0_SHIFT = 24,
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IDE_D1_SHIFT = 16,
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IDE_DRV_MASK = 0xff,
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IDE_CAST_D0_SHIFT = 6,
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IDE_CAST_D1_SHIFT = 4,
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IDE_CAST_DRV_MASK = 0x3,
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IDE_CAST_CMD_SHIFT = 24,
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IDE_CAST_CMD_MASK = 0xff,
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IDE_ETC_UDMA_MASK = 0xc0,
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};
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static int use_msr;
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static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
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{
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if (unlikely(use_msr)) {
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u32 dummy;
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rdmsr(MSR_IDE_CFG + reg, *val, dummy);
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return 0;
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}
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return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
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}
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static int cs5536_write(struct pci_dev *pdev, int reg, int val)
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{
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if (unlikely(use_msr)) {
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wrmsr(MSR_IDE_CFG + reg, val, 0);
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return 0;
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}
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return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
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}
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static void cs5536_program_dtc(ide_drive_t *drive, u8 tim)
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{
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struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
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int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
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u32 dtc;
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cs5536_read(pdev, DTC, &dtc);
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dtc &= ~(IDE_DRV_MASK << dshift);
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dtc |= tim << dshift;
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cs5536_write(pdev, DTC, dtc);
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}
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/**
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* cs5536_cable_detect - detect cable type
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* @hwif: Port to detect on
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*
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* Perform cable detection for ATA66 capable cable.
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*
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* Returns a cable type.
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*/
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static u8 cs5536_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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u32 cfg;
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cs5536_read(pdev, CFG, &cfg);
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if (cfg & IDE_CFG_CABLE)
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return ATA_CBL_PATA80;
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else
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return ATA_CBL_PATA40;
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}
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/**
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* cs5536_set_pio_mode - PIO timing setup
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* @drive: ATA device
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* @pio: PIO mode number
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*/
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static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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static const u8 drv_timings[5] = {
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0x98, 0x55, 0x32, 0x21, 0x20,
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};
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static const u8 addr_timings[5] = {
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0x2, 0x1, 0x0, 0x0, 0x0,
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};
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static const u8 cmd_timings[5] = {
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0x99, 0x92, 0x90, 0x22, 0x20,
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};
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struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
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ide_drive_t *pair = ide_get_pair_dev(drive);
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int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
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u32 cast;
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u8 cmd_pio = pio;
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if (pair)
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cmd_pio = min(pio, ide_get_best_pio_mode(pair, 255, 4));
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drive->drive_data &= (IDE_DRV_MASK << 8);
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drive->drive_data |= drv_timings[pio];
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cs5536_program_dtc(drive, drv_timings[pio]);
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cs5536_read(pdev, CAST, &cast);
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cast &= ~(IDE_CAST_DRV_MASK << cshift);
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cast |= addr_timings[pio] << cshift;
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cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
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cast |= cmd_timings[cmd_pio] << IDE_CAST_CMD_SHIFT;
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cs5536_write(pdev, CAST, cast);
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}
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/**
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* cs5536_set_dma_mode - DMA timing setup
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* @drive: ATA device
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* @mode: DMA mode
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*/
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static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode)
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{
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static const u8 udma_timings[6] = {
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0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
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};
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static const u8 mwdma_timings[3] = {
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0x67, 0x21, 0x20,
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};
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struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
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int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
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u32 etc;
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cs5536_read(pdev, ETC, &etc);
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if (mode >= XFER_UDMA_0) {
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etc &= ~(IDE_DRV_MASK << dshift);
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etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
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} else { /* MWDMA */
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etc &= ~(IDE_ETC_UDMA_MASK << dshift);
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drive->drive_data &= IDE_DRV_MASK;
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drive->drive_data |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
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}
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cs5536_write(pdev, ETC, etc);
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}
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static void cs5536_dma_start(ide_drive_t *drive)
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{
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if (drive->current_speed < XFER_UDMA_0 &&
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(drive->drive_data >> 8) != (drive->drive_data & IDE_DRV_MASK))
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cs5536_program_dtc(drive, drive->drive_data >> 8);
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ide_dma_start(drive);
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}
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static int cs5536_dma_end(ide_drive_t *drive)
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{
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int ret = ide_dma_end(drive);
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if (drive->current_speed < XFER_UDMA_0 &&
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(drive->drive_data >> 8) != (drive->drive_data & IDE_DRV_MASK))
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cs5536_program_dtc(drive, drive->drive_data & IDE_DRV_MASK);
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return ret;
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}
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static const struct ide_port_ops cs5536_port_ops = {
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.set_pio_mode = cs5536_set_pio_mode,
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.set_dma_mode = cs5536_set_dma_mode,
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.cable_detect = cs5536_cable_detect,
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};
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static const struct ide_dma_ops cs5536_dma_ops = {
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.dma_host_set = ide_dma_host_set,
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.dma_setup = ide_dma_setup,
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.dma_exec_cmd = ide_dma_exec_cmd,
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.dma_start = cs5536_dma_start,
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.dma_end = cs5536_dma_end,
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.dma_test_irq = ide_dma_test_irq,
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.dma_lost_irq = ide_dma_lost_irq,
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.dma_timeout = ide_dma_timeout,
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};
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static const struct ide_port_info cs5536_info = {
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.name = DRV_NAME,
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.port_ops = &cs5536_port_ops,
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.dma_ops = &cs5536_dma_ops,
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.host_flags = IDE_HFLAG_SINGLE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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};
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/**
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* cs5536_init_one
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* @dev: PCI device
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* @id: Entry in match table
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*/
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static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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u32 cfg;
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if (use_msr)
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printk(KERN_INFO DRV_NAME ": Using MSR regs instead of PCI\n");
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cs5536_read(dev, CFG, &cfg);
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if ((cfg & IDE_CFG_CHANEN) == 0) {
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printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
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return -ENODEV;
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}
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return ide_pci_init_one(dev, &cs5536_info, NULL);
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}
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static const struct pci_device_id cs5536_pci_tbl[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
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{ },
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};
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static struct pci_driver cs5536_pci_driver = {
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.name = DRV_NAME,
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.id_table = cs5536_pci_tbl,
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.probe = cs5536_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init cs5536_init(void)
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{
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return pci_register_driver(&cs5536_pci_driver);
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}
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static void __exit cs5536_exit(void)
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{
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pci_unregister_driver(&cs5536_pci_driver);
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}
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MODULE_AUTHOR("Martin K. Petersen, Bartlomiej Zolnierkiewicz");
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MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, cs5536_pci_tbl);
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module_param_named(msr, use_msr, int, 0644);
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MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
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module_init(cs5536_init);
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module_exit(cs5536_exit);
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