forked from luck/tmp_suning_uos_patched
[POWERPC] Add support for FP emulation for the e300c2 core
The e300c2 has no FPU. Its MSR[FP] is grounded to zero. If an attempt is made to execute a floating point instruction (including floating-point load, store, or move instructions), the e300c2 takes a floating-point unavailable interrupt. This patch adds support for FP emulation on the e300c2 by declaring a new CPU_FTR_FP_TAKES_FPUNAVAIL, where FP unavail interrupts are intercepted and redirected to the ProgramCheck exception path for correct emulation handling. (If we run out of CPU_FTR bits we could look to reclaim this bit by adding support to test the cpu_user_features for PPC_FEATURE_HAS_FPU instead) It adds a nop to the exception path for 32-bit processors with a FPU. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -706,7 +706,7 @@ config FORCE_MAX_ZONEORDER
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config MATH_EMULATION
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bool "Math emulation"
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depends on 4xx || 8xx || E200 || E500
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depends on 4xx || 8xx || E200 || PPC_83xx || E500
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---help---
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Some PowerPC chips designed for embedded applications do not have
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a floating-point unit and therefore do not implement the
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@ -833,7 +833,7 @@ static struct cpu_spec cpu_specs[] = {
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.pvr_mask = 0x7fff0000,
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.pvr_value = 0x00840000,
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.cpu_name = "e300c2",
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.cpu_features = CPU_FTRS_E300,
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.cpu_features = CPU_FTRS_E300C2,
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.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@ -437,6 +437,13 @@ Alignment:
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/* Floating-point unavailable */
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. = 0x800
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FPUnavailable:
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BEGIN_FTR_SECTION
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/*
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* Certain Freescale cores don't have a FPU and treat fp instructions
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* as a FP Unavailable exception. Redirect to illegal/emulation handling.
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*/
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b ProgramCheck
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END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
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EXCEPTION_PROLOG
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bne load_up_fpu /* if from user, just load it up */
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addi r3,r1,STACK_FRAME_OVERHEAD
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@ -782,6 +782,8 @@ void __kprobes program_check_exception(struct pt_regs *regs)
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unsigned int reason = get_reason(regs);
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extern int do_mathemu(struct pt_regs *regs);
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/* We can now get here via a FP Unavailable exception if the core
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* has no FPU, in that case no reason flags will be set */
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#ifdef CONFIG_MATH_EMULATION
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/* (reason & REASON_ILLEGAL) would be the obvious thing here,
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* but there seems to be a hardware bug on the 405GP (RevD)
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@ -126,6 +126,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
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#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
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#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
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#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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@ -295,6 +296,9 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
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CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_COMMON)
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#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
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CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
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#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
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#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
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@ -364,7 +368,8 @@ enum {
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CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
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CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
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CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
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CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
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CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
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CPU_FTRS_CLASSIC32 |
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#else
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CPU_FTRS_GENERIC_32 |
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#endif
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@ -403,7 +408,8 @@ enum {
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CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
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CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
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CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
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CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
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CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
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CPU_FTRS_CLASSIC32 &
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#else
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CPU_FTRS_GENERIC_32 &
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#endif
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