forked from luck/tmp_suning_uos_patched
ARCv2: SMP: ARConnect debug/robustness
- Handle possible interrupt coalescing from MCIP - chk if prev IPI ack before sending new Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -448,9 +448,10 @@ menuconfig ARC_DBG
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bool "ARC debugging"
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default y
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if ARC_DBG
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config ARC_DW2_UNWIND
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bool "Enable DWARF specific kernel stack unwind"
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depends on ARC_DBG
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default y
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select KALLSYMS
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help
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@ -464,18 +465,26 @@ config ARC_DW2_UNWIND
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config ARC_DBG_TLB_PARANOIA
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bool "Paranoia Checks in Low Level TLB Handlers"
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depends on ARC_DBG
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default n
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config ARC_DBG_TLB_MISS_COUNT
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bool "Profile TLB Misses"
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default n
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select DEBUG_FS
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depends on ARC_DBG
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help
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Counts number of I and D TLB Misses and exports them via Debugfs
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The counters can be cleared via Debugfs as well
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if SMP
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config ARC_IPI_DBG
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bool "Debug Inter Core interrupts"
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default n
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endif
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endif
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config ARC_UBOOT_SUPPORT
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bool "Support uboot arg Handling"
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default n
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@ -33,27 +33,67 @@ void mcip_init_smp(unsigned int cpu)
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static void mcip_ipi_send(int cpu)
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{
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unsigned long flags;
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int ipi_was_pending;
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/*
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* NOTE: We must spin here if the other cpu hasn't yet
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* serviced a previous message. This can burn lots
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* of time, but we MUST follows this protocol or
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* ipi messages can be lost!!!
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* Also, we must release the lock in this loop because
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* the other side may get to this same loop and not
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* be able to ack -- thus causing deadlock.
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*/
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do {
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
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ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
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if (ipi_was_pending == 0)
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break; /* break out but keep lock */
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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} while (1);
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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#ifdef CONFIG_ARC_IPI_DBG
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if (ipi_was_pending)
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pr_info("IPI ACK delayed from cpu %d\n", cpu);
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#endif
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}
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static void mcip_ipi_clear(int irq)
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{
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unsigned int cpu;
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unsigned int cpu, c;
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unsigned long flags;
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unsigned int __maybe_unused copy;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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/* Who sent the IPI */
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__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
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cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
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copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
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__mcip_cmd(CMD_INTRPT_GENERATE_ACK, __ffs(cpu)); /* 0,1,2,3... */
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/*
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* In rare case, multiple concurrent IPIs sent to same target can
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* possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
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* "vectored" (multiple bits sets) as opposed to typical single bit
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*/
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do {
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c = __ffs(cpu); /* 0,1,2,3 */
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__mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
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cpu &= ~(1U << c);
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} while (cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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#ifdef CONFIG_ARC_IPI_DBG
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if (c != __ffs(copy))
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pr_info("IPIs from %x coalesced to %x\n",
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copy, raw_smp_processor_id());
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#endif
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}
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volatile int wake_flag;
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@ -278,8 +278,10 @@ static void ipi_cpu_stop(void)
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machine_halt();
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}
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static inline void __do_IPI(unsigned long msg)
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static inline int __do_IPI(unsigned long msg)
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{
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int rc = 0;
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switch (msg) {
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case IPI_RESCHEDULE:
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scheduler_ipi();
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@ -294,8 +296,10 @@ static inline void __do_IPI(unsigned long msg)
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break;
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default:
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pr_warn("IPI with unexpected msg %ld\n", msg);
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rc = 1;
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}
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return rc;
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}
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/*
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@ -305,6 +309,7 @@ static inline void __do_IPI(unsigned long msg)
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irqreturn_t do_IPI(int irq, void *dev_id)
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{
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unsigned long pending;
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unsigned long __maybe_unused copy;
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pr_debug("IPI [%ld] received on cpu %d\n",
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*this_cpu_ptr(&ipi_data), smp_processor_id());
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@ -316,11 +321,18 @@ irqreturn_t do_IPI(int irq, void *dev_id)
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* "dequeue" the msg corresponding to this IPI (and possibly other
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* piggybacked msg from elided IPIs: see ipi_send_msg_one() above)
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*/
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pending = xchg(this_cpu_ptr(&ipi_data), 0);
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copy = pending = xchg(this_cpu_ptr(&ipi_data), 0);
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do {
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unsigned long msg = __ffs(pending);
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__do_IPI(msg);
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int rc;
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rc = __do_IPI(msg);
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#ifdef CONFIG_ARC_IPI_DBG
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/* IPI received but no valid @msg */
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if (rc)
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pr_info("IPI with bogus msg %ld in %ld\n", msg, copy);
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#endif
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pending &= ~(1U << msg);
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} while (pending);
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