forked from luck/tmp_suning_uos_patched
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
This commit is contained in:
commit
aac372de6b
arch/sparc64
@ -53,19 +53,18 @@
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* be guaranteed to be 0 ... mmu_context.h does guarantee this
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* by only using 10 bits in the hwcontext value.
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*/
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#define CREATE_VPTE_OFFSET1(r1, r2)
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#define CREATE_VPTE_OFFSET1(r1, r2) nop
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#define CREATE_VPTE_OFFSET2(r1, r2) \
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srax r1, 10, r2
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#define CREATE_VPTE_NOP nop
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#else
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#define CREATE_VPTE_OFFSET1(r1, r2) \
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srax r1, PAGE_SHIFT, r2
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#define CREATE_VPTE_OFFSET2(r1, r2) \
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sllx r2, 3, r2
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#define CREATE_VPTE_NOP
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#endif
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/* DTLB ** ICACHE line 1: Quick user TLB misses */
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mov TLB_SFSR, %g1
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ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS
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andcc %g4, TAG_CONTEXT_BITS, %g0 ! From Nucleus?
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from_tl1_trap:
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@ -74,18 +73,16 @@ from_tl1_trap:
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be,pn %xcc, kvmap ! Yep, special processing
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CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
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cmp %g5, 4 ! Last trap level?
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be,pn %xcc, longpath ! Yep, cannot risk VPTE miss
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nop ! delay slot
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/* DTLB ** ICACHE line 2: User finish + quick kernel TLB misses */
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be,pn %xcc, longpath ! Yep, cannot risk VPTE miss
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nop ! delay slot
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ldxa [%g3 + %g6] ASI_S, %g5 ! Load VPTE
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1: brgez,pn %g5, longpath ! Invalid, branch out
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nop ! Delay-slot
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9: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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retry ! Trap return
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nop
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nop
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nop
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/* DTLB ** ICACHE line 3: winfixups+real_faults */
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longpath:
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@ -106,8 +103,7 @@ longpath:
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nop
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nop
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nop
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CREATE_VPTE_NOP
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nop
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#undef CREATE_VPTE_OFFSET1
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#undef CREATE_VPTE_OFFSET2
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#undef CREATE_VPTE_NOP
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@ -14,14 +14,14 @@
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*/
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/* PROT ** ICACHE line 1: User DTLB protection trap */
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stxa %g0, [%g1] ASI_DMMU ! Clear SFSR FaultValid bit
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membar #Sync ! Synchronize ASI stores
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rdpr %pstate, %g5 ! Move into alternate globals
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mov TLB_SFSR, %g1
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stxa %g0, [%g1] ASI_DMMU ! Clear FaultValid bit
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membar #Sync ! Synchronize stores
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rdpr %pstate, %g5 ! Move into alt-globals
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wrpr %g5, PSTATE_AG|PSTATE_MG, %pstate
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rdpr %tl, %g1 ! Need to do a winfixup?
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rdpr %tl, %g1 ! Need a winfixup?
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cmp %g1, 1 ! Trap level >1?
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mov TLB_TAG_ACCESS, %g4 ! Prepare reload of vaddr
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nop
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mov TLB_TAG_ACCESS, %g4 ! For reload of vaddr
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/* PROT ** ICACHE line 2: More real fault processing */
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bgu,pn %xcc, winfix_trampoline ! Yes, perform winfixup
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@ -28,19 +28,14 @@
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#include <asm/mmu.h>
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/* This section from from _start to sparc64_boot_end should fit into
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* 0x0000.0000.0040.4000 to 0x0000.0000.0040.8000 and will be sharing space
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* with bootup_user_stack, which is from 0x0000.0000.0040.4000 to
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* 0x0000.0000.0040.6000 and empty_bad_page, which is from
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* 0x0000.0000.0040.6000 to 0x0000.0000.0040.8000.
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* 0x0000000000404000 to 0x0000000000408000.
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*/
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.text
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.globl start, _start, stext, _stext
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_start:
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start:
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_stext:
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stext:
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bootup_user_stack:
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! 0x0000000000404000
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b sparc64_boot
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flushw /* Flush register file. */
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@ -392,31 +387,30 @@ tlb_fixup_done:
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* former does use this code, the latter does not yet due
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* to some complexities. That should be fixed up at some
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* point.
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*
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* There used to be enormous complexity wrt. transferring
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* over from the firwmare's trap table to the Linux kernel's.
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* For example, there was a chicken & egg problem wrt. building
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* the OBP page tables, yet needing to be on the Linux kernel
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* trap table (to translate PAGE_OFFSET addresses) in order to
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* do that.
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*
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* We now handle OBP tlb misses differently, via linear lookups
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* into the prom_trans[] array. So that specific problem no
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* longer exists. Yet, unfortunately there are still some issues
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* preventing trampoline.S from using this code... ho hum.
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*/
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.globl setup_trap_table
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setup_trap_table:
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save %sp, -192, %sp
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/* Force interrupts to be disabled. Transferring over to
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* the Linux trap table is a very delicate operation.
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* Until we are actually on the Linux trap table, we cannot
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* get the PAGE_OFFSET linear mappings translated. We need
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* that mapping to be setup in order to initialize the firmware
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* page tables.
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*
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* So there is this window of time, from the return from
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* prom_set_trap_table() until inherit_prom_mappings_post()
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* (in arch/sparc64/mm/init.c) completes, during which no
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* firmware address space accesses can be made.
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*/
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/* Force interrupts to be disabled. */
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rdpr %pstate, %o1
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andn %o1, PSTATE_IE, %o1
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wrpr %o1, 0x0, %pstate
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wrpr %g0, 15, %pil
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/* Ok, now make the final valid firmware call to jump over
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* to the Linux trap table.
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*/
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/* Make the firmware call to jump over to the Linux trap table. */
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call prom_set_trap_table
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sethi %hi(sparc64_ttable_tl0), %o0
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@ -540,15 +534,21 @@ setup_tba: /* i0 = is_starfire */
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ret
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restore
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sparc64_boot_end:
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#include "systbls.S"
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#include "ktlb.S"
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#include "etrap.S"
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#include "rtrap.S"
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#include "winfixup.S"
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#include "entry.S"
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/*
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* The following skips make sure the trap table in ttable.S is aligned
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* The following skip makes sure the trap table in ttable.S is aligned
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* on a 32K boundary as required by the v9 specs for TBA register.
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*/
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sparc64_boot_end:
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.skip 0x2000 + _start - sparc64_boot_end
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bootup_user_stack_end:
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.skip 0x2000
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1:
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.skip 0x4000 + _start - 1b
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#ifdef CONFIG_SBUS
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/* This is just a hack to fool make depend config.h discovering
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@ -560,15 +560,6 @@ bootup_user_stack_end:
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! 0x0000000000408000
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#include "ttable.S"
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#include "systbls.S"
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#include "ktlb.S"
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#include "etrap.S"
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#include "rtrap.S"
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#include "winfixup.S"
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#include "entry.S"
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/* This is just anal retentiveness on my part... */
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.align 16384
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.data
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.align 8
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@ -15,14 +15,12 @@
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*/
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#define CREATE_VPTE_OFFSET1(r1, r2) \
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srax r1, 10, r2
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#define CREATE_VPTE_OFFSET2(r1, r2)
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#define CREATE_VPTE_NOP nop
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#define CREATE_VPTE_OFFSET2(r1, r2) nop
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#else /* PAGE_SHIFT */
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#define CREATE_VPTE_OFFSET1(r1, r2) \
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srax r1, PAGE_SHIFT, r2
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#define CREATE_VPTE_OFFSET2(r1, r2) \
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sllx r2, 3, r2
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#define CREATE_VPTE_NOP
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#endif /* PAGE_SHIFT */
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@ -36,6 +34,7 @@
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*/
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/* ITLB ** ICACHE line 1: Quick user TLB misses */
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mov TLB_SFSR, %g1
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ldxa [%g1 + %g1] ASI_IMMU, %g4 ! Get TAG_ACCESS
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CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset
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CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset
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@ -43,41 +42,38 @@
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1: brgez,pn %g5, 3f ! Not valid, branch out
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sethi %hi(_PAGE_EXEC), %g4 ! Delay-slot
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andcc %g5, %g4, %g0 ! Executable?
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/* ITLB ** ICACHE line 2: Real faults */
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be,pn %xcc, 3f ! Nope, branch.
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nop ! Delay-slot
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2: stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load PTE into TLB
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retry ! Trap return
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3: rdpr %pstate, %g4 ! Move into alternate globals
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/* ITLB ** ICACHE line 2: Real faults */
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3: rdpr %pstate, %g4 ! Move into alt-globals
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wrpr %g4, PSTATE_AG|PSTATE_MG, %pstate
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rdpr %tpc, %g5 ! And load faulting VA
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mov FAULT_CODE_ITLB, %g4 ! It was read from ITLB
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sparc64_realfault_common: ! Called by TL0 dtlb_miss too
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/* ITLB ** ICACHE line 3: Finish faults */
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sparc64_realfault_common: ! Called by dtlb_miss
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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ba,pt %xcc, etrap ! Save state
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1: rd %pc, %g7 ! ...
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nop
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/* ITLB ** ICACHE line 3: Finish faults + window fixups */
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call do_sparc64_fault ! Call fault handler
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add %sp, PTREGS_OFF, %o0! Compute pt_regs arg
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ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
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nop
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/* ITLB ** ICACHE line 4: Window fixups */
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winfix_trampoline:
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rdpr %tpc, %g3 ! Prepare winfixup TNPC
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or %g3, 0x7c, %g3 ! Compute offset to branch
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or %g3, 0x7c, %g3 ! Compute branch offset
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wrpr %g3, %tnpc ! Write it into TNPC
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done ! Do it to it
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/* ITLB ** ICACHE line 4: Unused... */
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nop
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nop
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nop
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nop
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CREATE_VPTE_NOP
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#undef CREATE_VPTE_OFFSET1
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#undef CREATE_VPTE_OFFSET2
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#undef CREATE_VPTE_NOP
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|
@ -58,9 +58,6 @@ vpte_noent:
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done
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vpte_insn_obp:
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sethi %hi(prom_pmd_phys), %g5
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ldx [%g5 + %lo(prom_pmd_phys)], %g5
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/* Behave as if we are at TL0. */
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wrpr %g0, 1, %tl
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rdpr %tpc, %g4 /* Find original faulting iaddr */
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@ -71,58 +68,57 @@ vpte_insn_obp:
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mov TLB_SFSR, %g1
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stxa %g4, [%g1 + %g1] ASI_IMMU
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/* Get PMD offset. */
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srlx %g4, 23, %g6
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and %g6, 0x7ff, %g6
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sllx %g6, 2, %g6
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sethi %hi(prom_trans), %g5
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or %g5, %lo(prom_trans), %g5
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/* Load PMD, is it valid? */
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lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
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brz,pn %g5, longpath
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sllx %g5, 11, %g5
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1: ldx [%g5 + 0x00], %g6 ! base
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brz,a,pn %g6, longpath ! no more entries, fail
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mov TLB_SFSR, %g1 ! and restore %g1
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ldx [%g5 + 0x08], %g1 ! len
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add %g6, %g1, %g1 ! end
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cmp %g6, %g4
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bgu,pt %xcc, 2f
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cmp %g4, %g1
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||||
bgeu,pt %xcc, 2f
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||||
ldx [%g5 + 0x10], %g1 ! PTE
|
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|
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/* Get PTE offset. */
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srlx %g4, 13, %g6
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and %g6, 0x3ff, %g6
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sllx %g6, 3, %g6
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|
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/* Load PTE. */
|
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ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
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brgez,pn %g5, longpath
|
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nop
|
||||
|
||||
/* TLB load and return from trap. */
|
||||
/* TLB load, restore %g1, and return from trap. */
|
||||
sub %g4, %g6, %g6
|
||||
add %g1, %g6, %g5
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mov TLB_SFSR, %g1
|
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stxa %g5, [%g0] ASI_ITLB_DATA_IN
|
||||
retry
|
||||
|
||||
2: ba,pt %xcc, 1b
|
||||
add %g5, (3 * 8), %g5 ! next entry
|
||||
|
||||
kvmap_do_obp:
|
||||
sethi %hi(prom_pmd_phys), %g5
|
||||
ldx [%g5 + %lo(prom_pmd_phys)], %g5
|
||||
sethi %hi(prom_trans), %g5
|
||||
or %g5, %lo(prom_trans), %g5
|
||||
srlx %g4, 13, %g4
|
||||
sllx %g4, 13, %g4
|
||||
|
||||
/* Get PMD offset. */
|
||||
srlx %g4, 23, %g6
|
||||
and %g6, 0x7ff, %g6
|
||||
sllx %g6, 2, %g6
|
||||
1: ldx [%g5 + 0x00], %g6 ! base
|
||||
brz,a,pn %g6, longpath ! no more entries, fail
|
||||
mov TLB_SFSR, %g1 ! and restore %g1
|
||||
ldx [%g5 + 0x08], %g1 ! len
|
||||
add %g6, %g1, %g1 ! end
|
||||
cmp %g6, %g4
|
||||
bgu,pt %xcc, 2f
|
||||
cmp %g4, %g1
|
||||
bgeu,pt %xcc, 2f
|
||||
ldx [%g5 + 0x10], %g1 ! PTE
|
||||
|
||||
/* Load PMD, is it valid? */
|
||||
lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
|
||||
brz,pn %g5, longpath
|
||||
sllx %g5, 11, %g5
|
||||
|
||||
/* Get PTE offset. */
|
||||
srlx %g4, 13, %g6
|
||||
and %g6, 0x3ff, %g6
|
||||
sllx %g6, 3, %g6
|
||||
|
||||
/* Load PTE. */
|
||||
ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
|
||||
brgez,pn %g5, longpath
|
||||
nop
|
||||
|
||||
/* TLB load and return from trap. */
|
||||
/* TLB load, restore %g1, and return from trap. */
|
||||
sub %g4, %g6, %g6
|
||||
add %g1, %g6, %g5
|
||||
mov TLB_SFSR, %g1
|
||||
stxa %g5, [%g0] ASI_DTLB_DATA_IN
|
||||
retry
|
||||
|
||||
2: ba,pt %xcc, 1b
|
||||
add %g5, (3 * 8), %g5 ! next entry
|
||||
|
||||
/*
|
||||
* On a first level data miss, check whether this is to the OBP range (note
|
||||
* that such accesses can be made by prom, as well as by kernel using
|
||||
|
@ -105,7 +105,7 @@ static void __init read_obp_memory(const char *property,
|
||||
regs[i].phys_addr = base;
|
||||
regs[i].reg_size = size;
|
||||
}
|
||||
sort(regs, ents, sizeof(struct linux_prom64_registers),
|
||||
sort(regs, ents, sizeof(struct linux_prom64_registers),
|
||||
cmp_p64, NULL);
|
||||
}
|
||||
|
||||
@ -367,8 +367,11 @@ struct linux_prom_translation {
|
||||
unsigned long size;
|
||||
unsigned long data;
|
||||
};
|
||||
static struct linux_prom_translation prom_trans[512] __initdata;
|
||||
static unsigned int prom_trans_ents __initdata;
|
||||
|
||||
/* Exported for kernel TLB miss handling in ktlb.S */
|
||||
struct linux_prom_translation prom_trans[512] __read_mostly;
|
||||
unsigned int prom_trans_ents __read_mostly;
|
||||
unsigned int swapper_pgd_zero __read_mostly;
|
||||
|
||||
extern unsigned long prom_boot_page;
|
||||
extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
|
||||
@ -378,122 +381,57 @@ extern void register_prom_callbacks(void);
|
||||
/* Exported for SMP bootup purposes. */
|
||||
unsigned long kern_locked_tte_data;
|
||||
|
||||
/* Exported for kernel TLB miss handling in ktlb.S */
|
||||
unsigned long prom_pmd_phys __read_mostly;
|
||||
unsigned int swapper_pgd_zero __read_mostly;
|
||||
|
||||
static pmd_t *prompmd __read_mostly;
|
||||
|
||||
#define BASE_PAGE_SIZE 8192
|
||||
|
||||
/*
|
||||
* Translate PROM's mapping we capture at boot time into physical address.
|
||||
* The second parameter is only set from prom_callback() invocations.
|
||||
*/
|
||||
unsigned long prom_virt_to_phys(unsigned long promva, int *error)
|
||||
{
|
||||
pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
|
||||
pte_t *ptep;
|
||||
unsigned long base;
|
||||
int i;
|
||||
|
||||
if (pmd_none(*pmdp)) {
|
||||
if (error)
|
||||
*error = 1;
|
||||
return 0;
|
||||
}
|
||||
ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
|
||||
if (!pte_present(*ptep)) {
|
||||
if (error)
|
||||
*error = 1;
|
||||
return 0;
|
||||
}
|
||||
if (error) {
|
||||
*error = 0;
|
||||
return pte_val(*ptep);
|
||||
}
|
||||
base = pte_val(*ptep) & _PAGE_PADDR;
|
||||
for (i = 0; i < prom_trans_ents; i++) {
|
||||
struct linux_prom_translation *p = &prom_trans[i];
|
||||
|
||||
return base + (promva & (BASE_PAGE_SIZE - 1));
|
||||
if (promva >= p->virt &&
|
||||
promva < (p->virt + p->size)) {
|
||||
unsigned long base = p->data & _PAGE_PADDR;
|
||||
|
||||
if (error)
|
||||
*error = 0;
|
||||
return base + (promva & (8192 - 1));
|
||||
}
|
||||
}
|
||||
if (error)
|
||||
*error = 1;
|
||||
return 0UL;
|
||||
}
|
||||
|
||||
/* The obp translations are saved based on 8k pagesize, since obp can
|
||||
* use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
|
||||
* HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte
|
||||
* HI_OBP_ADDRESS range are handled in ktlb.S and do not use the vpte
|
||||
* scheme (also, see rant in inherit_locked_prom_mappings()).
|
||||
*/
|
||||
static void __init build_obp_range(unsigned long start, unsigned long end, unsigned long data)
|
||||
{
|
||||
unsigned long vaddr;
|
||||
|
||||
for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) {
|
||||
unsigned long val;
|
||||
pmd_t *pmd;
|
||||
pte_t *pte;
|
||||
|
||||
pmd = prompmd + ((vaddr >> 23) & 0x7ff);
|
||||
if (pmd_none(*pmd)) {
|
||||
pte = __alloc_bootmem(BASE_PAGE_SIZE, BASE_PAGE_SIZE,
|
||||
PAGE_SIZE);
|
||||
if (!pte)
|
||||
prom_halt();
|
||||
memset(pte, 0, BASE_PAGE_SIZE);
|
||||
pmd_set(pmd, pte);
|
||||
}
|
||||
pte = (pte_t *) __pmd_page(*pmd) + ((vaddr >> 13) & 0x3ff);
|
||||
|
||||
val = data;
|
||||
|
||||
/* Clear diag TTE bits. */
|
||||
if (tlb_type == spitfire)
|
||||
val &= ~0x0003fe0000000000UL;
|
||||
|
||||
set_pte_at(&init_mm, vaddr, pte,
|
||||
__pte(val | _PAGE_MODIFIED));
|
||||
|
||||
data += BASE_PAGE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int in_obp_range(unsigned long vaddr)
|
||||
{
|
||||
return (vaddr >= LOW_OBP_ADDRESS &&
|
||||
vaddr < HI_OBP_ADDRESS);
|
||||
}
|
||||
|
||||
#define OBP_PMD_SIZE 2048
|
||||
static void __init build_obp_pgtable(void)
|
||||
static int cmp_ptrans(const void *a, const void *b)
|
||||
{
|
||||
unsigned long i;
|
||||
const struct linux_prom_translation *x = a, *y = b;
|
||||
|
||||
prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, PAGE_SIZE);
|
||||
if (!prompmd)
|
||||
prom_halt();
|
||||
|
||||
memset(prompmd, 0, OBP_PMD_SIZE);
|
||||
|
||||
prom_pmd_phys = __pa(prompmd);
|
||||
|
||||
for (i = 0; i < prom_trans_ents; i++) {
|
||||
unsigned long start, end;
|
||||
|
||||
if (!in_obp_range(prom_trans[i].virt))
|
||||
continue;
|
||||
|
||||
start = prom_trans[i].virt;
|
||||
end = start + prom_trans[i].size;
|
||||
if (end > HI_OBP_ADDRESS)
|
||||
end = HI_OBP_ADDRESS;
|
||||
|
||||
build_obp_range(start, end, prom_trans[i].data);
|
||||
}
|
||||
if (x->virt > y->virt)
|
||||
return 1;
|
||||
if (x->virt < y->virt)
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Read OBP translations property into 'prom_trans[]'.
|
||||
* Return the number of entries.
|
||||
*/
|
||||
/* Read OBP translations property into 'prom_trans[]'. */
|
||||
static void __init read_obp_translations(void)
|
||||
{
|
||||
int n, node;
|
||||
int n, node, ents, first, last, i;
|
||||
|
||||
node = prom_finddevice("/virtual-memory");
|
||||
n = prom_getproplen(node, "translations");
|
||||
@ -515,7 +453,41 @@ static void __init read_obp_translations(void)
|
||||
|
||||
n = n / sizeof(struct linux_prom_translation);
|
||||
|
||||
prom_trans_ents = n;
|
||||
ents = n;
|
||||
|
||||
sort(prom_trans, ents, sizeof(struct linux_prom_translation),
|
||||
cmp_ptrans, NULL);
|
||||
|
||||
/* Now kick out all the non-OBP entries. */
|
||||
for (i = 0; i < ents; i++) {
|
||||
if (in_obp_range(prom_trans[i].virt))
|
||||
break;
|
||||
}
|
||||
first = i;
|
||||
for (; i < ents; i++) {
|
||||
if (!in_obp_range(prom_trans[i].virt))
|
||||
break;
|
||||
}
|
||||
last = i;
|
||||
|
||||
for (i = 0; i < (last - first); i++) {
|
||||
struct linux_prom_translation *src = &prom_trans[i + first];
|
||||
struct linux_prom_translation *dest = &prom_trans[i];
|
||||
|
||||
*dest = *src;
|
||||
}
|
||||
for (; i < ents; i++) {
|
||||
struct linux_prom_translation *dest = &prom_trans[i];
|
||||
dest->virt = dest->size = dest->data = 0x0UL;
|
||||
}
|
||||
|
||||
prom_trans_ents = last - first;
|
||||
|
||||
if (tlb_type == spitfire) {
|
||||
/* Clear diag TTE bits. */
|
||||
for (i = 0; i < prom_trans_ents; i++)
|
||||
prom_trans[i].data &= ~0x0003fe0000000000UL;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init remap_kernel(void)
|
||||
@ -553,21 +525,18 @@ static void __init remap_kernel(void)
|
||||
}
|
||||
|
||||
|
||||
static void __init inherit_prom_mappings_pre(void)
|
||||
static void __init inherit_prom_mappings(void)
|
||||
{
|
||||
read_obp_translations();
|
||||
|
||||
/* Now fixup OBP's idea about where we really are mapped. */
|
||||
prom_printf("Remapping the kernel... ");
|
||||
remap_kernel();
|
||||
|
||||
prom_printf("done.\n");
|
||||
}
|
||||
|
||||
static void __init inherit_prom_mappings_post(void)
|
||||
{
|
||||
build_obp_pgtable();
|
||||
prom_printf("Registering callbacks... ");
|
||||
register_prom_callbacks();
|
||||
prom_printf("done.\n");
|
||||
}
|
||||
|
||||
/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
|
||||
@ -1519,7 +1488,7 @@ void __init paging_init(void)
|
||||
|
||||
swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
|
||||
|
||||
inherit_prom_mappings_pre();
|
||||
inherit_prom_mappings();
|
||||
|
||||
/* Ok, we can use our TLB miss and window trap handlers safely.
|
||||
* We need to do a quick peek here to see if we are on StarFire
|
||||
@ -1530,23 +1499,15 @@ void __init paging_init(void)
|
||||
extern void setup_tba(int);
|
||||
setup_tba(this_is_starfire);
|
||||
}
|
||||
__flush_tlb_all();
|
||||
|
||||
/* Everything from this point forward, until we are done with
|
||||
* inherit_prom_mappings_post(), must complete successfully
|
||||
* without calling into the firmware. The firwmare page tables
|
||||
* have not been built, but we are running on the Linux kernel's
|
||||
* trap table.
|
||||
*/
|
||||
inherit_locked_prom_mappings(1);
|
||||
|
||||
__flush_tlb_all();
|
||||
|
||||
/* Setup bootmem... */
|
||||
pages_avail = 0;
|
||||
last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
|
||||
|
||||
inherit_prom_mappings_post();
|
||||
|
||||
inherit_locked_prom_mappings(1);
|
||||
|
||||
#ifdef CONFIG_DEBUG_PAGEALLOC
|
||||
kernel_physical_mapping_init();
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user