forked from luck/tmp_suning_uos_patched
dma-mapping: add (back) arch_dma_mark_clean for ia64
Add back a hook to optimize dcache flushing after reading executable code using DMA. This gets ia64 out of the business of pretending to be dma incoherent just for this optimization. Signed-off-by: Christoph Hellwig <hch@lst.de>
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@ -8,6 +8,7 @@ menu "Processor type and features"
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config IA64
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bool
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select ARCH_HAS_DMA_MARK_CLEAN
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select ARCH_MIGHT_HAVE_PC_PARPORT
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select ARCH_MIGHT_HAVE_PC_SERIO
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select ACPI
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@ -32,8 +33,6 @@ config IA64
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select TTY
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select HAVE_ARCH_TRACEHOOK
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select HAVE_VIRT_CPU_ACCOUNTING
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select DMA_NONCOHERENT_MMAP
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select VIRT_TO_BUS
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select GENERIC_IRQ_PROBE
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select GENERIC_PENDING_IRQ if SMP
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/dma-direct.h>
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#include <linux/dma-mapping.h>
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#include <linux/export.h>
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/* Set this to 1 if there is a HW IOMMU in the system */
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@ -7,15 +7,3 @@ int iommu_detected __read_mostly;
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const struct dma_map_ops *dma_ops;
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EXPORT_SYMBOL(dma_ops);
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void *arch_dma_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
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{
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return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs);
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}
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void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_addr, unsigned long attrs)
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{
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dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);
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}
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@ -73,8 +73,7 @@ __ia64_sync_icache_dcache (pte_t pte)
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* DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to
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* flush them when they get mapped into an executable vm-area.
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*/
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void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
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enum dma_data_direction dir)
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void arch_dma_mark_clean(phys_addr_t paddr, size_t size)
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{
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unsigned long pfn = PHYS_PFN(paddr);
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@ -150,6 +150,9 @@ static inline void dma_direct_sync_single_for_cpu(struct device *dev,
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if (unlikely(is_swiotlb_buffer(paddr)))
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swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU);
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if (dir == DMA_FROM_DEVICE)
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arch_dma_mark_clean(paddr, size);
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}
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static inline dma_addr_t dma_direct_map_page(struct device *dev,
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@ -108,6 +108,14 @@ static inline void arch_dma_prep_coherent(struct page *page, size_t size)
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}
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#endif /* CONFIG_ARCH_HAS_DMA_PREP_COHERENT */
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#ifdef CONFIG_ARCH_HAS_DMA_MARK_CLEAN
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void arch_dma_mark_clean(phys_addr_t paddr, size_t size);
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#else
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static inline void arch_dma_mark_clean(phys_addr_t paddr, size_t size)
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{
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}
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#endif /* ARCH_HAS_DMA_MARK_CLEAN */
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void *arch_dma_set_uncached(void *addr, size_t size);
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void arch_dma_clear_uncached(void *addr, size_t size);
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@ -44,6 +44,12 @@ config ARCH_HAS_DMA_SET_MASK
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config ARCH_HAS_DMA_WRITE_COMBINE
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bool
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#
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# Select if the architectures provides the arch_dma_mark_clean hook
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#
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config ARCH_HAS_DMA_MARK_CLEAN
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bool
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config DMA_DECLARE_COHERENT
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bool
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@ -345,6 +345,9 @@ void dma_direct_sync_sg_for_cpu(struct device *dev,
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if (unlikely(is_swiotlb_buffer(paddr)))
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swiotlb_tbl_sync_single(dev, paddr, sg->length, dir,
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SYNC_FOR_CPU);
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if (dir == DMA_FROM_DEVICE)
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arch_dma_mark_clean(paddr, sg->length);
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}
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if (!dev_is_dma_coherent(dev))
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