forked from luck/tmp_suning_uos_patched
MIPS: detect presence of the FRE & UFR bits
Detect the presence of the Config5 FRE & UFE bits, as indicated by the FREP bit in FPIR. Record this as a CPU option bit, and provide a cpu_has_fre macro to ease checking of that option bit. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7678/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -344,4 +344,8 @@
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# define cpu_has_msa 0
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#endif
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#ifndef cpu_has_fre
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# define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
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#endif
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#endif /* __ASM_CPU_FEATURES_H */
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@ -368,6 +368,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
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#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
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#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
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#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
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/*
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* CPU ASE encodings
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@ -1317,6 +1317,8 @@ void cpu_probe(void)
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MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
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if (c->fpu_id & MIPS_FPIR_3D)
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c->ases |= MIPS_ASE_MIPS3D;
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if (c->fpu_id & MIPS_FPIR_FREP)
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c->options |= MIPS_CPU_FRE;
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}
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}
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