forked from luck/tmp_suning_uos_patched
Merge branch 'fixes' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm bugfixes from Gleb Natapov: "There is one more fix for MIPS KVM ABI here, MIPS and PPC build breakage fixes and a couple of PPC bug fixes" * 'fixes' of git://git.kernel.org/pub/scm/virt/kvm/kvm: kvm/ppc/booke64: Fix lazy ee handling in kvmppc_handle_exit() kvm/ppc/booke: Hold srcu lock when calling gfn functions kvm/ppc/booke64: Disable e6500 support kvm/ppc/booke64: Fix AltiVec interrupt numbers and build breakage mips/kvm: Use KVM_REG_MIPS and proper size indicators for *_ONE_REG kvm: Add definition of KVM_REG_MIPS KVM: add kvm_para_available to asm-generic/kvm_para.h
This commit is contained in:
Linus Torvalds
commit
af180b81a3
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@ -58,56 +58,53 @@ struct kvm_fpu {
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* bits[2..0] - Register 'sel' index.
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* bits[7..3] - Register 'rd' index.
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* bits[15..8] - Must be zero.
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* bits[63..16] - 1 -> CP0 registers.
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* bits[31..16] - 1 -> CP0 registers.
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* bits[51..32] - Must be zero.
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* bits[63..52] - As per linux/kvm.h
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*
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* Other sets registers may be added in the future. Each set would
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* have its own identifier in bits[63..16].
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*
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* The addr field of struct kvm_one_reg must point to an aligned
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* 64-bit wide location. For registers that are narrower than
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* 64-bits, the value is stored in the low order bits of the location,
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* and sign extended to 64-bits.
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* have its own identifier in bits[31..16].
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*
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* The registers defined in struct kvm_regs are also accessible, the
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* id values for these are below.
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*/
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#define KVM_REG_MIPS_R0 0
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#define KVM_REG_MIPS_R1 1
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#define KVM_REG_MIPS_R2 2
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#define KVM_REG_MIPS_R3 3
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#define KVM_REG_MIPS_R4 4
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#define KVM_REG_MIPS_R5 5
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#define KVM_REG_MIPS_R6 6
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#define KVM_REG_MIPS_R7 7
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#define KVM_REG_MIPS_R8 8
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#define KVM_REG_MIPS_R9 9
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#define KVM_REG_MIPS_R10 10
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#define KVM_REG_MIPS_R11 11
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#define KVM_REG_MIPS_R12 12
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#define KVM_REG_MIPS_R13 13
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#define KVM_REG_MIPS_R14 14
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#define KVM_REG_MIPS_R15 15
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#define KVM_REG_MIPS_R16 16
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#define KVM_REG_MIPS_R17 17
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#define KVM_REG_MIPS_R18 18
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#define KVM_REG_MIPS_R19 19
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#define KVM_REG_MIPS_R20 20
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#define KVM_REG_MIPS_R21 21
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#define KVM_REG_MIPS_R22 22
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#define KVM_REG_MIPS_R23 23
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#define KVM_REG_MIPS_R24 24
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#define KVM_REG_MIPS_R25 25
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#define KVM_REG_MIPS_R26 26
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#define KVM_REG_MIPS_R27 27
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#define KVM_REG_MIPS_R28 28
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#define KVM_REG_MIPS_R29 29
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#define KVM_REG_MIPS_R30 30
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#define KVM_REG_MIPS_R31 31
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#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
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#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
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#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
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#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
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#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
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#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
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#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
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#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
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#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
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#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
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#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
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#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
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#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
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#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
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#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
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#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
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#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
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#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
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#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
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#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
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#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
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#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
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#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
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#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
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#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
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#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
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#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
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#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
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#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
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#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
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#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
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#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
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#define KVM_REG_MIPS_HI 32
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#define KVM_REG_MIPS_LO 33
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#define KVM_REG_MIPS_PC 34
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#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
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#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
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#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
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/*
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* KVM MIPS specific structures and definitions
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@ -485,29 +485,35 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
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return -ENOIOCTLCMD;
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}
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#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0)
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#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0)
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#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2)
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#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0)
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#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1)
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#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0)
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#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0)
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#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0)
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#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0)
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#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0)
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#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0)
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#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0)
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#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0)
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#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1)
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#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0)
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#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1)
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#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2)
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#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3)
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#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7)
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#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0)
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#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0)
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#define MIPS_CP0_32(_R, _S) \
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(KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
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#define MIPS_CP0_64(_R, _S) \
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(KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
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#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
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#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
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#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
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#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
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#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
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#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
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#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
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#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
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#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
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#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
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#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
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#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
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#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
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#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
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#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
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#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
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#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
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#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
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#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
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#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
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#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
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static u64 kvm_mips_get_one_regs[] = {
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KVM_REG_MIPS_R0,
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@ -567,8 +573,6 @@ static u64 kvm_mips_get_one_regs[] = {
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static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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u64 __user *uaddr = (u64 __user *)(long)reg->addr;
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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s64 v;
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@ -631,18 +635,39 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
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default:
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return -EINVAL;
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}
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return put_user(v, uaddr);
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if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
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u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
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return put_user(v, uaddr64);
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} else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
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u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
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u32 v32 = (u32)v;
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return put_user(v32, uaddr32);
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} else {
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return -EINVAL;
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}
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}
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static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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u64 __user *uaddr = (u64 __user *)(long)reg->addr;
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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u64 v;
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if (get_user(v, uaddr) != 0)
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return -EFAULT;
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if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
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u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
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if (get_user(v, uaddr64) != 0)
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return -EFAULT;
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} else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
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u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
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s32 v32;
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if (get_user(v32, uaddr32) != 0)
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return -EFAULT;
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v = (s64)v32;
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} else {
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return -EINVAL;
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}
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switch (reg->id) {
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case KVM_REG_MIPS_R0:
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@ -54,8 +54,16 @@
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#define BOOKE_INTERRUPT_DEBUG 15
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/* E500 */
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#define BOOKE_INTERRUPT_SPE_UNAVAIL 32
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#define BOOKE_INTERRUPT_SPE_FP_DATA 33
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#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
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#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
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/*
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* TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
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*/
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#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
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#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
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#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
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#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
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BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
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#define BOOKE_INTERRUPT_SPE_FP_ROUND 34
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#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
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#define BOOKE_INTERRUPT_DOORBELL 36
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@ -67,10 +75,6 @@
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#define BOOKE_INTERRUPT_HV_SYSCALL 40
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#define BOOKE_INTERRUPT_HV_PRIV 41
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/* altivec */
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#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
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#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
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/* book3s */
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#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
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@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
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struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
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struct kvmppc_44x_tlbe *tlbe;
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unsigned int gtlb_index;
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int idx;
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gtlb_index = kvmppc_get_gpr(vcpu, ra);
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if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
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@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
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return EMULATE_FAIL;
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}
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idx = srcu_read_lock(&vcpu->kvm->srcu);
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if (tlbe_is_host_safe(vcpu, tlbe)) {
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gva_t eaddr;
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gpa_t gpaddr;
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@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
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kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
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}
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srcu_read_unlock(&vcpu->kvm->srcu, idx);
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trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
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tlbe->word2);
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|
|
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@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
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{
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int r = RESUME_HOST;
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int s;
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int idx;
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#ifdef CONFIG_PPC64
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WARN_ON(local_paca->irq_happened != 0);
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#endif
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/*
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* We enter with interrupts disabled in hardware, but
|
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* we need to call hard_irq_disable anyway to ensure that
|
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* the software state is kept in sync.
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*/
|
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hard_irq_disable();
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/* update before a new last_exit_type is rewritten */
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kvmppc_update_timing_stats(vcpu);
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|
|
@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
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break;
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}
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idx = srcu_read_lock(&vcpu->kvm->srcu);
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gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
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gfn = gpaddr >> PAGE_SHIFT;
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|
@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
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kvmppc_account_exit(vcpu, MMIO_EXITS);
|
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}
|
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srcu_read_unlock(&vcpu->kvm->srcu, idx);
|
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break;
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}
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|
|
@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
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kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
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idx = srcu_read_lock(&vcpu->kvm->srcu);
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|
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gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
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gfn = gpaddr >> PAGE_SHIFT;
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|
|
@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
|
|||
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
|
||||
}
|
||||
|
||||
srcu_read_unlock(&vcpu->kvm->srcu, idx);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
|
|||
struct kvm_book3e_206_tlb_entry *gtlbe;
|
||||
int tlbsel, esel;
|
||||
int recal = 0;
|
||||
int idx;
|
||||
|
||||
tlbsel = get_tlb_tlbsel(vcpu);
|
||||
esel = get_tlb_esel(vcpu, tlbsel);
|
||||
|
|
@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
|
|||
kvmppc_set_tlb1map_range(vcpu, gtlbe);
|
||||
}
|
||||
|
||||
idx = srcu_read_lock(&vcpu->kvm->srcu);
|
||||
|
||||
/* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
|
||||
if (tlbe_is_host_safe(vcpu, gtlbe)) {
|
||||
u64 eaddr = get_tlb_eaddr(gtlbe);
|
||||
|
|
@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
|
|||
kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
|
||||
}
|
||||
|
||||
srcu_read_unlock(&vcpu->kvm->srcu, idx);
|
||||
|
||||
kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
|
||||
return EMULATE_DONE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void)
|
|||
r = 0;
|
||||
else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
|
||||
r = 0;
|
||||
else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
|
||||
r = 0;
|
||||
else
|
||||
r = -ENOTSUPP;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,4 +18,9 @@ static inline unsigned int kvm_arch_para_features(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline bool kvm_para_available(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -783,6 +783,7 @@ struct kvm_dirty_tlb {
|
|||
#define KVM_REG_IA64 0x3000000000000000ULL
|
||||
#define KVM_REG_ARM 0x4000000000000000ULL
|
||||
#define KVM_REG_S390 0x5000000000000000ULL
|
||||
#define KVM_REG_MIPS 0x7000000000000000ULL
|
||||
|
||||
#define KVM_REG_SIZE_SHIFT 52
|
||||
#define KVM_REG_SIZE_MASK 0x00f0000000000000ULL
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user