forked from luck/tmp_suning_uos_patched
clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when the DIS power domain is during up-powergating process but the clamp to this domain is not removed yet. That causes a timeout and aborts the power sequence, although the PLLD/PLLD2 has already locked. To remove the false alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the clocks as locked. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -428,7 +428,7 @@ static struct tegra_clk_pll_params pll_d_params = {
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.div_nmp = &pllp_nmp,
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.freq_table = pll_d_freq_table,
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.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
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TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
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TEGRA_PLL_HAS_LOCK_ENABLE,
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};
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static struct tegra_clk_pll_params pll_d2_params = {
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@ -446,7 +446,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
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.div_nmp = &pllp_nmp,
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.freq_table = pll_d_freq_table,
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.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
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TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
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TEGRA_PLL_HAS_LOCK_ENABLE,
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};
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static const struct pdiv_map pllu_p[] = {
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