forked from luck/tmp_suning_uos_patched
ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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4a2e32794e
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@ -25,6 +25,7 @@
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#include "flowctrl.h"
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#include "iomap.h"
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#include "fuse.h"
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static u8 flowctrl_offset_halt_cpu[] = {
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FLOW_CTRL_HALT_CPU0_EVENTS,
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@ -75,11 +76,26 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
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int i;
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reg = flowctrl_read_cpu_csr(cpuid);
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
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switch (tegra_chip_id) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfe */
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reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
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break;
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case TEGRA30:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfi */
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reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
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break;
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}
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
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reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; /* pwr gating on wfi */
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reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
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flowctrl_write_cpu_csr(cpuid, reg);
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@ -99,8 +115,20 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
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/* Disable powergating via flow controller for CPU0 */
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reg = flowctrl_read_cpu_csr(cpuid);
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
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switch (tegra_chip_id) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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case TEGRA30:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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}
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reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
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@ -34,6 +34,10 @@
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#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTRL_CPU1_CSR 0x18
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#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
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#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
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#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
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#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
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#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
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#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
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