forked from luck/tmp_suning_uos_patched
clk: imx: Correct the root clk of media ldb on imx8mp
The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -375,10 +375,10 @@ static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_2
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"sys_pll3_out", "audio_pll2_out",
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"video_pll1_out", };
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static const char * const imx8mp_media_mipi_phy2_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
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"sys_pll1_800m", "sys_pll2_1000m",
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"clk_ext2", "audio_pll2_out",
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"video_pll1_out", };
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static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
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"sys_pll1_800m", "sys_pll2_1000m",
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"clk_ext2", "audio_pll2_out",
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"video_pll1_out", };
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static const char * const imx8mp_media_mipi_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
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"sys_pll1_800m", "sys_pll2_1000m",
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@ -647,7 +647,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
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hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
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hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00);
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hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
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hws[IMX8MP_CLK_MEDIA_MIPI_PHY2_REF] = imx8m_clk_hw_composite("media_mipi_phy2_ref", imx8mp_media_mipi_phy2_ref_sels, ccm_base + 0xbf00);
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hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
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hws[IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC] = imx8m_clk_hw_composite("media_mipi_csi2_esc", imx8mp_media_mipi_csi2_esc_sels, ccm_base + 0xbf80);
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hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
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hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
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@ -180,7 +180,7 @@
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#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
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#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
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#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
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#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174
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#define IMX8MP_CLK_MEDIA_LDB 174
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#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
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#define IMX8MP_CLK_PCIE2_CTRL 176
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#define IMX8MP_CLK_PCIE2_PHY 177
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